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OpenRAM
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fix bl in stim file

This commit is contained in:
jcirimel 2020-01-21 01:44:15 -08:00
parent 73691f6054
commit 40c01dab85
4 changed files with 41 additions and 20 deletions
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16
compiler/characterizer/delay.py
View File

@ -302,10 +302,9 @@ class delay(simulation):
exclude_set = self.get_bl_name_search_exclusions()
for int_net in [cell_bl, cell_br]:
bl_names.append(self.get_alias_in_path(paths, int_net, cell_mod, exclude_set))
#if OPTS.use_pex:
# bank_num = 0
# bl_names[0] = "bl_b{0}_{1}".format(bank_num, )
# bl_names[1] = "br_b{0}_{1}".format(bank_num, )
if OPTS.use_pex:
for i in range(len(bl_names)):
bl_names[i] = bl_names[i].split('.')[-1]
return bl_names[0], bl_names[1]
@ -396,8 +395,13 @@ class delay(simulation):
# instantiate the sram
self.sf.write("\n* Instantiation of the SRAM\n")
self.stim.inst_model(pins=self.pins,
model_name=self.sram.name)
if not OPTS.use_pex:
self.stim.inst_model(pins=self.pins,
model_name=self.sram.name)
else:
self.stim.inst_sram_pex(pins=self.pins,
model_name=self.sram.name)
self.sf.write("\n* SRAM output loads\n")
for port in self.read_ports:
for i in range(self.word_size):

29
compiler/characterizer/stimuli.py
View File

@ -51,18 +51,27 @@ class stimuli():
self.sf.write("X{0} ".format(model_name))
for pin in pins:
self.sf.write("{0} ".format(pin))
if OPTS.use_pex:
for bank in range(OPTS.num_banks):
for row in range(OPTS.num_words):
for col in range(OPTS.word_size):
self.sf.write("bitcell_Q_b{0}_r{1}_c{2} ".format(bank,row,col))
self.sf.write("bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank,row,col))
for col in range(OPTS.word_size):
self.sf.write("bl_b{0}_c{2} ".format(bank, row,col))
self.sf.write("br_b{0}_c{2} ".format(bank, row,col))
self.sf.write("s_en{0} ".format(bank))
self.sf.write("{0}\n".format(model_name))
def inst_sram_pex(self, pins, model_name):
self.sf.write("X{0} ".format(model_name))
for pin in pins:
self.sf.write("{0} ".format(pin))
for bank in range(OPTS.num_banks):
for row in range(OPTS.num_words):
for col in range(OPTS.word_size):
self.sf.write("bitcell_Q_b{0}_r{1}_c{2} ".format(bank,row,col))
self.sf.write("bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank,row,col))
for col in range(OPTS.word_size):
if OPTS.num_banks == 1:
self.sf.write("bl_{2} ".format(bank, row,col))
self.sf.write("br_{2} ".format(bank, row,col))
else:
self.sf.write("bl{0}_{2} ".format(bank, row,col))
self.sf.write("br{0}_{2} ".format(bank, row,col))
self.sf.write("s_en{0} ".format(bank))
self.sf.write("{0}\n".format(model_name))
def create_inverter(self, size=1, beta=2.5):
""" Generates inverter for the top level signals (only for sim purposes) """

8
compiler/sram/sram_base.py
View File

@ -115,8 +115,12 @@ class sram_base(design, verilog, lef):
self.add_layout_pin_rect_center("bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , storage_layer_name, Q)
self.add_layout_pin_rect_center("bitcell_Q_bar_b{0}_r{1}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), storage_layer_name, Q_bar)
self.add_layout_pin_rect_center("bl_b{0}_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , bitline_layer_name, bl)
self.add_layout_pin_rect_center("br_b{0}_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), bitline_layer_name, br)
if OPTS.num_banks == 1:
self.add_layout_pin_rect_center("bl_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , bitline_layer_name, bl)
self.add_layout_pin_rect_center("br_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), bitline_layer_name, br)
else:
self.add_layout_pin_rect_center("bl{0}_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , bitline_layer_name, bl)
self.add_layout_pin_rect_center("br{0}_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), bitline_layer_name, br)

8
compiler/verify/magic.py
View File

@ -420,8 +420,12 @@ def correct_port(name, output_file_name, ref_file_name):
bitcell_list += "bitcell_Q_b{0}_r{1}_c{2} ".format(bank, row,col)
bitcell_list += "bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank, row,col)
for col in range(OPTS.word_size):
bitcell_list += "bl_b{0}_c{2} ".format(bank, row,col)
bitcell_list += "br_b{0}_c{2} ".format(bank, row,col)
if OPTS.num_banks == 1:
bitcell_list += "bl_{2} ".format(bank, row,col)
bitcell_list += "br_{2} ".format(bank, row,col)
else:
bitcell_list += "bl{0}_{2} ".format(bank, row,col)
bitcell_list += "br{0}_{2} ".format(bank, row,col)
bitcell_list += "\n"
control_list = "+ "