mirror of https://github.com/VLSIDA/OpenRAM.git
fix s_en in stim
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parent
075bf0d841
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364842569a
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@ -286,7 +286,7 @@ class delay(simulation):
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enable_name = sa_mods[0].get_enable_name()
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sen_name = self.get_alias_in_path(paths, enable_name, sa_mods[0])
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if OPTS.use_pex:
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#get sense amp multi bank
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sen_name = sen_name.split('.')[-1]
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return sen_name
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def get_bl_name(self, paths, port):
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@ -480,7 +480,7 @@ class sram_1bank(sram_base):
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debug.error("Signal={} not contained in control logic connections={}"\
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.format(sen_name, control_conns))
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if sen_name in self.pins:
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debug.error("Internal signal={} contained in port list. Name defined by the parent.")
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debug.error("Internal signal={} contained in port list. Name defined by the parent.")
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return "X{}.{}".format(sram_name, sen_name)
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def get_cell_name(self, inst_name, row, col):
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