mirror of https://github.com/VLSIDA/OpenRAM.git
Merge branch 'dev' into analytical_cleanup
This commit is contained in:
Hunter Nichols
commit
d273c0eef5
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@ -84,8 +84,6 @@ class bank(design.design):
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self.add_pin("dout{0}_{1}".format(port,bit),"OUTPUT")
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for port in self.read_ports:
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self.add_pin(self.bitcell_array.get_rbl_bl_name(self.port_rbl_map[port]),"OUTPUT")
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for port in self.read_ports:
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self.add_pin(self.bitcell_array.get_rbl_wl_name(self.port_rbl_map[port]),"INPUT")
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for port in self.write_ports:
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for bit in range(self.word_size):
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self.add_pin("din{0}_{1}".format(port,bit),"INPUT")
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@ -306,13 +304,13 @@ class bank(design.design):
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self.input_control_signals = []
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port_num = 0
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for port in range(OPTS.num_rw_ports):
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self.input_control_signals.append(["wl_en{}".format(port_num), "w_en{}".format(port_num), "s_en{}".format(port_num), "p_en_bar{}".format(port_num), "rbl_wl{}".format(port_num)])
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self.input_control_signals.append(["w_en{}".format(port_num), "s_en{}".format(port_num), "p_en_bar{}".format(port_num), "wl_en{}".format(port_num)])
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port_num += 1
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for port in range(OPTS.num_w_ports):
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self.input_control_signals.append(["wl_en{}".format(port_num), "w_en{}".format(port_num), "p_en_bar{}".format(port_num)])
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self.input_control_signals.append(["w_en{}".format(port_num), "p_en_bar{}".format(port_num), "wl_en{}".format(port_num)])
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port_num += 1
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for port in range(OPTS.num_r_ports):
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self.input_control_signals.append(["wl_en{}".format(port_num), "s_en{}".format(port_num), "p_en_bar{}".format(port_num), "rbl_wl{}".format(port_num)])
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self.input_control_signals.append(["s_en{}".format(port_num), "p_en_bar{}".format(port_num), "wl_en{}".format(port_num)])
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port_num += 1
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# Number of control lines in the bus for each port
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@ -422,9 +420,9 @@ class bank(design.design):
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for row in range(self.num_rows):
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for wordline in self.wl_names:
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temp.append("{0}_{1}".format(wordline,row))
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for rbl in range(self.num_rbl):
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rbl_wl_name=self.bitcell_array.get_rbl_wl_name(rbl)
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temp.append(rbl_wl_name)
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for port in self.all_ports:
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if self.port_data[port].has_rbl():
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temp.append("wl_en{0}".format(port))
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temp.append("vdd")
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temp.append("gnd")
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self.connect_inst(temp)
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@ -947,7 +945,7 @@ class bank(design.design):
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if port in self.read_ports:
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rbl_wl_name = self.bitcell_array.get_rbl_wl_name(self.port_rbl_map[port])
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connection.append((self.prefix+"rbl_wl{}".format(port), self.bitcell_array_inst.get_pin(rbl_wl_name).lc()))
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connection.append((self.prefix+"wl_en{}".format(port), self.bitcell_array_inst.get_pin(rbl_wl_name).lc()))
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if port in self.write_ports:
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connection.append((self.prefix+"w_en{}".format(port), self.port_data_inst[port].get_pin("w_en").lc()))
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@ -967,10 +965,10 @@ class bank(design.design):
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control_signal = self.prefix+"wl_en{}".format(port)
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if port%2:
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pin_pos = self.port_address_inst[port].get_pin("wl_en").uc()
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mid_pos = pin_pos + vector(0,self.m2_gap) # to route down to the top of the bus
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mid_pos = pin_pos + vector(0,2*self.m2_gap) # to route down to the top of the bus
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else:
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pin_pos = self.port_address_inst[port].get_pin("wl_en").bc()
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mid_pos = pin_pos - vector(0,self.m2_gap) # to route down to the top of the bus
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mid_pos = pin_pos - vector(0,2*self.m2_gap) # to route down to the top of the bus
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control_x_offset = self.bus_xoffset[port][control_signal].x
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control_pos = vector(control_x_offset, mid_pos.y)
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self.add_wire(("metal1","via1","metal2"),[pin_pos, mid_pos, control_pos])
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@ -101,17 +101,23 @@ class control_logic(design.design):
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self.add_mod(self.rbl_driver)
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# clk_buf drives a flop for every address and control bit
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# clk_buf drives a flop for every address
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addr_flops = math.log(self.num_words,2) + math.log(self.words_per_row,2)
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# plus data flops and control flops
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num_flops = addr_flops + self.word_size + self.num_control_signals
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# each flop internally has a FO 5 approximately
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# plus about 5 fanouts for the control logic
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# each flop internally has a FO 4 approximately
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clock_fanout = 4*(math.log(self.num_words,2) + math.log(self.words_per_row,2) \
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+ self.num_control_signals) + 5
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clock_fanout = 5*num_flops + 5
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self.clk_buf_driver = factory.create(module_type="pdriver",
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fanout=clock_fanout,
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height=dff_height)
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self.add_mod(self.clk_buf_driver)
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# We will use the maximum since this same value is used to size the wl_en
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# and the p_en_bar drivers
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max_fanout = max(self.num_rows,self.num_cols)
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# wl_en drives every row in the bank
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self.wl_en_driver = factory.create(module_type="pdriver",
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fanout=self.num_rows,
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@ -132,14 +138,16 @@ class control_logic(design.design):
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# used to generate inverted signals with low fanout
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self.inv = factory.create(module_type="pinv",
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size=1,
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height=dff_height)
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size=1,
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height=dff_height)
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self.add_mod(self.inv)
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# p_en_bar drives every column in the bitcell array
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# but it is sized the same as the wl_en driver with
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# prepended 3 inverter stages to guarantee it is slower and odd polarity
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self.p_en_bar_driver = factory.create(module_type="pdriver",
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neg_polarity=True,
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fanout=self.num_cols,
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neg_polarity=True,
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height=dff_height)
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self.add_mod(self.p_en_bar_driver)
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@ -346,9 +354,9 @@ class control_logic(design.design):
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# Outputs to the bank
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if self.port_type == "rw":
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self.output_list = ["rbl_wl", "s_en", "w_en"]
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self.output_list = ["s_en", "w_en"]
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elif self.port_type == "r":
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self.output_list = ["rbl_wl", "s_en"]
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self.output_list = ["s_en"]
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else:
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self.output_list = ["w_en"]
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self.output_list.append("p_en_bar")
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@ -376,7 +384,6 @@ class control_logic(design.design):
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if (self.port_type == "rw") or (self.port_type == "w"):
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self.create_wen_row()
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if (self.port_type == "rw") or (self.port_type == "r"):
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self.create_rbl_row()
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self.create_sen_row()
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self.create_delay()
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self.create_pen_row()
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@ -410,9 +417,6 @@ class control_logic(design.design):
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height = self.w_en_gate_inst.uy()
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control_center_y = self.w_en_gate_inst.uy()
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row += 1
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if (self.port_type == "rw") or (self.port_type == "r"):
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self.place_rbl_row(row)
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row += 1
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self.place_pen_row(row)
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row += 1
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if (self.port_type == "rw") or (self.port_type == "r"):
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@ -441,7 +445,6 @@ class control_logic(design.design):
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if (self.port_type == "rw") or (self.port_type == "w"):
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self.route_wen()
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if (self.port_type == "rw") or (self.port_type == "r"):
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self.route_rbl()
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self.route_sen()
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self.route_pen()
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self.route_clk_buf()
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@ -596,42 +599,15 @@ class control_logic(design.design):
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def route_wlen(self):
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wlen_map = zip(["A"], ["gated_clk_bar"])
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self.connect_vertical_bus(wlen_map, self.wl_en_inst, self.rail_offsets)
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self.connect_vertical_bus(wlen_map, self.wl_en_inst, self.rail_offsets)
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self.connect_output(self.wl_en_inst, "Z", "wl_en")
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def create_rbl_row(self):
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self.rbl_inst=self.add_inst(name="rbl_driver",
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mod=self.rbl_driver)
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# input: gated_clk_bar, output: rbl_wl
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self.connect_inst(["gated_clk_bar", "rbl_wl", "vdd", "gnd"])
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def place_rbl_row(self,row):
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x_off = self.control_x_offset
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(y_off,mirror)=self.get_offset(row)
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offset = vector(x_off, y_off)
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self.rbl_inst.place(offset, mirror)
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self.row_end_inst.append(self.rbl_inst)
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def route_rbl(self):
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""" Connect the logic for the rbl_in generation """
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rbl_in_map = zip(["A"], ["gated_clk_bar"])
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self.connect_vertical_bus(rbl_in_map, self.rbl_inst, self.rail_offsets)
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self.connect_output(self.rbl_inst, "Z", "rbl_wl")
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# Input from RBL goes to the delay line for futher delay
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self.copy_layout_pin(self.delay_inst, "in", "rbl_bl")
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def create_pen_row(self):
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input_name = "gated_clk_buf"
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# input: pre_p_en, output: p_en_bar
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# input: gated_clk_bar, output: p_en_bar
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self.p_en_bar_inst=self.add_inst(name="inv_p_en_bar",
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mod=self.p_en_bar_driver)
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self.connect_inst([input_name, "p_en_bar", "vdd", "gnd"])
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self.connect_inst(["gated_clk_buf", "p_en_bar", "vdd", "gnd"])
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def place_pen_row(self,row):
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@ -690,6 +666,10 @@ class control_logic(design.design):
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self.add_wire(("metal1","via1","metal2"),[out_pos, mid1,in_pos])
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self.connect_output(self.s_en_gate_inst, "Z", "s_en")
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# Input from RBL goes to the delay line for futher delay
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self.copy_layout_pin(self.delay_inst, "in", "rbl_bl")
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def create_wen_row(self):
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@ -0,0 +1,138 @@
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import debug
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from tech import drc
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from math import log
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from vector import vector
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from globals import OPTS
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import pgate
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from sram_factory import factory
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class pand3(pgate.pgate):
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"""
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This is a simple buffer used for driving loads.
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"""
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def __init__(self, name, size=1, height=None):
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debug.info(1, "Creating pand3 {}".format(name))
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self.add_comment("size: {}".format(size))
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self.size = size
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# Creates the netlist and layout
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pgate.pgate.__init__(self, name, height)
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def create_netlist(self):
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self.add_pins()
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self.create_modules()
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self.create_insts()
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def create_modules(self):
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# Shield the cap, but have at least a stage effort of 4
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self.nand = factory.create(module_type="pnand3",height=self.height)
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self.add_mod(self.nand)
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self.inv = factory.create(module_type="pinv", size=self.size, height=self.height)
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self.add_mod(self.inv)
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def create_layout(self):
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self.width = self.nand.width + self.inv.width
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self.place_insts()
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self.add_wires()
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self.add_layout_pins()
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self.DRC_LVS()
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def add_pins(self):
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self.add_pin("A", "INPUT")
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self.add_pin("B", "INPUT")
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self.add_pin("C", "INPUT")
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self.add_pin("Z", "OUTPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def create_insts(self):
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self.nand_inst=self.add_inst(name="pand3_nand",
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mod=self.nand)
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self.connect_inst(["A", "B", "C", "zb_int", "vdd", "gnd"])
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self.inv_inst=self.add_inst(name="pand3_inv",
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mod=self.inv)
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self.connect_inst(["zb_int", "Z", "vdd", "gnd"])
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def place_insts(self):
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# Add NAND to the right
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self.nand_inst.place(offset=vector(0,0))
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# Add INV to the right
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self.inv_inst.place(offset=vector(self.nand_inst.rx(),0))
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def add_wires(self):
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# nand Z to inv A
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z1_pin = self.nand_inst.get_pin("Z")
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a2_pin = self.inv_inst.get_pin("A")
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mid1_point = vector(0.5*(z1_pin.cx()+a2_pin.cx()), z1_pin.cy())
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mid2_point = vector(mid1_point, a2_pin.cy())
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self.add_path("metal1", [z1_pin.center(), mid1_point, mid2_point, a2_pin.center()])
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def add_layout_pins(self):
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# Continous vdd rail along with label.
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vdd_pin=self.inv_inst.get_pin("vdd")
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self.add_layout_pin(text="vdd",
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layer="metal1",
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offset=vdd_pin.ll().scale(0,1),
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width=self.width,
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height=vdd_pin.height())
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|
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# Continous gnd rail along with label.
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gnd_pin=self.inv_inst.get_pin("gnd")
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self.add_layout_pin(text="gnd",
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layer="metal1",
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offset=gnd_pin.ll().scale(0,1),
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width=self.width,
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height=vdd_pin.height())
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|
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pin = self.inv_inst.get_pin("Z")
|
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self.add_layout_pin_rect_center(text="Z",
|
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layer=pin.layer,
|
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offset=pin.center(),
|
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width=pin.width(),
|
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height=pin.height())
|
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|
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for pin_name in ["A","B", "C"]:
|
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pin = self.nand_inst.get_pin(pin_name)
|
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self.add_layout_pin_rect_center(text=pin_name,
|
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layer=pin.layer,
|
||||
offset=pin.center(),
|
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width=pin.width(),
|
||||
height=pin.height())
|
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|
||||
|
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|
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def analytical_delay(self, corner, slew, load=0.0):
|
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""" Calculate the analytical delay of DFF-> INV -> INV """
|
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nand_delay = self.nand.analytical_delay(corner, slew=slew, load=self.inv.input_load())
|
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inv_delay = self.inv.analytical_delay(corner, slew=nand_delay.slew, load=load)
|
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return nand_delay + inv_delay
|
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|
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def get_stage_efforts(self, external_cout, inp_is_rise=False):
|
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"""Get the stage efforts of the A or B -> Z path"""
|
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stage_effort_list = []
|
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stage1_cout = self.inv.get_cin()
|
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stage1 = self.nand.get_stage_effort(stage1_cout, inp_is_rise)
|
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stage_effort_list.append(stage1)
|
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last_stage_is_rise = stage1.is_rise
|
||||
|
||||
stage2 = self.inv.get_stage_effort(external_cout, last_stage_is_rise)
|
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stage_effort_list.append(stage2)
|
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|
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return stage_effort_list
|
||||
|
||||
def get_cin(self):
|
||||
"""Return the relative input capacitance of a single input"""
|
||||
return self.nand.get_cin()
|
||||
|
||||
|
|
@ -5,12 +5,13 @@
|
|||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
#
|
||||
import contact
|
||||
import pgate
|
||||
import debug
|
||||
from tech import drc, parameter, spice
|
||||
from vector import vector
|
||||
from globals import OPTS
|
||||
import contact
|
||||
import logical_effort
|
||||
from sram_factory import factory
|
||||
|
||||
class pnor2(pgate.pgate):
|
||||
|
|
@ -38,28 +39,30 @@ class pnor2(pgate.pgate):
|
|||
pgate.pgate.__init__(self, name, height)
|
||||
|
||||
|
||||
def add_pins(self):
|
||||
""" Adds pins for spice netlist """
|
||||
pin_list = ["A", "B", "Z", "vdd", "gnd"]
|
||||
dir_list = ["INPUT", "INPUT", "OUTPUT", "INOUT", "INOUT"]
|
||||
self.add_pin_list(pin_list, dir_list)
|
||||
|
||||
def create_netlist(self):
|
||||
self.add_pins()
|
||||
self.add_ptx()
|
||||
self.create_ptx()
|
||||
self.setup_layout_constants()
|
||||
|
||||
def create_layout(self):
|
||||
""" Calls all functions related to the generation of the layout """
|
||||
self.add_supply_rails()
|
||||
self.add_ptx()
|
||||
|
||||
self.setup_layout_constants()
|
||||
self.route_supply_rails()
|
||||
self.place_ptx()
|
||||
self.connect_rails()
|
||||
self.add_well_contacts()
|
||||
self.extend_wells(self.well_pos)
|
||||
self.route_inputs()
|
||||
self.route_output()
|
||||
|
||||
def create_ptx(self):
|
||||
def add_pins(self):
|
||||
""" Adds pins for spice netlist """
|
||||
pin_list = ["A", "B", "Z", "vdd", "gnd"]
|
||||
dir_list = ["INPUT", "INPUT", "OUTPUT", "INOUT", "INOUT"]
|
||||
self.add_pin_list(pin_list, dir_list)
|
||||
|
||||
def add_ptx(self):
|
||||
""" Create the PMOS and NMOS transistors. """
|
||||
self.nmos = factory.create(module_type="ptx",
|
||||
width=self.nmos_width,
|
||||
|
|
@ -104,7 +107,7 @@ class pnor2(pgate.pgate):
|
|||
self.top_bottom_space = max(0.5*self.m1_width + self.m1_space + extra_contact_space,
|
||||
drc("poly_extend_active"), self.poly_space)
|
||||
|
||||
def add_supply_rails(self):
|
||||
def route_supply_rails(self):
|
||||
""" Add vdd/gnd rails to the top and bottom. """
|
||||
self.add_layout_pin_rect_center(text="gnd",
|
||||
layer="metal1",
|
||||
|
|
@ -116,7 +119,31 @@ class pnor2(pgate.pgate):
|
|||
offset=vector(0.5*self.width,self.height),
|
||||
width=self.width)
|
||||
|
||||
def add_ptx(self):
|
||||
def create_ptx(self):
|
||||
"""
|
||||
Add PMOS and NMOS to the layout at the upper-most and lowest position
|
||||
to provide maximum routing in channel
|
||||
"""
|
||||
|
||||
self.pmos1_inst=self.add_inst(name="pnor2_pmos1",
|
||||
mod=self.pmos)
|
||||
self.connect_inst(["vdd", "A", "net1", "vdd"])
|
||||
|
||||
self.pmos2_inst = self.add_inst(name="pnor2_pmos2",
|
||||
mod=self.pmos)
|
||||
self.connect_inst(["net1", "B", "Z", "vdd"])
|
||||
|
||||
|
||||
self.nmos1_inst=self.add_inst(name="pnor2_nmos1",
|
||||
mod=self.nmos)
|
||||
self.connect_inst(["Z", "A", "gnd", "gnd"])
|
||||
|
||||
self.nmos2_inst=self.add_inst(name="pnor2_nmos2",
|
||||
mod=self.nmos)
|
||||
self.connect_inst(["Z", "B", "gnd", "gnd"])
|
||||
|
||||
|
||||
def place_ptx(self):
|
||||
"""
|
||||
Add PMOS and NMOS to the layout at the upper-most and lowest position
|
||||
to provide maximum routing in channel
|
||||
|
|
@ -124,29 +151,16 @@ class pnor2(pgate.pgate):
|
|||
|
||||
pmos1_pos = vector(self.pmos.active_offset.x,
|
||||
self.height - self.pmos.active_height - self.top_bottom_space)
|
||||
self.pmos1_inst=self.add_inst(name="pnor2_pmos1",
|
||||
mod=self.pmos,
|
||||
offset=pmos1_pos)
|
||||
self.connect_inst(["vdd", "A", "net1", "vdd"])
|
||||
self.pmos1_inst.place(pmos1_pos)
|
||||
|
||||
self.pmos2_pos = pmos1_pos + self.overlap_offset
|
||||
self.pmos2_inst = self.add_inst(name="pnor2_pmos2",
|
||||
mod=self.pmos,
|
||||
offset=self.pmos2_pos)
|
||||
self.connect_inst(["net1", "B", "Z", "vdd"])
|
||||
|
||||
self.pmos2_inst.place(self.pmos2_pos)
|
||||
|
||||
nmos1_pos = vector(self.pmos.active_offset.x, self.top_bottom_space)
|
||||
self.nmos1_inst=self.add_inst(name="pnor2_nmos1",
|
||||
mod=self.nmos,
|
||||
offset=nmos1_pos)
|
||||
self.connect_inst(["Z", "A", "gnd", "gnd"])
|
||||
|
||||
self.nmos1_inst.place(nmos1_pos)
|
||||
|
||||
self.nmos2_pos = nmos1_pos + self.overlap_offset
|
||||
self.nmos2_inst=self.add_inst(name="pnor2_nmos2",
|
||||
mod=self.nmos,
|
||||
offset=self.nmos2_pos)
|
||||
self.connect_inst(["Z", "B", "gnd", "gnd"])
|
||||
self.nmos2_inst.place(self.nmos2_pos)
|
||||
|
||||
# Output position will be in between the PMOS and NMOS
|
||||
self.output_pos = vector(0,0.5*(pmos1_pos.y+nmos1_pos.y+self.nmos.active_height))
|
||||
|
|
|
|||
|
|
@ -341,8 +341,6 @@ class sram_base(design, verilog, lef):
|
|||
temp.append("DOUT{0}[{1}]".format(port,bit))
|
||||
for port in self.read_ports:
|
||||
temp.append("rbl_bl{0}".format(port))
|
||||
for port in self.read_ports:
|
||||
temp.append("rbl_wl{0}".format(port))
|
||||
for port in self.write_ports:
|
||||
for bit in range(self.word_size):
|
||||
temp.append("BANK_DIN{0}[{1}]".format(port,bit))
|
||||
|
|
@ -506,9 +504,6 @@ class sram_base(design, verilog, lef):
|
|||
temp.append("rbl_bl{}".format(port))
|
||||
|
||||
# Ouputs
|
||||
if port in self.read_ports:
|
||||
temp.append("rbl_wl{}".format(port))
|
||||
|
||||
if port in self.read_ports:
|
||||
temp.append("s_en{}".format(port))
|
||||
if port in self.write_ports:
|
||||
|
|
@ -530,7 +525,10 @@ class sram_base(design, verilog, lef):
|
|||
in_pos = src_pin.rc()
|
||||
else:
|
||||
in_pos = src_pin.lc()
|
||||
out_pos = dest_pin.center()
|
||||
if src_pin.cy() < dest_pin.cy():
|
||||
out_pos = dest_pin.bc()
|
||||
else:
|
||||
out_pos = dest_pin.uc()
|
||||
|
||||
# move horizontal first
|
||||
self.add_wire(("metal3","via2","metal2"),[in_pos, vector(out_pos.x,in_pos.y),out_pos])
|
||||
|
|
|
|||
|
|
@ -0,0 +1,38 @@
|
|||
#!/usr/bin/env python3
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2019 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
from sram_factory import factory
|
||||
import debug
|
||||
|
||||
class pand3_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("config_{0}".format(OPTS.tech_name))
|
||||
global verify
|
||||
import verify
|
||||
|
||||
import pand3
|
||||
|
||||
debug.info(2, "Testing pand3 gate 4x")
|
||||
a = pand3.pand3(name="pand3x4", size=4)
|
||||
self.local_check(a)
|
||||
|
||||
globals.end_openram()
|
||||
|
||||
# instantiate a copdsay of the class to actually run the test
|
||||
if __name__ == "__main__":
|
||||
(OPTS, args) = globals.parse_args()
|
||||
del sys.argv[1:]
|
||||
header(__file__, OPTS.tech_name)
|
||||
unittest.main(testRunner=debugTestRunner())
|
||||
Loading…
Reference in New Issue