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pbitcell working with bitline adjustments

This commit is contained in:
Jesse Cirimelli-Low 2020-01-27 10:03:31 +00:00
parent 1062cbfd7f
commit d42cd9a281
4 changed files with 37 additions and 39 deletions
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18
compiler/base/geometry.py
View File

@ -333,22 +333,22 @@ class instance(geometry):
if node.mirror == 'MX':
Q_y = -1 * Q_y
Q_bar_y = -1 * Q_bar_y
for pair in range(len(normalized_bl_offsets)):
for offset in range(len(offset)):
normalized_bl_offsets[pair][offset] = -1 * normalized_bl_offsets[pair][offset]
normalized_bl_offsets[pair] = (normalized_bl_offsets[pair][0],
-1 * normalized_bl_offsets[pair][1])
for pair in range(len(normalized_br_offsets)):
for offset in range(len(offset)):
normalized_br_offsets[pair][offset] = -1 * normalized_br_offsets[pair][offset]
normalized_br_offsets[pair] = (normalized_br_offsets[pair][0],
-1 * normalized_br_offsets[pair][1])
Q_offsets.append([Q_x, Q_y])
Q_bar_offsets.append([Q_bar_x, Q_bar_y])
for offset in bl_offset:
bl_offsets.append(offset)
for offset in br.offset:
br_offsets.append(offset)
bl_offsets.append(normalized_bl_offsets)
br_offsets.append(normalized_br_offsets)
elif node.mod.insts is not []:
for instance in node.mod.insts:
@ -360,7 +360,7 @@ class instance(geometry):
vector_spaces = self.apply_path_transform(path)
origin = vector_spaces[2]
origin_offsets.append([origin[0], origin[1]])
return(origin_offsets, Q_offsets, Q_bar_offsets, bl_offsets, br_offsets)
def __str__(self):

4
compiler/characterizer/stimuli.py
View File

@ -63,10 +63,6 @@ class stimuli():
self.sf.write("bitcell_Q_b{0}_r{1}_c{2} ".format(bank,row,col))
self.sf.write("bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank,row,col))
for col in range(OPTS.word_size):
if OPTS.num_banks == 1:
self.sf.write("bl_{2} ".format(bank, row,col))
self.sf.write("br_{2} ".format(bank, row,col))
else:
self.sf.write("bl{0}_{2} ".format(bank, row,col))
self.sf.write("br{0}_{2} ".format(bank, row,col))

48
compiler/sram/sram_base.py
View File

@ -19,6 +19,7 @@ from verilog import verilog
from lef import lef
from sram_factory import factory
from tech import drc
import numpy as np
import logical_effort
class sram_base(design, verilog, lef):
@ -102,33 +103,38 @@ class sram_base(design, verilog, lef):
bl_offsets = pex_offsets[3]
br_offsets = pex_offsets[4]
storage_layer_name = "metal1"
bitline_layer_name = "metal2"
Q = [bank_offset[bank_num][0] + Q_offset[bank_num][0], bank_offset[bank_num][1] + Q_offset[bank_num][1]]
Q_bar = [bank_offset[bank_num][0] + Q_bar_offset[bank_num][0], bank_offset[bank_num][1] + Q_bar_offset[bank_num][1]]
bl = []
br = []
for i in range(len(bl_offsets)):
bl.append([bank_offset[bank_num][1] + bl_offsets[bank_num][2*(i)], bank_offset[bank_num][1] + bl_offsets[bank_num][2*(i)+1]])
storage_layer_name = "metal1"
bitline_layer_name = "metal2"
for cell in range(len(bank_offset)):
Q = [bank_offset[cell][0] + Q_offset[cell][0], bank_offset[cell][1] + Q_offset[cell][1]]
Q_bar = [bank_offset[cell][0] + Q_bar_offset[cell][0], bank_offset[cell][1] + Q_bar_offset[cell][1]]
for i in range(len(br_offsets)):
br.append([bank_offset[bank_num][1] + br_offsets[bank_num][2*(i)], bank_offset[bank_num][1] + br_offsets[bank_num][2*(i)+1]])
self.add_layout_pin_rect_center("bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, cell % OPTS.num_words, int(cell / OPTS.num_words)) , storage_layer_name, Q)
self.add_layout_pin_rect_center("bitcell_Q_bar_b{0}_r{1}_c{2}".format(bank_num, cell % OPTS.num_words, int(cell / OPTS.num_words)), storage_layer_name, Q_bar)
for bitline in range(len(bl_offsets[cell])):
bitline_location = [float(bank_offset[cell][0]) + bl_offsets[cell][bitline][0], float(bank_offset[cell][1]) + bl_offsets[cell][bitline][1]]
bl.append(bitline_location)
self.add_layout_pin_rect_center("bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , storage_layer_name, Q)
self.add_layout_pin_rect_center("bitcell_Q_bar_b{0}_r{1}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), storage_layer_name, Q_bar)
for bitline in range(len(br_offsets[0])):
bitline_location = [float(bank_offset[cell][0]) + br_offsets[cell][bitline][0], float(bank_offset[cell][1]) + br_offsets[cell][bitline][1]]
br.append(bitline_location)
for col in range(len(bl)):
if OPTS.num_banks == 1:
self.add_layout_pin_rect_center("bl0_{0}".format(int(col / OPTS.num_words)), bitline_layer_name, bl[col])
else:
self.add_layout_pin_rect_center("bl{0}_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , bitline_layer_name, bl)
if OPTS.num_banks == 1:
for i in range(len(bl_offsets)):
self.add_layout_pin_rect_center("bl_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , bitline_layer_name, bl)
for i in range(len(br_offsets)):
self.add_layout_pin_rect_center("br_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), bitline_layer_name, br)
else:
self.add_layout_pin_rect_center("bl{0}_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , bitline_layer_name, bl)
self.add_layout_pin_rect_center("br{0}_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), bitline_layer_name, br)
for col in range(len(br)):
if OPTS.num_banks == 1:
self.add_layout_pin_rect_center("br0_{0}".format(int(col / OPTS.num_words)), bitline_layer_name, br[col])
else:
self.add_layout_pin_rect_center("br{0}_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , bitline_layer_name, br)

6
compiler/verify/magic.py
View File

@ -420,12 +420,8 @@ def correct_port(name, output_file_name, ref_file_name):
bitcell_list += "bitcell_Q_b{0}_r{1}_c{2} ".format(bank, row,col)
bitcell_list += "bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank, row,col)
for col in range(OPTS.word_size):
if OPTS.num_banks == 1:
bitcell_list += "bl_{2} ".format(bank, row,col)
bitcell_list += "br_{2} ".format(bank, row,col)
else:
bitcell_list += "bl{0}_{2} ".format(bank, row,col)
bitcell_list += "br{0}_{2} ".format(bank, row,col)
bitcell_list += "br{0}_{2} ".format(bank, row,col)
bitcell_list += "\n"
control_list = "+ "