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OpenRAM
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Simplify is not None

This commit is contained in:
Matt Guthaus 2019-08-22 15:02:52 -07:00
parent ee2456f433
commit 64fc771fc4
3 changed files with 11 additions and 11 deletions
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2
compiler/modules/bank.py
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@ -722,7 +722,7 @@ class bank(design.design):
din_name = "din{0}_{1}".format(port,row)
self.copy_layout_pin(self.port_data_inst[port], data_name, din_name)
if self.word_size is not None:
if self.word_size:
for row in range(self.num_wmasks):
wmask_name = "bank_wmask_{}".format(row)
bank_wmask_name = "bank_wmask{0}_{1}".format(port, row)

4
compiler/modules/write_driver_array.py
View File

@ -62,7 +62,7 @@ class write_driver_array(design.design):
for i in range(self.word_size):
self.add_pin("bl_{0}".format(i), "OUTPUT")
self.add_pin("br_{0}".format(i), "OUTPUT")
if self.write_size is not None:
if self.write_size:
for i in range(self.num_wmasks):
self.add_pin("en_{0}".format(i), "INPUT")
else:
@ -148,7 +148,7 @@ class write_driver_array(design.design):
self.add_layout_pin_rect_center(text=n,
layer="metal3",
offset=pin_pos)
if self.write_size is not None:
if self.write_size:
for bit in range(self.num_wmasks):
en_pin = self.driver_insts[bit*self.write_size].get_pin("en")
# Determine width of wmask modified en_pin with/without col mux

16
compiler/sram/sram_1bank.py
View File

@ -77,7 +77,7 @@ class sram_1bank(sram_base):
# Port 0
port = 0
if self.write_size is not None:
if self.write_size:
if port in self.write_ports:
# Add the write mask flops below the write mask AND array.
wmask_pos[port] = vector(self.bank.bank_array_ll.x,
@ -138,7 +138,7 @@ class sram_1bank(sram_base):
port = 1
if port in self.write_ports:
if self.write_size is not None:
if self.write_size:
# Add the write mask flops below the write mask AND array.
wmask_pos[port] = vector(self.bank.bank_array_ur.x - self.data_dff_insts[port].width,
self.bank.height + 0.5*max_gap_size + self.dff.height)
@ -207,7 +207,7 @@ class sram_1bank(sram_base):
for bit in range(self.word_size):
self.copy_layout_pin(self.data_dff_insts[port], "din_{}".format(bit), "din{0}[{1}]".format(port,bit))
if self.write_size is not None:
if self.write_size:
for bit in range(self.num_wmasks):
self.copy_layout_pin(self.wmask_dff_insts[port], "din_{}".format(bit), "wmask{0}[{1}]".format(port,bit))
@ -228,7 +228,7 @@ class sram_1bank(sram_base):
self.route_data_dff()
if self.write_size is not None:
if self.write_size:
self.route_wmask_dff()
def route_clk(self):
@ -282,7 +282,7 @@ class sram_1bank(sram_base):
self.add_path("metal2",[mid_pos, clk_steiner_pos], width=max(m2m3.width,m2m3.height))
self.add_wire(("metal3","via2","metal2"),[data_dff_clk_pos, mid_pos, clk_steiner_pos])
if self.write_size is not None:
if self.write_size:
wmask_dff_clk_pin = self.wmask_dff_insts[port].get_pin("clk")
wmask_dff_clk_pos = wmask_dff_clk_pin.center()
mid_pos = vector(clk_steiner_pos.x, wmask_dff_clk_pos.y)
@ -362,7 +362,7 @@ class sram_1bank(sram_base):
dff_names = ["dout_{}".format(x) for x in range(self.word_size)]
dff_pins = [self.data_dff_insts[port].get_pin(x) for x in dff_names]
if self.write_size is not None:
if self.write_size:
for x in dff_names:
pin_offset = self.data_dff_insts[port].get_pin(x).center()
self.add_via_center(layers=("metal1", "via1", "metal2"),
@ -375,7 +375,7 @@ class sram_1bank(sram_base):
bank_names = ["din{0}_{1}".format(port,x) for x in range(self.word_size)]
bank_pins = [self.bank_inst.get_pin(x) for x in bank_names]
if self.write_size is not None:
if self.write_size:
for x in bank_names:
pin_offset = self.bank_inst.get_pin(x).bc()
self.add_via_center(layers=("metal1", "via1", "metal2"),
@ -386,7 +386,7 @@ class sram_1bank(sram_base):
offset=pin_offset)
route_map = list(zip(bank_pins, dff_pins))
if self.write_size is not None:
if self.write_size:
self.create_horizontal_channel_route(netlist=route_map,
offset=offset,
layer_stack=("metal3", "via3", "metal4"))