mirror of https://github.com/VLSIDA/OpenRAM.git
update magic for multiport
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30604fb093
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@ -63,8 +63,9 @@ class stimuli():
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self.sf.write("bitcell_Q_b{0}_r{1}_c{2} ".format(bank,row,col))
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self.sf.write("bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank,row,col))
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for col in range(OPTS.word_size):
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self.sf.write("bl{0}_{2} ".format(bank, row, col))
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self.sf.write("br{0}_{2} ".format(bank, row, col))
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for port in range(OPTS.num_r_ports + OPTS.num_w_ports + OPTS.num_rw_ports):
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self.sf.write("bl{0}_{2} ".format(port, row, col))
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self.sf.write("br{0}_{2} ".format(port, row, col))
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self.sf.write("s_en{0} ".format(bank))
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@ -128,19 +128,13 @@ class sram_base(design, verilog, lef):
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col = br_meta[cell][0][2]
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for bitline in range(len(br_offsets[cell])):
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bitline_location = [float(bank_offset[cell][0]) + br_offsets[cell][bitline][0], float(bank_offset[cell][1]) + br_offsets[cell][bitline][1]]
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br.append([bitline_location, br_meta[cell][bitline][3], col])
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br.append([bitline_location, br_meta[cell][bitline][3], col])
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for i in range(len(bl)):
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self.add_layout_pin_rect_center("bl{0}_{1}".format(bl[i][1], bl[i][2]), bitline_layer_name, bl[i][0])
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for i in range(len(br)):
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self.add_layout_pin_rect_center("br{0}_{1}".format(br[i][1], br[i][2]), bitline_layer_name, br[i][0])
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self.add_layout_pin_rect_center("br{0}_{1}".format(br[i][1], br[i][2]), bitline_layer_name, br[i][0])
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# add pex labels for control logic
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for i in range (len(self.control_logic_insts)):
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@ -420,6 +420,7 @@ def correct_port(name, output_file_name, ref_file_name):
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bitcell_list += "bitcell_Q_b{0}_r{1}_c{2} ".format(bank, row, col)
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bitcell_list += "bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank, row, col)
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for col in range(OPTS.word_size):
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for port in range(OPTS.num_r_ports + OPTS.num_w_ports + OPTS.num_rw_ports):
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bitcell_list += "bl{0}_{2} ".format(bank, row, col)
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bitcell_list += "br{0}_{2} ".format(bank, row, col)
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bitcell_list += "\n"
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