luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Unique name for sram channel routes

This commit is contained in:
mrg 2020-10-01 09:55:34 -07:00
parent aaa36bf5cf
commit 18c8ad265e
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
compiler/sram/sram_1bank.py
View File

@ -414,7 +414,7 @@ class sram_1bank(sram_base):
layer_stack=self.m1_stack,
parent=self)
if add_routes:
self.add_inst("hc", cr)
self.add_inst(cr.name, cr)
self.connect_inst([])
else:
self.col_addr_bus_size[port] = cr.height
@ -470,7 +470,7 @@ class sram_1bank(sram_base):
layer_stack=layer_stack,
parent=self)
if add_routes:
self.add_inst("hc", cr)
self.add_inst(cr.name, cr)
self.connect_inst([])
else:
self.data_bus_size[port] = max(cr.height, self.col_addr_bus_size[port]) + self.data_bus_gap
@ -482,7 +482,7 @@ class sram_1bank(sram_base):
layer_stack=layer_stack,
parent=self)
if add_routes:
self.add_inst("hc", cr)
self.add_inst(cr.name, cr)
self.connect_inst([])
else:
self.data_bus_size[port] = max(cr.height, self.col_addr_bus_size[port]) + self.data_bus_gap