262 Commits

Author	SHA1	Message	Date
mrg	70c83f20b6	Fixes to pass unit tests. ... Skip replica tests until freepdk45 cells are made. Revert to previous control and row addr dff placement.	2019-07-03 13:37:56 -07:00
mrg	bc4a3ee2b7	New port_data module works in SCMOS	2019-07-03 13:17:12 -07:00
jsowash	67c6cdf3bb	Fixed error where word_size was compared to num_words and added write_size to control_logic.py	2019-07-01 15:51:40 -07:00
jsowash	242771f710	Merge branch 'dev' into add_wmask	2019-06-28 15:44:27 -07:00
jsowash	1f76afd294	Begin wmask functionality. Added wmask to verilog file and config parameters.	2019-06-28 15:43:09 -07:00
Hunter Nichols	3f5b60856a	Fixed key error with analytical delay of write ports.	2019-06-28 13:49:04 -07:00
Hunter Nichols	4e08e2da87	Merged and fixed conflicts with dev	2019-06-25 16:55:50 -07:00
Matt Guthaus	6e044b776f	Merge branch 'pep8_cleanup' into dev	2019-06-14 08:47:10 -07:00
mrg	58f51b72f1	Merge fixes	2019-06-03 15:31:49 -07:00
mrg	bd4d965e37	Begin single layer supply router	2019-06-03 15:27:37 -07:00
mrg	4612c9c182	Move power pins before no route option	2019-06-03 15:27:37 -07:00
mrg	bf86969972	Create sram subdirectory.	2019-05-31 08:56:24 -07:00