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OpenRAM
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Exit on DRC not run, check for LVSDRC before running in sram_base.

This commit is contained in:
mrg 2020-07-14 08:38:49 -07:00
parent e502ee02be
commit bb8157b3b7
2 changed files with 4 additions and 4 deletions
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2
compiler/sram/sram_base.py
View File

@ -129,7 +129,7 @@ class sram_base(design, verilog, lef):
start_time = datetime.datetime.now()
# We only enable final verification if we have routed the design
self.DRC_LVS(final_verification=OPTS.route_supplies, force_check=True)
self.DRC_LVS(final_verification=OPTS.route_supplies, force_check=OPTS.check_lvsdrc)
if not OPTS.is_unit_test:
print_time("Verification", datetime.datetime.now(), start_time)

6
compiler/verify/none.py
View File

@ -20,7 +20,7 @@ pex_warned = False
def run_drc(cell_name, gds_name, extract=False, final_verification=False):
global drc_warned
if not drc_warned:
debug.warning("DRC unable to run.")
debug.error("DRC unable to run.", -1)
drc_warned=True
# Since we warned, return a failing test.
return 1
@ -29,7 +29,7 @@ def run_drc(cell_name, gds_name, extract=False, final_verification=False):
def run_lvs(cell_name, gds_name, sp_name, final_verification=False):
global lvs_warned
if not lvs_warned:
debug.warning("LVS unable to run.")
debug.error("LVS unable to run.", -1)
lvs_warned=True
# Since we warned, return a failing test.
return 1
@ -38,7 +38,7 @@ def run_lvs(cell_name, gds_name, sp_name, final_verification=False):
def run_pex(name, gds_name, sp_name, output=None, final_verification=False):
global pex_warned
if not pex_warned:
debug.warning("PEX unable to run.")
debug.error("PEX unable to run.", -1)
pex_warned=True
# Since we warned, return a failing test.
return 1