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817 Commits

Author SHA1 Message Date
Matt Guthaus 563ff77d44 Add sram_config class. Rename port variables for better description. 2018-08-31 12:03:28 -07:00
Michael Timothy Grimes 75d77095d0 merging changes to magic.py 2018-08-31 09:01:15 -07:00
Hunter Nichols 4022f014b2 Merge branch 'dev' into multiport_characterization 2018-08-31 00:43:33 -07:00
Hunter Nichols 60088c2dfb Added changes to lib to allow the default to run. Will crash with multiport options. 2018-08-31 00:42:56 -07:00
Hunter Nichols 6614c3eb51 Altered min_period algorithm to work for multiport. Works for default config but mostly untested for multiport options. 2018-08-30 22:43:56 -07:00
Hunter Nichols 5989a3c952 Expanded run_delay_stimulas to multiport. Bug Fixes as well. 2018-08-30 17:08:34 -07:00
Hunter Nichols 907b7310ee Actually changed the noops default data in this commit. 2018-08-30 15:16:54 -07:00
Hunter Nichols 53fa6108e1 Changed most noops calls to have default input of all 0's. Changed parse_values to return dict even if some values fail. 2018-08-30 15:11:54 -07:00
Matt Guthaus 3ab0b569cb Use a .magicrc in the technology directory to read magic tech files 2018-08-30 14:20:41 -07:00
Michael Timothy Grimes 35ae4a275e Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-08-30 12:42:24 -07:00
Hunter Nichols 73388e9797 Merge branch 'dev' into multiport_characterization 2018-08-30 01:20:23 -07:00
Hunter Nichols e32c1fdd23 Changed part (4) of analyze to use the updated measure names. 2018-08-30 01:18:34 -07:00
Hunter Nichols 78be724867 Edited find_feasible period to use dynamic naming on its measured values and edited the algorithm to work with multiport. 2018-08-30 00:11:14 -07:00
Hunter Nichols 02cf51d3be Added generic parsing function to capture multiple values. This commit does not run and it messes up some naming conventions 2018-08-29 22:16:42 -07:00
Matt Guthaus 762f2d894c Revert all transFlags in GdsMill 2018-08-29 17:23:04 -07:00
Matt Guthaus 93a6247f26 Unrotate vias in delay chain 2018-08-29 17:21:53 -07:00
Hunter Nichols 4b515fe1ac Changed create_test_cycles to have targeted ports for characterization rather than all ports always. 2018-08-29 17:16:11 -07:00
Michael Timothy Grimes e118cc2d5c Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-08-29 16:06:50 -07:00
Michael Timothy Grimes aeaab13d28 Unit tests for pbitcell now passing, so commenting out skip line. Also gave pbitcell_array useful names in unit test for easier debugging 2018-08-29 16:05:13 -07:00
Matt Guthaus 5a065cf701 Remove setting of rotate transflag. Not supported in Calibre? 2018-08-29 16:04:15 -07:00
Michael Timothy Grimes 7ef7c084cd fixed typo that added two '/' characters to path sys command (i.e. from tech//SCN3ME_SUBM.30 to tech/SCN3ME_SUBM.30) 2018-08-29 16:01:25 -07:00
Michael Timothy Grimes 29da8a5209 Further changes to pbitcell so that it passes unit tests for bitcell_array 2018-08-29 15:54:49 -07:00
Matt Guthaus 334aa53cee Merge branch 'supply_routing' of https://github.com/VLSIDA/PrivateRAM into supply_routing 2018-08-29 15:40:04 -07:00
Matt Guthaus 73289a6090 Clean up GdsMill. Fix rotate bug I introduced in transFlags! 2018-08-29 15:34:45 -07:00
Matt Guthaus 0ce2dd2791 Add supply_grid file 2018-08-29 15:34:45 -07:00
Matt Guthaus 27bb1d2ee7 Rewrite blockage routines in router. Clean up GdsMill code. 2018-08-29 15:34:45 -07:00
Matt Guthaus 04b7c419f1 Rename _new cell back to original for LVS comparison script 2018-08-29 15:34:45 -07:00
Matt Guthaus 5386b7a0f4 Initial refactor of signal and supply router classes. 2018-08-29 15:34:45 -07:00
Matt Guthaus 19d14e39ce Remove extraneous files 2018-08-29 15:34:45 -07:00
Matt Guthaus 6220ea6d47 Update router to work with pin_layout structure. 2018-08-29 15:34:45 -07:00
Matt Guthaus 41fba9d27c Add sketch for power grid routing code 2018-08-29 15:34:16 -07:00
Michael Timothy Grimes 807a4d7767 Fixed drcs error in magic. Pbitcell should now pass unit tests in calibre and magic. 2018-08-29 15:30:50 -07:00
Hunter Nichols 775fe7b57c Fixed measure statement stating times. This commit crashes if there are no readwrite ports. 2018-08-29 15:13:31 -07:00
Michael Timothy Grimes 1d5a41df2d fixed issue with read ports that caused extra transistors to appear 2018-08-29 08:52:45 -07:00
Hunter Nichols 8a0411279e Merge branch 'dev' into multiport_characterization 2018-08-29 01:27:37 -07:00
Hunter Nichols 8fad81ff1e Changed delay measures to add additional measure based on # of ports. Measure times are not correct yet. 2018-08-29 00:43:27 -07:00
Hunter Nichols ffe59bdf51 Edited delay measures to handle multiple readwrite ports. This commit is not well tested. 2018-08-29 00:01:22 -07:00
Matt Guthaus e804f36bec Add parameters to give preference to DRC/LVS/PEX tools like we do for spice. 2018-08-28 13:41:26 -07:00
Hunter Nichols fa8434e5f0 Added debug checks for unsupported port options. 2018-08-28 13:01:35 -07:00
Hunter Nichols bd763fa1e3 Fixed naming issue between sram instance and PWL in stimulus 2018-08-28 12:09:02 -07:00
Matt Guthaus 309bfaea2a Update comments in magic to download the correct version of design rules 2018-08-28 11:48:23 -07:00
Matt Guthaus 8752d799b4 Skip pbitcell tests for now 2018-08-28 10:45:50 -07:00
Matt Guthaus 95a8688506 Rewrite blockage routines in router. Clean up GdsMill code. 2018-08-28 10:43:45 -07:00
Matt Guthaus 0dbc88dab2 Rename _new cell back to original for LVS comparison script 2018-08-28 10:43:44 -07:00
Matt Guthaus 82833ef8f0 Initial refactor of signal and supply router classes. 2018-08-28 10:43:44 -07:00
Matt Guthaus 8f1e2675fe Remove extraneous files 2018-08-28 10:43:44 -07:00
Matt Guthaus 2ae1e0234d Update router to work with pin_layout structure. 2018-08-28 10:43:44 -07:00
Matt Guthaus ea52af3747 Add sketch for power grid routing code 2018-08-28 10:43:44 -07:00
Matt Guthaus ac8a16ebdf Fix permissions for unit tests to be run standalone. 2018-08-28 10:31:58 -07:00
Matt Guthaus e17c69be3e Clean up new code for add_modules, add_pins and netlist/layouts. 2018-08-28 10:24:09 -07:00
Hunter Nichols 0bb4b48439 Merge branch 'dev' into multiport_characterization 2018-08-28 00:37:26 -07:00
Hunter Nichols 75da5a994b Edited create_test_cycles to generate values that characterize all ports. Still several bugs and lib file does not support multiple ports. 2018-08-28 00:30:15 -07:00
Hunter Nichols ba5988ec7f Added write port structure to create_test_cycles. This commit contains test code. 2018-08-27 20:35:29 -07:00
Hunter Nichols d82d3df4a7 Added read port cycle data generation. This commit contains test code in create_test_cycles 2018-08-27 18:17:02 -07:00
Matt Guthaus 6401cbf2a6 Move place function to instance class rather than hierarchy. 2018-08-27 17:25:39 -07:00
Matt Guthaus 8664f7a0b8 Converted all modules to not run create_layout when netlist_only 
mode is enabled.
 2018-08-27 16:42:48 -07:00
Hunter Nichols a0e06809f9 Comments now display port in stim file. 2018-08-27 16:23:23 -07:00
Hunter Nichols 350823d434 Added basic structure to add_test_cycles to characterize multiple ports and its helper functions to allow for ports to be selected for characterization 2018-08-27 15:56:42 -07:00
Matt Guthaus 9f051df18d Added netlist only configuration option. 2018-08-27 14:33:02 -07:00
Matt Guthaus 19d46f5954 Finalized separation of netlist/layout creation. 2018-08-27 14:18:32 -07:00
Matt Guthaus 0daad338e4 All modules have split netlist/layout. 2018-08-27 11:13:34 -07:00
Matt Guthaus 87f539f3a8 Separate netlist/layout for flop and precharge array. 2018-08-27 10:54:21 -07:00
Matt Guthaus 138a70fc23 Add place_inst routine. 
Separate create netlist and layout in some modules.
 2018-08-27 10:42:40 -07:00
Michael Timothy Grimes 8c73a26daa Changing function names in bitcell and pbitcell to better reflect what values they're returning. Editting function calls in bitcell_array and bank accordingly. 2018-08-26 14:37:17 -07:00
Hunter Nichols 6dc72f5b1e Added additional control signal to stim file based on # of ports. 2018-08-23 17:46:24 -07:00
Hunter Nichols efcb435fde Changed # of address signals to reflect # of ports in delay 2018-08-23 14:49:56 -07:00
Hunter Nichols 9151858449 Characterizer now recognizesmultiple ports and additional DIN/DOUT signals are added to stim file. 2018-08-22 23:45:43 -07:00
Hunter Nichols 21e85297d3 Merge branch 'dev' into multiport_characterization 2018-08-22 14:50:29 -07:00
Hunter Nichols 8abf45a5d3 Some test code added. To be removed later. 2018-08-22 14:19:09 -07:00
Michael Timothy Grimes b8ae21a52b made multi-port changes to sram. This commit will allow all levels of openram to pass unit tests 2018-08-20 22:11:24 -07:00
Michael Timothy Grimes f0cca8293c Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-08-19 00:01:52 -07:00
Michael Timothy Grimes 8e3dc332f3 changed control signal names in bank select to accommodate multi-port changes in bank 2018-08-19 00:00:42 -07:00
Michael Timothy Grimes 19ca0d6c2a Changing control logic names to match naming scheme for multi-port. din[0] to din0[0], s_en to s_en0, addr[0] to addr0[0], etc. Sram level should pass unit tests for single port but will not currently pass for multi-port 2018-08-18 16:51:21 -07:00
Michael Timothy Grimes 0f8da1510e Reverting pin name changes of precharge cell and array back to 'bl' and 'br'. Also clarifying bl and br init parameters to reflect that they refer to the bitcell lines. 2018-08-18 15:27:07 -07:00
Matt Guthaus e3f2ee8a7e Fix VCG error in channel route. 
Note, the channel routing algorithm still does not handle
horizontal conflicts or cyclic vertical conflicts!
 2018-08-15 14:19:04 -07:00
Matt Guthaus 6e332e581a Updated to include local magic rules 2018-08-15 09:46:23 -07:00
Michael Timothy Grimes e147f807a5 adding a unit test for multiported bank, this test will skip in the regression testing because multiported bank does not pass drc yet 2018-08-15 04:32:56 -07:00
Michael Timothy Grimes e4a94e8597 Merging changes to bank. Bank has been altered to accommodate multiport. Single port still passes unit test, though some control signal names have been changed to have a following 0 (e.g. s_en to s_en0). Multiport does not pass drc yet, but can accurately generate a spice netlist. 2018-08-15 04:00:48 -07:00
Michael Timothy Grimes e592d95146 Altered bank to accommodate multiport. Single port still works, though some of the control signal names have been changes to have a following 0 (e.g. s_en to s_en0). Multiport does not pass drc yet, but can generate an accurate spice netlist. 2018-08-15 03:36:40 -07:00
Michael Timothy Grimes a5af4a2b9c resolved variable name error in 00_code_format test 2018-08-15 03:33:33 -07:00
Michael Timothy Grimes af43fb6276 called bitcell function before reading the height of the bitcell because pbitcell's dynamic height can only be determined after the module is called 2018-08-15 02:19:36 -07:00
Michael Timothy Grimes 040340b49f editted naming convention on precharge to accommodate multiport 2018-08-15 02:14:45 -07:00
Michael Timothy Grimes 8d97862f6e altered precharge array and precharge unit tests to accommodate multiport 2018-08-15 00:55:23 -07:00
Matt Guthaus 36bfd2932a Update delay results with new clock routing 2018-08-14 10:51:02 -07:00
Matt Guthaus 8900edbe12 Finalize single bank clock routing. 2018-08-14 10:36:35 -07:00
Matt Guthaus 3420b1002c Connect data and column DFF clocks in 1 bank. 2018-08-14 10:09:41 -07:00
Matt Guthaus 5ff49d322d bank_sel_bar only used for clk now 2018-08-13 15:14:52 -07:00
Matt Guthaus f7f318d72e Remove tri_en signals from bank control logic. 2018-08-13 14:47:03 -07:00
Matt Guthaus 49bee6a96e Remove OEB signal since we split DIN/DOUT ports 2018-08-13 14:09:49 -07:00
Matt Guthaus 9ffba4b052 Add +x permissions on precharge and pbitcell tests 2018-08-13 09:57:10 -07:00
Matt Guthaus 34736b7b3f Remove carriage returns form python files 2018-08-07 09:44:01 -07:00
Matt Guthaus abacf6a2d0 Add carriage return check for python files 2018-08-07 09:40:45 -07:00
Michael Timothy Grimes c2a9e91dba Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-08-05 19:53:28 -07:00
Michael Timothy Grimes 5666ee6635 altered precharge module to accomodate bitlines from pbitcell, and altered unit test to test both bitcell and pbitcell configurations 2018-08-05 19:46:05 -07:00
Michael Timothy Grimes ecd4612167 altered bitcell, pbitcell, and bitcell array modules to accomodate additional bitline reference functions 2018-08-05 19:43:59 -07:00
Matt Guthaus c0d5f781cf Not sure how VCG channel constraint got removed. Fixed this bug before... 2018-07-27 15:15:40 -07:00
Matt Guthaus a7a3099702 Fix comments in stimulus file to show list and not zip type 2018-07-27 15:00:00 -07:00
Matt Guthaus d739c17b8d Fix delay numbers in hspice delay unit test. 2018-07-27 14:43:52 -07:00
Matt Guthaus d75d17bc8a Update golden results for FreePDK45 tests. 2018-07-27 14:25:52 -07:00
Matt Guthaus 642a5cfe73 Line-wrap pinv debug formatting 2018-07-27 14:07:55 -07:00
Matt Guthaus 71606e1097 Add read cycle to clear DOUT bus before each read measure. 2018-07-27 14:06:59 -07:00
Matt Guthaus 8f72621f4a Converted delay measurement to use add_read/add_write functions. 
Rewrote the logic to add one cycle at a time for easier
manipulation. This can be extended more easily into the
functional simulations.
 2018-07-27 11:36:17 -07:00
Matt Guthaus 5b2cb6a95e Update remaining SCMOS golden lib files. 2018-07-27 09:44:12 -07:00
Matt Guthaus 6b967c08dd Updated output messages in timing test comparisons. 
Added output to show which lines differ and what their line numbers are..
Added output to show relative difference of approximate compares.
Added output to include file names that mismatch.
 2018-07-27 09:34:44 -07:00
Matt Guthaus 01cbc71a2a Limit sizes for dff_buf too. Add comments about restriction. 2018-07-27 08:17:50 -07:00
Matt Guthaus b541efe959 Fix wide gnd rail spacing to inverter NMOS by adding size limit to pinv. 2018-07-27 07:23:18 -07:00
Matt Guthaus 0e0516c4a6 Fix delay test unit test results. 2018-07-26 16:45:09 -07:00
Matt Guthaus 85595b0f6f Update format of delay test output during an error to directly 
copy into unit test. Factor function into testutils.py for comparison.
 2018-07-26 16:05:24 -07:00
Matt Guthaus 5088487cf7 Update delay tests to output useful information for debug. 2018-07-26 15:45:17 -07:00
Matt Guthaus a00e160274 Convert bitline index to integer in trim_spice 2018-07-26 14:29:44 -07:00
Matt Guthaus f098b995f0 Fix pinvbuf test to use new interface with only driver size. 2018-07-26 14:20:00 -07:00
Matt Guthaus c8808c268a Close output log in test 30 to avoid warning 2018-07-26 14:01:40 -07:00
Matt Guthaus bc67ad5ead Fixed timing to be measured from positive clock edge since 
reading a 1 will be the precharge time.
Started modifying the lib file for DIN and DOUT ports, but did not
check the syntax yet.
 2018-07-26 13:58:50 -07:00
Matt Guthaus e827c1b8c7 Make pinvbuf have unique names for GDS compliance. 
Add back gating of w_en since write should happen in second half
or else we will have write and precharge simultaneously active.
 2018-07-26 11:40:40 -07:00
Matt Guthaus 00a87d57ab Modified pinvbuf to have a stage effort of 4 for driving the 
clock bar to wordline enable.
Fixed comments in stimulus file to have right cycle numbers.
Removed clock gating on we signal since clock gating is already
done on the WL signals. It is redundant.
 2018-07-26 11:28:48 -07:00
Michael Timothy Grimes fb0de710ec Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-07-26 09:04:59 -07:00
Michael Timothy Grimes 27ab411146 fixed error I missed in pbitcell_array test 2018-07-26 09:02:52 -07:00
Matt Guthaus dd7069dd98 Remove print statement 2018-07-25 15:51:48 -07:00
Matt Guthaus b7525a14c2 Change DIN to DOUT in characterizer. Spacing dff flops down by m2 not m1 pitch. 2018-07-25 15:50:49 -07:00
Matt Guthaus d6df215718 Always use m2_pitch as default for channel for via spacing rules 2018-07-25 15:47:11 -07:00
Matt Guthaus 6d71c3f790 Fix bug to remove pin from conflicts in addition to graph keys 2018-07-25 15:36:16 -07:00
Matt Guthaus a4bfbe3545 Move dff_array pins to center of rail 2018-07-25 15:08:04 -07:00
Matt Guthaus 44f0e4a1de Fix new offset coordinate syntax error 2018-07-25 13:47:36 -07:00
Matt Guthaus 64b3cfee26 Only print LVS/DRC stats when it is enabled 2018-07-25 13:44:34 -07:00
Matt Guthaus 7c254d540d Change channel route api to use pin maps instead of an insteads for cases where there are multiple instances that have the pins (e.g. decoders) 2018-07-25 11:37:06 -07:00
Matt Guthaus f7a2766c29 First draft of naive channel route in hierarchy_layout. It doesn't implement horizontal conflicts or try to minimize the number of channels. 2018-07-25 11:13:30 -07:00
Matt Guthaus 48d3b25b74 Rotate the output pins of the control logic. Need to fix this permanently. 2018-07-24 14:26:01 -07:00
Matt Guthaus 16a084fde1 Add vdd/gnd at right end of rails. Rename some signals for clarity. 2018-07-24 14:15:11 -07:00
Matt Guthaus aa2ea26db3 Convert control module to use hierarchy bus API 2018-07-24 10:35:07 -07:00
Matt Guthaus b50f57ea3a Remove control logic supply rails and replace with M3 supply pins 2018-07-24 10:12:54 -07:00
Matt Guthaus 45a53ed089 Rotate via in center for freepdk 2018-07-19 14:01:48 -07:00
Matt Guthaus 4c3bd0e42b Move WL gnd contacts outside the cell for simplicity 2018-07-19 13:38:45 -07:00
Matt Guthaus beee8229d1 Revert change. Add gnd pin to right on bitline load. 2018-07-19 13:26:12 -07:00
Matt Guthaus ea53066966 Align RBL inverter with first load inverter in delay chain to aid supply connections 2018-07-19 11:02:13 -07:00
Matt Guthaus 311ab97bfc Fix s_en stages to be even per Kevin's bug report. Assert minimum fanout to ensure vdd/gnd connections. 2018-07-19 10:51:20 -07:00
Matt Guthaus 128dfd5830 Add internal vdd/gnd connections for delay chain 2018-07-19 10:37:47 -07:00
Matt Guthaus 51958814a0 Fixing power via problems in freepdk45 2018-07-19 10:23:08 -07:00
Matt Guthaus 9983408fa3 Add verilog_write to sram wrapper for verilog unit test 2018-07-19 10:05:30 -07:00
Matt Guthaus 3f57853969 Use lower case names except for leaf cells and top level 2018-07-18 15:10:57 -07:00
Matt Guthaus 4a139b682d Add temporary options to LVS to allow name merging 2018-07-18 15:10:29 -07:00
Matt Guthaus a9c0ec5549 Add LVS correspondence points to each bank type 2018-07-18 14:29:04 -07:00
Matt Guthaus a878ce5500 Standardize DRC and LVS message levels 2018-07-18 14:28:43 -07:00
Matt Guthaus 58896a6f8e Fix control signal names on control_logic input 2018-07-18 13:41:44 -07:00
Matt Guthaus b88947ef5c Pass the sram design to lib instead of the sram wrapper 2018-07-18 11:51:42 -07:00
Matt Guthaus f43d4cc98f Fix routing clk connections of dff arrays 2018-07-18 11:38:58 -07:00
Matt Guthaus 0701fceb0b Use sram rather than new meta-sram class in the characterizer for delay 2018-07-18 10:39:29 -07:00
Matt Guthaus 1130062343 Fix syntax error in delay test to use new sram wrapper module 2018-07-18 10:33:18 -07:00
Matt Guthaus b8a3bc9b1a Space hier decoder input connections along rails to avoid conflicts 2018-07-18 10:21:58 -07:00
Matt Guthaus b8e3629923 Fix syntax error in unit test 2018-07-17 15:14:22 -07:00
Matt Guthaus 01655b1d54 Clean up tests. Enable 8-way tests. Some tests still have channel route conflicts. 2018-07-17 15:13:00 -07:00