Add regression test for issue #756.

(cherry picked from commit 899d459233)

.gitattributes

@@ -0,0 +1,2 @@
+# gperf in MSYS chokes on DOS line endings
+*.gperf text eol=lf

.github/test.sh

@@ -0,0 +1,14 @@
+#!/usr/bin/env sh
+
+echo "Using the bundled ivtest to run regression tests."
+echo " pwd = $(pwd)"
+
+cd ivtest
+
+status=0
+
+perl vvp_reg.pl || status=1
+
+perl vpi_reg.pl || status=1
+
+exit $status

.github/workflows/test.yml

@@ -0,0 +1,85 @@
+name: test
+
+on:
+  push:
+  pull_request:
+
+jobs:
+
+
+  lin:
+    strategy:
+      fail-fast: false
+      matrix:
+        os: [
+          '18.04',
+          '20.04'
+        ]
+    runs-on: ubuntu-${{ matrix.os }}
+    name: '🐧 Ubuntu ${{ matrix.os }}'
+    steps:
+
+    - uses: actions/checkout@v2
+
+    - name: Install dependencies
+      run: |
+        sudo apt update -qq
+        sudo apt install -y make g++ git bison flex gperf libreadline-dev autoconf
+
+    - name: Build, check and install
+      run: |
+        autoconf
+        ./configure
+        make check
+        sudo make install
+
+    - name: Test
+      run: ./.github/test.sh
+
+
+  win:
+    runs-on: windows-latest
+    strategy:
+      fail-fast: false
+      matrix:
+        include: [
+          { msystem: MINGW64, arch: x86_64 },
+          { msystem: MINGW32, arch: i686 }
+        ]
+    name: 🟪 ${{ matrix.msystem}} · ${{ matrix.arch }}
+    defaults:
+      run:
+        shell: msys2 {0}
+    env:
+      MINGW_INSTALLS: ${{ matrix.msystem }}
+    steps:
+
+    - run: git config --global core.autocrlf input
+      shell: bash
+
+    - uses: actions/checkout@v2
+
+    - uses: msys2/setup-msys2@v2
+      with:
+        msystem: ${{ matrix.msystem }}
+        update: true
+        install: >
+          git
+          base-devel
+          mingw-w64-${{ matrix.arch }}-toolchain
+
+    - name: Build and check
+      run: |
+        cd msys2
+        makepkg-mingw --noconfirm --noprogressbar -sCLf
+
+    - name: Install
+      run: pacman -U --noconfirm msys2/*.zst
+
+    - name: Test
+      run: ./.github/test.sh
+
+    - uses: actions/upload-artifact@v2
+      with:
+        name: ${{ matrix.msystem }}-${{ matrix.arch }}
+        path: msys2/*.zst

AStatement.h

@@ -1,7 +1,7 @@
 #ifndef IVL_AStatement_H
 #define IVL_AStatement_H
 /*
- * Copyright (c) 2008-2014 Stephen Williams ([email protected])
+ * Copyright (c) 2008-2021 Stephen Williams ([email protected])
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -42,7 +42,7 @@ class AContrib : public Statement {
       AContrib(PExpr*lval, PExpr*rval);
       ~AContrib();
 
-      virtual void dump(ostream&out, unsigned ind) const;
+      virtual void dump(std::ostream&out, unsigned ind) const;
       virtual NetProc* elaborate(Design*des, NetScope*scope) const;
 
     private:
@@ -68,10 +68,10 @@ class AProcess : public LineInfo {
       ivl_process_type_t type() const { return type_; }
       Statement*statement() { return statement_; }
 
-      map<perm_string,PExpr*> attributes;
+      std::map<perm_string,PExpr*> attributes;
 
 	// Dump the analog process
-      void dump(ostream&out, unsigned ind) const;
+      void dump(std::ostream&out, unsigned ind) const;
 
     private:
       ivl_process_type_t type_;

BUGS.txt

@@ -116,13 +116,17 @@ programs.
 
 RESEARCHING EXISTING/PAST BUGS, AND FILING REPORTS
 
-The URL <http://sourceforge.net/tracker/?group_id=149850> is the main
-bug tracking system. Once you believe you have found a bug, you may
-browse the bugs database for existing bugs that may be related to
-yours. You might find that your bug has already been fixed in a later
-release or snapshot. If that's the case, then you are set. Also,
-consider if you are reporting a bug or really asking for a new
-feature, and use the appropriate tracker.
+The URL <https://sourceforge.net/p/iverilog/bugs/> is the main
+bug tracking system, although some users have reported bugs at
+<https://github.com/steveicarus/iverilog/issues/>. Once you believe
+you have found a bug, you may browse the bugs database for existing
+bugs that may be related to yours. You might find that your bug has
+already been fixed in a later release or snapshot. If that's the case,
+then you are set. Also, consider if you are reporting a bug or really
+asking for a new feature, and use the appropriate tracker.
+
+ system (although you will also find bug rep
+
 
 The bug database supports basic keyword searches, and you can
 optionally limit your search to active bugs, or fixed bugs. You may
@@ -145,7 +149,7 @@ version from git. Please see the developer documentation for more
 detailed instructions -- <http://iverilog.wikia.com/wiki/>.
 
 When you make a patch, submit it to the "Patches" tracker at
-<http://sourceforge.net/tracker/?group_id=149850>. Patches added to
+<https://sourceforge.net/p/iverilog/patches/>. Patches added to
 the "Patches" tracker enter the developer workflow, are checked,
 applied to the appropriate git branch, and are pushed. Then the
 tracker item is closed.
@@ -158,7 +162,7 @@ clarification before applying it.)
 
 COPYRIGHT ISSUES
 
-Icarus Verilog is Copyright (c) 1998-2008 Stephen Williams except
+Icarus Verilog is Copyright (c) 1998-2018 Stephen Williams except
 where otherwise noted. Minor patches are covered as derivative works
 (or editorial comment or whatever the appropriate legal term is) and
 folded into the rest of ivl. However, if a submission can reasonably

HName.cc

@@ -40,7 +40,7 @@ hname_t::hname_t(perm_string text, int num)
       number_[0] = num;
 }
 
-hname_t::hname_t(perm_string text, vector<int>&nums)
+hname_t::hname_t(perm_string text, const vector<int>&nums)
 : name_(text), number_(nums)
 {
 }

HName.h

@@ -1,7 +1,7 @@
 #ifndef IVL_HName_H
 #define IVL_HName_H
 /*
- * Copyright (c) 2001-2014 Stephen Williams ([email protected])
+ * Copyright (c) 2001-2021 Stephen Williams ([email protected])
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -36,13 +36,13 @@
 
 class hname_t {
 
-      friend ostream& operator<< (ostream&out, const hname_t&that);
+      friend std::ostream& operator<< (std::ostream&out, const hname_t&that);
 
     public:
       hname_t ();
       explicit hname_t (perm_string text);
       explicit hname_t (perm_string text, int num);
-      explicit hname_t (perm_string text, std::vector<int>&nums);
+      explicit hname_t (perm_string text, const std::vector<int>&nums);
       hname_t (const hname_t&that);
       ~hname_t();
 
@@ -56,12 +56,12 @@ class hname_t {
 
       size_t has_numbers() const;
       int peek_number(size_t idx) const;
+      const std::vector<int>&peek_numbers() const;
 
     private:
       perm_string name_;
-	// If the number is anything other than INT_MIN, then this is
-	// the numeric part of the name. Otherwise, it is not part of
-	// the name at all.
+	// If this vector has size, then the numbers all together make
+	// up part of the hierarchical name.
       std::vector<int> number_;
 
     private: // not implemented
@@ -82,19 +82,24 @@ inline int hname_t::peek_number(size_t idx) const
       return number_[idx];
 }
 
+inline const std::vector<int>& hname_t::peek_numbers(void) const
+{
+      return number_;
+}
+
 inline size_t hname_t::has_numbers() const
 {
       return number_.size();
 }
 
-extern ostream& operator<< (ostream&, const hname_t&);
+extern std::ostream& operator<< (std::ostream&, const hname_t&);
 
 inline bool operator != (const hname_t&l, const hname_t&r)
 { return ! (l == r); }
 
-inline ostream& operator<< (ostream&out, const list<hname_t>&ll)
+inline std::ostream& operator<< (std::ostream&out, const std::list<hname_t>&ll)
 {
-      list<hname_t>::const_iterator cur = ll.begin();
+      std::list<hname_t>::const_iterator cur = ll.begin();
       out << *cur;
       ++ cur;
       while (cur != ll.end()) {

INSTALL

@@ -19,8 +19,8 @@ diffs or instructions to the address given in the `README' so they can
 be considered for the next release.  If at some point `config.cache'
 contains results you don't want to keep, you may remove or edit it.
 
-   The file `configure.in' is used to create `configure' by a program
-called `autoconf'.  You only need `configure.in' if you want to change
+   The file `configure.ac' is used to create `configure' by a program
+called `autoconf'.  You only need `configure.ac' if you want to change
 it or regenerate `configure' using a newer version of `autoconf'.
 
 The simplest way to compile this package is:
@@ -178,4 +178,3 @@ operates.
      script, and exit.
 
 `configure' also accepts some other, not widely useful, options.
-

Makefile.in

@@ -70,7 +70,8 @@ dllib=@DLLIB@
 HOSTCC = @CC@
 HOSTCFLAGS = @WARNING_FLAGS@ @WARNING_FLAGS_CC@ @CFLAGS@
 
-CC = @CC@
+BUILDCC = @CC_FOR_BUILD@
+BUILDEXT = @BUILD_EXEEXT@
 CXX = @CXX@
 DLLTOOL = @DLLTOOL@
 INSTALL = @INSTALL@
@@ -100,7 +101,7 @@ CTARGETFLAGS = @CTARGETFLAGS@
 M = LineInfo.o StringHeap.o
 
 TT = t-dll.o t-dll-api.o t-dll-expr.o t-dll-proc.o t-dll-analog.o
-FF = cprop.o nodangle.o synth.o synth2.o syn-rules.o
+FF = cprop.o exposenodes.o nodangle.o synth.o synth2.o syn-rules.o
 
 O = main.o async.o design_dump.o discipline.o dup_expr.o elaborate.o \
     elab_expr.o elaborate_analog.o elab_lval.o elab_net.o \
@@ -116,10 +117,10 @@ O = main.o async.o design_dump.o discipline.o dup_expr.o elaborate.o \
     net_udp.o pad_to_width.o parse.o parse_misc.o pform.o pform_analog.o \
     pform_disciplines.o pform_dump.o pform_package.o pform_pclass.o \
     pform_class_type.o pform_string_type.o pform_struct_type.o pform_types.o \
-    symbol_search.o sync.o sys_funcs.o verinum.o verireal.o target.o \
-    Attrib.o HName.o Module.o PClass.o PDelays.o PEvent.o PExpr.o PGate.o \
-    PGenerate.o PPackage.o PScope.o PSpec.o PTask.o PUdp.o PFunction.o PWire.o \
-    Statement.o AStatement.o $M $(FF) $(TT)
+    symbol_search.o sync.o sys_funcs.o verinum.o verireal.o vpi_modules.o target.o \
+    Attrib.o HName.o Module.o PClass.o PDelays.o PEvent.o PExpr.o PFunction.o \
+    PGate.o PGenerate.o PModport.o PNamedItem.o PPackage.o PScope.o PSpec.o \
+    PTask.o PUdp.o PWire.o Statement.o AStatement.o $M $(FF) $(TT)
 
 all: dep config.h _pli_types.h version_tag.h ivl@EXEEXT@ version.exe iverilog-vpi.man
 	$(foreach dir,$(SUBDIRS),$(MAKE) -C $(dir) $@ && ) true
@@ -127,9 +128,9 @@ all: dep config.h _pli_types.h version_tag.h ivl@EXEEXT@ version.exe iverilog-vp
 # In the windows world, the installer will need a dosify program to
 # dosify text files.
 ifeq (@MINGW32@,yes)
-all: dosify.exe
-dosify.exe: $(srcdir)/dosify.c
-	$(HOSTCC) $(HOSTCFLAGS) -o dosify.exe $(srcdir)/dosify.c
+all: dosify$(BUILDEXT)
+dosify$(BUILDEXT): $(srcdir)/dosify.c
+	$(BUILDCC) $(CFLAGS) -o dosify$(BUILDEXT) $(srcdir)/dosify.c
 endif
 
 # This rule rules the compiler in the trivial hello.vl program to make
@@ -137,7 +138,7 @@ endif
 check: all
 	$(foreach dir,$(SUBDIRS),$(MAKE) -C $(dir) $@ && ) true
 	test -r check.conf || cp $(srcdir)/check.conf .
-	driver/iverilog -B. -BPivlpp -tcheck -ocheck.vvp $(srcdir)/examples/hello.vl
+	driver/iverilog -B. -BMvpi -BPivlpp -tcheck -ocheck.vvp $(srcdir)/examples/hello.vl
 ifeq (@WIN32@,yes)
 ifeq (@install_suffix@,)
 	vvp/vvp -M- -M./vpi ./check.vvp | grep 'Hello, World'
@@ -156,7 +157,7 @@ clean:
 	$(foreach dir,$(SUBDIRS),$(MAKE) -C $(dir) $@ && ) true
 	rm -f *.o parse.cc parse.h lexor.cc
 	rm -f ivl.exp iverilog-vpi.man iverilog-vpi.pdf iverilog-vpi.ps
-	rm -f parse.output syn-rules.output dosify.exe ivl@EXEEXT@ check.vvp
+	rm -f parse.output syn-rules.output dosify$(BUILDEXT) ivl@EXEEXT@ check.vvp
 	rm -f lexor_keyword.cc libivl.a libvpi.a iverilog-vpi syn-rules.cc
 	rm -rf dep
 	rm -f version.exe
@@ -174,7 +175,8 @@ endif
 	rm -rf autom4te.cache
 
 cppcheck: $(O:.o=.cc) $(srcdir)/dosify.c $(srcdir)/version.c
-	cppcheck --enable=all -f --suppressions-list=$(srcdir)/cppcheck.sup \
+	cppcheck --enable=all --std=posix --std=c99 --std=c++03 -f \
+	         --suppressions-list=$(srcdir)/cppcheck.sup \
 	         -UYYPARSE_PARAM -UYYPRINT -Ushort -Usize_t -Uyyoverflow \
 	         -UYYTYPE_INT8 -UYYTYPE_INT16 -UYYTYPE_UINT8 -UYYTYPE_UINT16 \
 	         --relative-paths=$(srcdir) $(INCLUDE_PATH) $^
@@ -200,7 +202,7 @@ stamp-_pli_types-h: $(srcdir)/_pli_types.h.in config.status
 	./config.status _pli_types.h
 _pli_types.h: stamp-_pli_types-h
 
-$(srcdir)/configure: $(srcdir)/configure.in $(srcdir)/aclocal.m4
+$(srcdir)/configure: $(srcdir)/configure.ac $(srcdir)/aclocal.m4
 	cd $(srcdir) && autoconf
 
 config.status: $(srcdir)/configure
@@ -239,7 +241,7 @@ iverilog-vpi: $(srcdir)/iverilog-vpi.sh Makefile
 endif
 
 version.exe: $(srcdir)/version.c $(srcdir)/version_base.h version_tag.h
-	$(HOSTCC) $(HOSTCFLAGS) -o version.exe -I. -I$(srcdir) $(srcdir)/version.c
+	$(BUILDCC) $(CFLAGS) -o version.exe -I. -I$(srcdir) $(srcdir)/version.c
 
 %.o: %.cc config.h
 	$(CXX) $(CPPFLAGS) $(CXXFLAGS) @DEPENDENCY_FLAG@ -c $< -o $*.o
@@ -252,11 +254,9 @@ lexor.o: lexor.cc parse.h
 
 parse.o: parse.cc
 
-# Build this in two steps to avoid parallel build issues (see pr3462585)
-parse.cc: $(srcdir)/parse.y
-	$(YACC) --verbose -t -p VL -d -o $@ $<
-parse.h: parse.cc
-	mv parse.cc.h $@ 2>/dev/null || mv parse.hh $@
+# Use pattern rules to avoid parallel build issues (see pr3462585)
+parse%cc parse%h: $(srcdir)/parse%y
+	$(YACC) --verbose -t -p VL --defines=parse.h -o parse.cc $<
 
 syn-rules.cc: $(srcdir)/syn-rules.y
 	$(YACC) --verbose -t -p syn_ -o $@ $<
@@ -292,7 +292,7 @@ endif
 version_tag.h version:
 	@if $(GIT_PRESENT) && test -d $(srcdir)/.git; then \
 	    echo "Using git-describe for VERSION_TAG"; \
-	    tmp=`$(GIT) --git-dir $(srcdir)/.git describe --always --dirty \
+	    tmp=`(cd $(srcdir) && $(GIT) describe --always --dirty) \
 		   | sed -e 's;\(.*\);#define VERSION_TAG "\1";'`; \
 	    echo "$$tmp" | diff - version_tag.h > /dev/null 2>&1 || echo "$$tmp" > version_tag.h || exit 1; \
 	elif test -r $(srcdir)/version_tag.h; then \
@@ -305,66 +305,61 @@ version_tag.h version:
 
 ifeq (@MINGW32@,yes)
 ifeq ($(MAN),none)
-INSTALL_DOC = $(mandir)/man1/iverilog-vpi$(suffix).1
+INSTALL_DOC = installman
 else
 ifeq ($(PS2PDF),none)
-INSTALL_DOC = $(mandir)/man1/iverilog-vpi$(suffix).1
+INSTALL_DOC = installman
 else
-INSTALL_DOC = $(prefix)/iverilog-vpi$(suffix).pdf $(mandir)/man1/iverilog-vpi$(suffix).1
+INSTALL_DOC = installpdf installman
 all: dep iverilog-vpi.pdf
 endif
 endif
 INSTALL_DOCDIR = $(mandir)/man1
 else
-INSTALL_DOC = $(mandir)/man1/iverilog-vpi$(suffix).1
+INSTALL_DOC = installman
 INSTALL_DOCDIR = $(mandir)/man1
 endif
 
 ifeq (@MINGW32@,yes)
 WIN32_INSTALL =
 else
-WIN32_INSTALL = $(bindir)/iverilog-vpi$(suffix)
+WIN32_INSTALL = installwin32
 endif
 
-install: all installdirs $(libdir)/ivl$(suffix)/ivl@EXEEXT@  $(libdir)/ivl$(suffix)/include/constants.vams $(libdir)/ivl$(suffix)/include/disciplines.vams $(includedir)/ivl_target.h $(includedir)/_pli_types.h $(includedir)/sv_vpi_user.h $(includedir)/vpi_user.h $(includedir)/acc_user.h $(includedir)/veriuser.h $(WIN32_INSTALL) $(INSTALL_DOC)
+install: all installdirs installfiles
 	$(foreach dir,$(SUBDIRS),$(MAKE) -C $(dir) $@ && ) true
 
-$(bindir)/iverilog-vpi$(suffix): ./iverilog-vpi
+F = ./ivl@EXEEXT@ \
+	$(srcdir)/constants.vams \
+	$(srcdir)/disciplines.vams \
+	$(srcdir)/ivl_target.h \
+	./_pli_types.h \
+	$(srcdir)/sv_vpi_user.h \
+	$(srcdir)/vpi_user.h \
+	$(srcdir)/acc_user.h \
+	$(srcdir)/veriuser.h \
+	$(INSTALL_DOC) \
+	$(WIN32_INSTALL)
+
+installwin32: ./iverilog-vpi installdirs
 	$(INSTALL_SCRIPT) ./iverilog-vpi "$(DESTDIR)$(bindir)/iverilog-vpi$(suffix)"
 
-$(libdir)/ivl$(suffix)/ivl@EXEEXT@: ./ivl@EXEEXT@
-	$(INSTALL_PROGRAM) ./ivl@EXEEXT@ "$(DESTDIR)$(libdir)/ivl$(suffix)/ivl@EXEEXT@"
-
-$(libdir)/ivl$(suffix)/include/constants.vams: $(srcdir)/constants.vams
-	$(INSTALL_DATA) $(srcdir)/constants.vams "$(DESTDIR)$(libdir)/ivl$(suffix)/include/constants.vams"
-
-$(libdir)/ivl$(suffix)/include/disciplines.vams: $(srcdir)/disciplines.vams
-	$(INSTALL_DATA) $(srcdir)/disciplines.vams "$(DESTDIR)$(libdir)/ivl$(suffix)/include/disciplines.vams"
-
-$(includedir)/ivl_target.h: $(srcdir)/ivl_target.h
-	$(INSTALL_DATA) $(srcdir)/ivl_target.h "$(DESTDIR)$(includedir)/ivl_target.h"
-
-$(includedir)/_pli_types.h: _pli_types.h
-	$(INSTALL_DATA) $< "$(DESTDIR)$(includedir)/_pli_types.h"
-
-$(includedir)/sv_vpi_user.h: $(srcdir)/sv_vpi_user.h
-	$(INSTALL_DATA) $(srcdir)/sv_vpi_user.h "$(DESTDIR)$(includedir)/sv_vpi_user.h"
-
-$(includedir)/vpi_user.h: $(srcdir)/vpi_user.h
-	$(INSTALL_DATA) $(srcdir)/vpi_user.h "$(DESTDIR)$(includedir)/vpi_user.h"
-
-$(includedir)/acc_user.h: $(srcdir)/acc_user.h
-	$(INSTALL_DATA) $(srcdir)/acc_user.h "$(DESTDIR)$(includedir)/acc_user.h"
-
-$(includedir)/veriuser.h: $(srcdir)/veriuser.h
-	$(INSTALL_DATA) $(srcdir)/veriuser.h "$(DESTDIR)$(includedir)/veriuser.h"
-
-$(mandir)/man1/iverilog-vpi$(suffix).1: iverilog-vpi.man
+installman: iverilog-vpi.man installdirs
 	$(INSTALL_DATA) iverilog-vpi.man "$(DESTDIR)$(mandir)/man1/iverilog-vpi$(suffix).1"
 
-$(prefix)/iverilog-vpi$(suffix).pdf: iverilog-vpi.pdf
+installpdf: iverilog-vpi.pdf installdirs
 	$(INSTALL_DATA) iverilog-vpi.pdf "$(DESTDIR)$(prefix)/iverilog-vpi$(suffix).pdf"
 
+installfiles: $(F) | installdirs
+	$(INSTALL_PROGRAM) ./ivl@EXEEXT@ "$(DESTDIR)$(libdir)/ivl$(suffix)/ivl@EXEEXT@"
+	$(INSTALL_DATA) $(srcdir)/constants.vams "$(DESTDIR)$(libdir)/ivl$(suffix)/include/constants.vams"
+	$(INSTALL_DATA) $(srcdir)/disciplines.vams "$(DESTDIR)$(libdir)/ivl$(suffix)/include/disciplines.vams"
+	$(INSTALL_DATA) $(srcdir)/ivl_target.h "$(DESTDIR)$(includedir)/ivl_target.h"
+	$(INSTALL_DATA) ./_pli_types.h "$(DESTDIR)$(includedir)/_pli_types.h"
+	$(INSTALL_DATA) $(srcdir)/sv_vpi_user.h "$(DESTDIR)$(includedir)/sv_vpi_user.h"
+	$(INSTALL_DATA) $(srcdir)/vpi_user.h "$(DESTDIR)$(includedir)/vpi_user.h"
+	$(INSTALL_DATA) $(srcdir)/acc_user.h "$(DESTDIR)$(includedir)/acc_user.h"
+	$(INSTALL_DATA) $(srcdir)/veriuser.h "$(DESTDIR)$(includedir)/veriuser.h"
 
 installdirs: $(srcdir)/mkinstalldirs
 	$(srcdir)/mkinstalldirs "$(DESTDIR)$(bindir)" \

Module.cc

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1998-2010 Stephen Williams ([email protected])
+ * Copyright (c) 1998-2019 Stephen Williams ([email protected])
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -24,6 +24,8 @@
 # include  "PWire.h"
 # include  <cassert>
 
+using namespace std;
+
 list<Module::named_expr_t> Module::user_defparms;
 
 /* n is a permallocated string. */
@@ -32,12 +34,9 @@ Module::Module(LexicalScope*parent, perm_string n)
 {
       library_flag = false;
       is_cell = false;
+      is_interface = false;
       program_block = false;
       uc_drive = UCD_NONE;
-      timescale_warn_done = false;
-      time_unit = 0;
-      time_precision = 0;
-      time_from_timescale = false;
 }
 
 Module::~Module()
@@ -94,13 +93,15 @@ perm_string Module::get_port_name(unsigned idx) const
 {
 
       assert(idx < ports.size());
-      if (ports[idx] == 0) {
+      if (ports[idx] == 0 || ports[idx]->name.str() == 0) {
               /* It is possible to have undeclared ports. These
                  are ports that are skipped in the declaration,
                  for example like so: module foo(x ,, y); The
                  port between x and y is unnamed and thus
-                 inaccessible to binding by name. */
-            return perm_string::literal("");
+                 inaccessible to binding by name. Port references
+		 that aren't simple or escaped identifiers are
+		 also inaccessible to binding by name. */
+            return perm_string::literal("unnamed");
       }
       return ports[idx]->name;
 }
@@ -123,3 +124,13 @@ const list<PGate*>& Module::get_gates() const
 {
       return gates_;
 }
+
+PNamedItem::SymbolType Module::symbol_type() const
+{
+      if (program_block)
+            return PROGRAM;
+      if (is_interface)
+            return INTERFACE;
+
+      return MODULE;
+}

Module.h

@@ -1,7 +1,7 @@
 #ifndef IVL_Module_H
 #define IVL_Module_H
 /*
- * Copyright (c) 1998-2014 Stephen Williams ([email protected])
+ * Copyright (c) 1998-2019 Stephen Williams ([email protected])
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -28,13 +28,14 @@
 # include  "HName.h"
 # include  "named.h"
 # include  "PScope.h"
-# include  "LineInfo.h"
+# include  "PNamedItem.h"
 # include  "netlist.h"
 # include  "pform_types.h"
 class PExpr;
 class PEIdent;
 class PGate;
 class PGenerate;
+class PModport;
 class PSpecPath;
 class PTask;
 class PFunction;
@@ -47,9 +48,13 @@ class NetScope;
  * A module is a named container and scope. A module holds a bunch of
  * semantic quantities such as wires and gates. The module is
  * therefore the handle for grasping the described circuit.
+ *
+ * SystemVerilog introduces program blocks and interfaces. These have
+ * much in common with modules, so the Module class is used to represent
+ * these containers as well.
  */
 
-class Module : public PScopeExtra, public LineInfo {
+class Module : public PScopeExtra, public PNamedItem {
 
 	/* The module ports are in general a vector of port_t
 	   objects. Each port has a name and an ordered list of
@@ -59,12 +64,12 @@ class Module : public PScopeExtra, public LineInfo {
     public:
       struct port_t {
 	    perm_string name;
-	    vector<PEIdent*> expr;
+	    std::vector<PEIdent*> expr;
       };
 
     public:
 	/* The name passed here is the module name, not the instance
-	   name. This make must be a permallocated string. */
+	   name. This name must be a permallocated string. */
       explicit Module(LexicalScope*parent, perm_string name);
       ~Module();
 
@@ -81,21 +86,26 @@ class Module : public PScopeExtra, public LineInfo {
 	   restrictions and slightly modify scheduling semantics. */
       bool program_block;
 
+	/* This is true if the module represents a interface
+	   instead of a module/cell. Interfaces have different
+	   content restrictions and some extra allowed items. */
+      bool is_interface;
+
       enum UCDriveType { UCD_NONE, UCD_PULL0, UCD_PULL1 };
       UCDriveType uc_drive;
 
 	/* specparams are simpler than other parameters, in that they
 	   can have a range, but not an explicit type. The restrictions
 	   are enforced by the parser. */
-      map<perm_string,param_expr_t>specparams;
+      std::map<perm_string,param_expr_t*>specparams;
 
 	/* The module also has defparam assignments which don't create
 	   new parameters within the module, but may be used to set
 	   values within this module (when instantiated) or in other
 	   instantiated modules. */
-      typedef pair<pform_name_t,PExpr*> named_expr_t;
-      list<named_expr_t>defparms;
-      static list<named_expr_t>user_defparms;
+      typedef std::pair<pform_name_t,PExpr*> named_expr_t;
+      std::list<named_expr_t>defparms;
+      static std::list<named_expr_t>user_defparms;
 
         /* Parameters may be overridden at instantiation time;
            the overrides do not contain explicit parameter names,
@@ -103,29 +113,28 @@ class Module : public PScopeExtra, public LineInfo {
            appear in the instantiated module.  Therefore a
            list of names in module-order is needed to pass from
            a parameter-index to its name. */
-      list<perm_string> param_names;
+      std::list<perm_string> param_names;
 
 	/* This is an array of port descriptors, which is in turn a
 	   named array of PEident pointers. */
-      vector<port_t*> ports;
+      std::vector<port_t*> ports;
 
-      map<perm_string,PExpr*> attributes;
-
-	/* These are the timescale for this module. The default is
-	   set by the `timescale directive. */
-      int time_unit, time_precision;
-      bool time_from_timescale;
-      bool timescale_warn_done;
+      std::map<perm_string,PExpr*> attributes;
 
 	/* The module has a list of generate schemes that appear in
 	   the module definition. These are used at elaboration time. */
-      list<PGenerate*> generate_schemes;
+      std::list<PGenerate*> generate_schemes;
 
 	/* Nested modules are placed here, and are not elaborated
 	   unless they are instantiated, implicitly or explicitly. */
       std::map<perm_string,Module*> nested_modules;
 
-      list<PSpecPath*> specify_paths;
+	/* An interface can contain one or more named modport lists.
+           The parser will ensure these don't appear in modules or
+           program blocks. */
+      std::map<perm_string,PModport*> modports;
+
+      std::list<PSpecPath*> specify_paths;
 
 	// The mod_name() is the name of the module type.
       perm_string mod_name() const { return pscope_name(); }
@@ -133,7 +142,7 @@ class Module : public PScopeExtra, public LineInfo {
       void add_gate(PGate*gate);
 
       unsigned port_count() const;
-      const vector<PEIdent*>& get_port(unsigned idx) const;
+      const std::vector<PEIdent*>& get_port(unsigned idx) const;
       unsigned find_port(const char*name) const;
 
       // Return port name ("" for undeclared port)
@@ -141,19 +150,21 @@ class Module : public PScopeExtra, public LineInfo {
 
       PGate* get_gate(perm_string name);
 
-      const list<PGate*>& get_gates() const;
+      const std::list<PGate*>& get_gates() const;
 
-      void dump(ostream&out) const;
+      void dump(std::ostream&out) const;
       bool elaborate(Design*, NetScope*scope) const;
 
-      typedef map<perm_string,PExpr*> replace_t;
+      typedef std::map<perm_string,PExpr*> replace_t;
       bool elaborate_scope(Design*, NetScope*scope, const replace_t&rep);
 
       bool elaborate_sig(Design*, NetScope*scope) const;
 
+      SymbolType symbol_type() const;
+
     private:
-      void dump_specparams_(ostream&out, unsigned indent) const;
-      list<PGate*> gates_;
+      void dump_specparams_(std::ostream&out, unsigned indent) const;
+      std::list<PGate*> gates_;
 
     private: // Not implemented
       Module(const Module&);

PClass.cc

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012 Stephen Williams ([email protected])
+ * Copyright (c) 2012-2019 Stephen Williams ([email protected])
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -28,3 +28,8 @@ PClass::PClass(perm_string name, LexicalScope*parent)
 PClass::~PClass()
 {
 }
+
+PNamedItem::SymbolType PClass::symbol_type() const
+{
+      return CLASS;
+}

PClass.h

@@ -1,7 +1,7 @@
 #ifndef IVL_PClass_H
 #define IVL_PClass_H
 /*
- * Copyright (c) 2012-2014 Stephen Williams ([email protected])
+ * Copyright (c) 2012-2019 Stephen Williams ([email protected])
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -20,7 +20,7 @@
  */
 
 # include  "PScope.h"
-# include  "LineInfo.h"
+# include  "PNamedItem.h"
 # include  "StringHeap.h"
 # include  <iostream>
 
@@ -32,7 +32,7 @@ class PChainConstructor;
  * collected.
  */
 
-class PClass : public PScopeExtra, public LineInfo {
+class PClass : public PScopeExtra, public PNamedItem {
 
     public:
       explicit PClass (perm_string name, LexicalScope*parent);
@@ -40,6 +40,8 @@ class PClass : public PScopeExtra, public LineInfo {
 
       void dump(std::ostream&out, unsigned indent) const;
 
+      SymbolType symbol_type() const;
+
     public:
       class_type_t*type;
 };

PDelays.cc

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1999-2011 Stephen Williams ([email protected])
+ * Copyright (c) 1999-2021 Stephen Williams ([email protected])
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -26,10 +26,7 @@
 # include  "verinum.h"
 # include  "netmisc.h"
 
-bool dly_used_no_timescale = false;
-bool dly_used_timescale = false;
-bool display_ts_dly_warning = true;
-
+using namespace std;
 
 PDelays::PDelays()
 {
@@ -80,19 +77,7 @@ static NetExpr*calculate_val(Design*des, NetScope*scope, PExpr*expr)
 {
       NetExpr*dex = elab_and_eval(des, scope, expr, -1);
 
-	/* Print a warning if we find default and `timescale based
-	 * delays in the design, since this is likely an error. */
-      if (scope->time_from_timescale()) dly_used_timescale = true;
-      else dly_used_no_timescale = true;
-
-      if (display_ts_dly_warning &&
-          dly_used_no_timescale && dly_used_timescale) {
-	    cerr << "warning: Found both default and "
-	            "`timescale based delays. Use" << endl;
-	    cerr << "         -Wtimescale to find the "
-	            "module(s) with no `timescale." << endl;
-	    display_ts_dly_warning = false;
-      }
+      check_for_inconsistent_delays(scope);
 
 	/* If the delay expression is a real constant or vector
 	   constant, then evaluate it, scale it to the local time

PDelays.h

@@ -1,7 +1,7 @@
 #ifndef IVL_PDelays_H
 #define IVL_PDelays_H
 /*
- * Copyright (c) 1999-2014 Stephen Williams ([email protected])
+ * Copyright (c) 1999-2021 Stephen Williams ([email protected])
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -24,12 +24,6 @@
 # include  <list>
 # include  <iostream>
 
-#ifdef __GNUC__
-#if __GNUC__ > 2
-using namespace std;
-#endif
-#endif
-
 class Design;
 class NetScope;
 class NetExpr;
@@ -49,7 +43,7 @@ class PDelays {
 	   this object takes ownership of the expressions, and will
 	   delete it in the destructor. */
       void set_delay(PExpr*);
-      void set_delays(const list<PExpr*>*del, bool delete_flag=true);
+      void set_delays(const std::list<PExpr*>*del, bool delete_flag=true);
 
       unsigned delay_count() const;
 
@@ -59,7 +53,7 @@ class PDelays {
 		       NetExpr*&decay_time,
 		       bool as_nets_flag =false) const;
 
-      void dump_delays(ostream&out) const;
+      void dump_delays(std::ostream&out) const;
 
     private:
       PExpr* delay_[3];
@@ -70,6 +64,6 @@ class PDelays {
       PDelays& operator= (const PDelays&);
 };
 
-ostream& operator << (ostream&o, const PDelays&);
+std::ostream& operator << (std::ostream&o, const PDelays&);
 
 #endif /* IVL_PDelays_H */

PEvent.cc

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2004 Stephen Williams ([email protected])
+ * Copyright (c) 2004-2019 Stephen Williams ([email protected])
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -35,3 +35,7 @@ perm_string  PEvent::name() const
       return name_;
 }
 
+PNamedItem::SymbolType PEvent::symbol_type() const
+{
+      return EVENT;
+}

PEvent.h

@@ -1,7 +1,7 @@
 #ifndef IVL_PEvent_H
 #define IVL_PEvent_H
 /*
- * Copyright (c) 2000-2014 Stephen Williams ([email protected])
+ * Copyright (c) 2000-2019 Stephen Williams ([email protected])
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -19,7 +19,7 @@
  *    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
  */
 
-# include  "LineInfo.h"
+# include  "PNamedItem.h"
 # include  "StringHeap.h"
 # include  <string>
 
@@ -31,7 +31,7 @@ class NetScope;
  * are declared in Verilog as ``event foo;'' The name passed to the
  * constructor is the "foo" part of the declaration.
  */
-class PEvent : public LineInfo {
+class PEvent : public PNamedItem {
 
     public:
 	// The name is a perm-allocated string. It is the simple name
@@ -43,6 +43,8 @@ class PEvent : public LineInfo {
 
       void elaborate_scope(Design*des, NetScope*scope) const;
 
+      SymbolType symbol_type() const;
+
     private:
       perm_string name_;
 

PExpr.cc

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1998-2012 Stephen Williams <[email protected]>
+ * Copyright (c) 1998-2020 Stephen Williams <[email protected]>
  * Copyright CERN 2013 / Stephen Williams ([email protected])
  *
  *    This source code is free software; you can redistribute it
@@ -30,6 +30,8 @@
 # include  "util.h"
 # include  <typeinfo>
 
+using namespace std;
+
 PExpr::PExpr()
 {
       expr_type_   = IVL_VT_NO_TYPE;
@@ -126,9 +128,8 @@ PEBinary::~PEBinary()
 
 void PEBinary::declare_implicit_nets(LexicalScope*scope, NetNet::Type type)
 {
-      assert(left_ && right_);
-      left_->declare_implicit_nets(scope, type);
-      right_->declare_implicit_nets(scope, type);
+      if (left_) left_->declare_implicit_nets(scope, type);
+      if (right_) right_->declare_implicit_nets(scope, type);
 }
 
 bool PEBinary::has_aa_term(Design*des, NetScope*scope) const
@@ -137,7 +138,7 @@ bool PEBinary::has_aa_term(Design*des, NetScope*scope) const
       return left_->has_aa_term(des, scope) || right_->has_aa_term(des, scope);
 }
 
-PECastSize::PECastSize(unsigned si, PExpr*b)
+PECastSize::PECastSize(PExpr*si, PExpr*b)
 : size_(si), base_(b)
 {
 }
@@ -169,7 +170,7 @@ PEBComp::~PEBComp()
 PEBLogic::PEBLogic(char op, PExpr*l, PExpr*r)
 : PEBinary(op, l, r)
 {
-      assert(op == 'a' || op == 'o');
+      assert(op == 'a' || op == 'o' || op == 'q' || op == 'Q');
 }
 
 PEBLogic::~PEBLogic()
@@ -204,12 +205,12 @@ PEBShift::~PEBShift()
 }
 
 PECallFunction::PECallFunction(const pform_name_t&n, const vector<PExpr *> &parms)
-: package_(0), path_(n), parms_(parms)
+: package_(0), path_(n), parms_(parms), is_overridden_(false)
 {
 }
 
 PECallFunction::PECallFunction(PPackage*pkg, const pform_name_t&n, const vector<PExpr *> &parms)
-: package_(pkg), path_(n), parms_(parms)
+: package_(pkg), path_(n), parms_(parms), is_overridden_(false)
 {
 }
 
@@ -222,7 +223,7 @@ static pform_name_t pn_from_ps(perm_string n)
 }
 
 PECallFunction::PECallFunction(PPackage*pkg, perm_string n, const list<PExpr *> &parms)
-: package_(pkg), path_(pn_from_ps(n)), parms_(parms.size())
+: package_(pkg), path_(pn_from_ps(n)), parms_(parms.size()), is_overridden_(false)
 {
       int tmp_idx = 0;
       assert(parms_.size() == parms.size());
@@ -232,18 +233,18 @@ PECallFunction::PECallFunction(PPackage*pkg, perm_string n, const list<PExpr *>
 }
 
 PECallFunction::PECallFunction(perm_string n, const vector<PExpr*>&parms)
-: package_(0), path_(pn_from_ps(n)), parms_(parms)
+: package_(0), path_(pn_from_ps(n)), parms_(parms), is_overridden_(false)
 {
 }
 
 PECallFunction::PECallFunction(perm_string n)
-: package_(0), path_(pn_from_ps(n))
+: package_(0), path_(pn_from_ps(n)), is_overridden_(false)
 {
 }
 
 // NOTE: Anachronism. Try to work all use of svector out.
 PECallFunction::PECallFunction(const pform_name_t&n, const list<PExpr *> &parms)
-: package_(0), path_(n), parms_(parms.size())
+: package_(0), path_(n), parms_(parms.size()), is_overridden_(false)
 {
       int tmp_idx = 0;
       assert(parms_.size() == parms.size());
@@ -253,7 +254,7 @@ PECallFunction::PECallFunction(const pform_name_t&n, const list<PExpr *> &parms)
 }
 
 PECallFunction::PECallFunction(perm_string n, const list<PExpr*>&parms)
-: package_(0), path_(pn_from_ps(n)), parms_(parms.size())
+: package_(0), path_(pn_from_ps(n)), parms_(parms.size()), is_overridden_(false)
 {
       int tmp_idx = 0;
       assert(parms_.size() == parms.size());

PExpr.h

@@ -1,7 +1,7 @@
 #ifndef IVL_PExpr_H
 #define IVL_PExpr_H
 /*
- * Copyright (c) 1998-2014 Stephen Williams <[email protected]>
+ * Copyright (c) 1998-2019 Stephen Williams <[email protected]>
  * Copyright CERN 2013 / Stephen Williams ([email protected])
  *
  *    This source code is free software; you can redistribute it
@@ -60,7 +60,7 @@ class PExpr : public LineInfo {
       PExpr();
       virtual ~PExpr();
 
-      virtual void dump(ostream&) const;
+      virtual void dump(std::ostream&) const;
 
         // This method tests whether the expression contains any identifiers
         // that have not been previously declared in the specified scope or
@@ -202,7 +202,7 @@ class PExpr : public LineInfo {
       PExpr& operator= (const PExpr&);
 };
 
-ostream& operator << (ostream&, const PExpr&);
+std::ostream& operator << (std::ostream&, const PExpr&);
 
 class PEAssignPattern : public PExpr {
     public:
@@ -230,11 +230,11 @@ class PEAssignPattern : public PExpr {
 class PEConcat : public PExpr {
 
     public:
-      PEConcat(const list<PExpr*>&p, PExpr*r =0);
+      explicit PEConcat(const std::list<PExpr*>&p, PExpr*r =0);
       ~PEConcat();
 
       virtual verinum* eval_const(Design*des, NetScope*sc) const;
-      virtual void dump(ostream&) const;
+      virtual void dump(std::ostream&) const;
 
       virtual void declare_implicit_nets(LexicalScope*scope, NetNet::Type type);
 
@@ -261,7 +261,7 @@ class PEConcat : public PExpr {
       NetNet* elaborate_lnet_common_(Design*des, NetScope*scope,
 				     bool bidirectional_flag) const;
     private:
-      vector<PExpr*>parms_;
+      std::vector<PExpr*>parms_;
       std::valarray<width_mode_t>width_modes_;
 
       PExpr*repeat_;
@@ -289,7 +289,7 @@ class PEEvent : public PExpr {
       edge_t type() const;
       PExpr* expr() const;
 
-      virtual void dump(ostream&) const;
+      virtual void dump(std::ostream&) const;
 
       virtual bool has_aa_term(Design*des, NetScope*scope) const;
 
@@ -322,7 +322,7 @@ class PEFNumber : public PExpr {
 				     unsigned expr_wid,
                                      unsigned flags) const;
 
-      virtual void dump(ostream&) const;
+      virtual void dump(std::ostream&) const;
 
     private:
       verireal*value_;
@@ -340,7 +340,7 @@ class PEIdent : public PExpr {
 	// current identifier.
       void append_name(perm_string);
 
-      virtual void dump(ostream&) const;
+      virtual void dump(std::ostream&) const;
 
       virtual void declare_implicit_nets(LexicalScope*scope, NetNet::Type type);
 
@@ -379,6 +379,8 @@ class PEIdent : public PExpr {
 
       virtual bool is_collapsible_net(Design*des, NetScope*scope) const;
 
+      const PPackage* package() const { return package_; }
+
       const pform_name_t& path() const { return path_; }
 
     private:
@@ -433,10 +435,10 @@ class PEIdent : public PExpr {
 				   bool need_const_idx) const;
       NetAssign_*elaborate_lval_net_class_member_(Design*, NetScope*,
 						   NetNet*,
-						   const perm_string&) const;
+						   pform_name_t) const;
       bool elaborate_lval_net_packed_member_(Design*, NetScope*,
 					     NetAssign_*,
-					     const perm_string&) const;
+					     pform_name_t member_path) const;
       bool elaborate_lval_darray_bit_(Design*, NetScope*,
 				       NetAssign_*) const;
 
@@ -521,17 +523,13 @@ class PEIdent : public PExpr {
 					   unsigned flags) const;
 
       unsigned test_width_method_(Design*des, NetScope*scope, width_mode_t&mode);
-      NetExpr*elaborate_expr_method_(Design*des,
-				     NetScope*scope,
-				     unsigned expr_wid,
-				     unsigned flags) const;
+
 
     private:
       NetNet* elaborate_lnet_common_(Design*des, NetScope*scope,
 				     bool bidirectional_flag) const;
 
-      NetAssign_*scan_lname_for_nested_members_(Design*des, NetScope*scope,
-						       const pform_name_t&path) const;
+
       bool eval_part_select_(Design*des, NetScope*scope, NetNet*sig,
 			     long&midx, long&lidx) const;
 };
@@ -542,7 +540,7 @@ class PENewArray : public PExpr {
       explicit PENewArray (PExpr*s, PExpr*i);
       ~PENewArray();
 
-      virtual void dump(ostream&) const;
+      virtual void dump(std::ostream&) const;
       virtual unsigned test_width(Design*des, NetScope*scope,
 				  width_mode_t&mode);
       virtual NetExpr*elaborate_expr(Design*des, NetScope*scope,
@@ -566,7 +564,7 @@ class PENewClass : public PExpr {
 
       ~PENewClass();
 
-      virtual void dump(ostream&) const;
+      virtual void dump(std::ostream&) const;
 	// Class objects don't have a useful width, but the expression
 	// is IVL_VT_CLASS.
       virtual unsigned test_width(Design*des, NetScope*scope,
@@ -591,7 +589,7 @@ class PENewCopy : public PExpr {
       explicit PENewCopy(PExpr*src);
       ~PENewCopy();
 
-      virtual void dump(ostream&) const;
+      virtual void dump(std::ostream&) const;
 	// Class objects don't have a useful width, but the expression
 	// is IVL_VT_CLASS.
       virtual unsigned test_width(Design*des, NetScope*scope,
@@ -611,7 +609,7 @@ class PENull : public PExpr {
       explicit PENull();
       ~PENull();
 
-      virtual void dump(ostream&) const;
+      virtual void dump(std::ostream&) const;
       virtual unsigned test_width(Design*des, NetScope*scope,
 				  width_mode_t&mode);
       virtual NetExpr*elaborate_expr(Design*des, NetScope*scope,
@@ -629,7 +627,7 @@ class PENumber : public PExpr {
 
       const verinum& value() const;
 
-      virtual void dump(ostream&) const;
+      virtual void dump(std::ostream&) const;
       virtual unsigned test_width(Design*des, NetScope*scope,
 				  width_mode_t&mode);
 
@@ -663,8 +661,8 @@ class PEString : public PExpr {
       explicit PEString(char*s);
       ~PEString();
 
-      string value() const;
-      virtual void dump(ostream&) const;
+      std::string value() const;
+      virtual void dump(std::ostream&) const;
 
       virtual unsigned test_width(Design*des, NetScope*scope,
 				  width_mode_t&mode);
@@ -685,7 +683,7 @@ class PETypename : public PExpr {
       explicit PETypename(data_type_t*data_type);
       ~PETypename();
 
-      virtual void dump(ostream&) const;
+      virtual void dump(std::ostream&) const;
       virtual unsigned test_width(Design*des, NetScope*scope,
 				  width_mode_t&mode);
       virtual NetExpr*elaborate_expr(Design*des, NetScope*scope,
@@ -703,7 +701,7 @@ class PEUnary : public PExpr {
       explicit PEUnary(char op, PExpr*ex);
       ~PEUnary();
 
-      virtual void dump(ostream&out) const;
+      virtual void dump(std::ostream&out) const;
 
       virtual void declare_implicit_nets(LexicalScope*scope, NetNet::Type type);
 
@@ -735,7 +733,7 @@ class PEBinary : public PExpr {
       explicit PEBinary(char op, PExpr*l, PExpr*r);
       ~PEBinary();
 
-      virtual void dump(ostream&out) const;
+      virtual void dump(std::ostream&out) const;
 
       virtual void declare_implicit_nets(LexicalScope*scope, NetNet::Type type);
 
@@ -860,7 +858,7 @@ class PETernary : public PExpr {
       explicit PETernary(PExpr*e, PExpr*t, PExpr*f);
       ~PETernary();
 
-      virtual void dump(ostream&out) const;
+      virtual void dump(std::ostream&out) const;
 
       virtual void declare_implicit_nets(LexicalScope*scope, NetNet::Type type);
 
@@ -892,7 +890,7 @@ class PETernary : public PExpr {
  */
 class PECallFunction : public PExpr {
     public:
-      explicit PECallFunction(const pform_name_t&n, const vector<PExpr *> &parms);
+      explicit PECallFunction(const pform_name_t&n, const std::vector<PExpr *> &parms);
 	// Call function defined in package.
       explicit PECallFunction(PPackage*pkg, perm_string n, const std::vector<PExpr *> &parms);
       explicit PECallFunction(PPackage*pkg, perm_string n, const std::list<PExpr *> &parms);
@@ -901,24 +899,26 @@ class PECallFunction : public PExpr {
       explicit PECallFunction(PPackage*pkg, const pform_name_t&n, const std::vector<PExpr *> &parms);
 
 	// Call of system function (name is not hierarchical)
-      explicit PECallFunction(perm_string n, const vector<PExpr *> &parms);
+      explicit PECallFunction(perm_string n, const std::vector<PExpr *> &parms);
       explicit PECallFunction(perm_string n);
 
 	// std::list versions. Should be removed!
-      explicit PECallFunction(const pform_name_t&n, const list<PExpr *> &parms);
-      explicit PECallFunction(perm_string n, const list<PExpr *> &parms);
+      explicit PECallFunction(const pform_name_t&n, const std::list<PExpr *> &parms);
+      explicit PECallFunction(perm_string n, const std::list<PExpr *> &parms);
 
       ~PECallFunction();
 
-      virtual void dump(ostream &) const;
+      virtual void dump(std::ostream &) const;
 
       virtual void declare_implicit_nets(LexicalScope*scope, NetNet::Type type);
 
       virtual bool has_aa_term(Design*des, NetScope*scope) const;
 
       virtual NetExpr*elaborate_expr(Design*des, NetScope*scope,
-				     unsigned expr_wid,
-                                     unsigned flags) const;
+				     ivl_type_t type, unsigned flags) const;
+
+      virtual NetExpr*elaborate_expr(Design*des, NetScope*scope,
+				     unsigned expr_wid, unsigned flags) const;
 
       virtual unsigned test_width(Design*des, NetScope*scope,
 				  width_mode_t&mode);
@@ -928,6 +928,9 @@ class PECallFunction : public PExpr {
       pform_name_t path_;
       std::vector<PExpr *> parms_;
 
+        // For system functions.
+      bool is_overridden_;
+
       bool check_call_matches_definition_(Design*des, NetScope*dscope) const;
 
 
@@ -969,10 +972,10 @@ class PECallFunction : public PExpr {
 class PECastSize  : public PExpr {
 
     public:
-      explicit PECastSize(unsigned expr_wid, PExpr*base);
+      explicit PECastSize(PExpr*size, PExpr*base);
       ~PECastSize();
 
-      void dump(ostream &out) const;
+      void dump(std::ostream &out) const;
 
       virtual NetExpr*elaborate_expr(Design*des, NetScope*scope,
 				     unsigned expr_wid,
@@ -982,7 +985,7 @@ class PECastSize  : public PExpr {
 				  width_mode_t&mode);
 
     private:
-      unsigned size_;
+      PExpr* size_;
       PExpr* base_;
 };
 
@@ -995,7 +998,10 @@ class PECastType  : public PExpr {
       explicit PECastType(data_type_t*target, PExpr*base);
       ~PECastType();
 
-      void dump(ostream &out) const;
+      void dump(std::ostream &out) const;
+
+      virtual NetExpr*elaborate_expr(Design*des, NetScope*scope,
+				     ivl_type_t type, unsigned flags) const;
 
       virtual NetExpr*elaborate_expr(Design*des, NetScope*scope,
 				     unsigned expr_wid, unsigned flags) const;

PFunction.cc

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1999-2013 Stephen Williams ([email protected])
+ * Copyright (c) 1999-2019 Stephen Williams ([email protected])
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -23,6 +23,8 @@
 # include <cassert>
 # include "ivl_assert.h"
 
+using namespace std;
+
 PFunction::PFunction(perm_string name, LexicalScope*parent, bool is_auto__)
 : PTaskFunc(name, parent), statement_(0)
 {
@@ -83,3 +85,8 @@ PChainConstructor* PFunction::extract_chain_constructor()
 
       return res;
 }
+
+PNamedItem::SymbolType PFunction::symbol_type() const
+{
+      return FUNCTION;
+}

PGate.cc

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1999-2013 Stephen Williams ([email protected])
+ * Copyright (c) 1999-2021 Stephen Williams ([email protected])
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -24,6 +24,8 @@
 # include  "verinum.h"
 # include  <cassert>
 
+using namespace std;
+
 void PGate::set_pins_(list<PExpr*>*pins)
 {
       assert(pins);
@@ -39,7 +41,7 @@ void PGate::set_pins_(list<PExpr*>*pins)
 }
 
 PGate::PGate(perm_string name, list<PExpr*>*pins, const list<PExpr*>*del)
-: name_(name), pins_(pins? pins->size() : 0)
+: name_(name), pins_(pins? pins->size() : 0), ranges_(0)
 {
       if (pins) set_pins_(pins);
       if (del) delay_.set_delays(del);
@@ -48,7 +50,7 @@ PGate::PGate(perm_string name, list<PExpr*>*pins, const list<PExpr*>*del)
 }
 
 PGate::PGate(perm_string name, list<PExpr*>*pins, PExpr*del)
-: name_(name), pins_(pins? pins->size() : 0)
+: name_(name), pins_(pins? pins->size() : 0), ranges_(0)
 {
       if (pins) set_pins_(pins);
       if (del) delay_.set_delay(del);
@@ -57,7 +59,7 @@ PGate::PGate(perm_string name, list<PExpr*>*pins, PExpr*del)
 }
 
 PGate::PGate(perm_string name, list<PExpr*>*pins)
-: name_(name), pins_(pins? pins->size() : 0)
+: name_(name), pins_(pins? pins->size() : 0), ranges_(0)
 {
       if (pins) set_pins_(pins);
       str0_ = IVL_DR_STRONG;
@@ -68,6 +70,12 @@ PGate::~PGate()
 {
 }
 
+void PGate::set_ranges(list<pform_range_t>*ranges)
+{
+      assert(ranges_ == 0);
+      ranges_ = ranges;
+}
+
 ivl_drive_t PGate::strength0() const
 {
       return str0_;
@@ -117,6 +125,11 @@ unsigned PGate::delay_count() const
       return delay_.delay_count();
 }
 
+PNamedItem::SymbolType PGate::symbol_type() const
+{
+      return INSTANCE;
+}
+
 PGAssign::PGAssign(list<PExpr*>*pins)
 : PGate(perm_string(), pins)
 {
@@ -136,14 +149,14 @@ PGAssign::~PGAssign()
 PGBuiltin::PGBuiltin(Type t, perm_string name,
 		     list<PExpr*>*pins,
 		     list<PExpr*>*del)
-: PGate(name, pins, del), type_(t), msb_(0), lsb_(0)
+: PGate(name, pins, del), type_(t)
 {
 }
 
 PGBuiltin::PGBuiltin(Type t, perm_string name,
 		     list<PExpr*>*pins,
 		     PExpr*del)
-: PGate(name, pins, del), type_(t), msb_(0), lsb_(0)
+: PGate(name, pins, del), type_(t)
 {
 }
 
@@ -152,15 +165,6 @@ PGBuiltin::~PGBuiltin()
 {
 }
 
-void PGBuiltin::set_range(PExpr*msb, PExpr*lsb)
-{
-      assert(msb_ == 0);
-      assert(lsb_ == 0);
-
-      msb_ = msb;
-      lsb_ = lsb;
-}
-
 const char* PGBuiltin::gate_name() const
 {
       switch(type_) {
@@ -261,20 +265,20 @@ const char* PGBuiltin::gate_name() const
 
 PGModule::PGModule(perm_string type, perm_string name, list<PExpr*>*pins)
 : PGate(name, pins), bound_type_(0), type_(type), overrides_(0), pins_(0),
-  npins_(0), parms_(0), nparms_(0), msb_(0), lsb_(0)
+  npins_(0), parms_(0), nparms_(0)
 {
 }
 
 PGModule::PGModule(perm_string type, perm_string name,
 		   named<PExpr*>*pins, unsigned npins)
 : PGate(name, 0), bound_type_(0), type_(type), overrides_(0), pins_(pins),
-  npins_(npins), parms_(0), nparms_(0), msb_(0), lsb_(0)
+  npins_(npins), parms_(0), nparms_(0)
 {
 }
 
 PGModule::PGModule(Module*type, perm_string name)
 : PGate(name, 0), bound_type_(type), overrides_(0), pins_(0),
-  npins_(0), parms_(0), nparms_(0), msb_(0), lsb_(0)
+  npins_(0), parms_(0), nparms_(0)
 {
 }
 
@@ -296,15 +300,6 @@ void PGModule::set_parameters(named<PExpr*>*pa, unsigned npa)
       nparms_ = npa;
 }
 
-void PGModule::set_range(PExpr*msb, PExpr*lsb)
-{
-      assert(msb_ == 0);
-      assert(lsb_ == 0);
-
-      msb_ = msb;
-      lsb_ = lsb;
-}
-
 perm_string PGModule::get_type() const
 {
       return type_;

PGate.h

@@ -1,7 +1,7 @@
 #ifndef IVL_PGate_H
 #define IVL_PGate_H
 /*
- * Copyright (c) 1998-2014 Stephen Williams ([email protected])
+ * Copyright (c) 1998-2021 Stephen Williams ([email protected])
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -22,7 +22,7 @@
 # include  "svector.h"
 # include  "StringHeap.h"
 # include  "named.h"
-# include  "LineInfo.h"
+# include  "PNamedItem.h"
 # include  "PDelays.h"
 # include  "netlist.h"
 # include  <map>
@@ -47,19 +47,22 @@ class Module;
  * single strength pair. There is a strength of the 0 drive, and a
  * strength of the 1 drive.
  */
-class PGate : public LineInfo {
+class PGate : public PNamedItem {
 
     public:
-      explicit PGate(perm_string name, list<PExpr*>*pins,
-		     const list<PExpr*>*del);
+      explicit PGate(perm_string name, std::list<PExpr*>*pins,
+		     const std::list<PExpr*>*del);
 
-      explicit PGate(perm_string name, list<PExpr*>*pins,
+      explicit PGate(perm_string name, std::list<PExpr*>*pins,
 		     PExpr*del);
 
-      explicit PGate(perm_string name, list<PExpr*>*pins);
+      explicit PGate(perm_string name, std::list<PExpr*>*pins);
 
       virtual ~PGate();
 
+      void set_ranges(std::list<pform_range_t>*ranges);
+      bool is_array() const { return ranges_ != 0; }
+
       perm_string get_name() const { return name_; }
 
 	// This evaluates the delays as far as possible, but returns
@@ -81,27 +84,35 @@ class PGate : public LineInfo {
       void strength0(ivl_drive_t);
       void strength1(ivl_drive_t);
 
-      map<perm_string,PExpr*> attributes;
+      std::map<perm_string,PExpr*> attributes;
 
-      virtual void dump(ostream&out, unsigned ind =4) const;
+      virtual void dump(std::ostream&out, unsigned ind =4) const;
       virtual void elaborate(Design*des, NetScope*scope) const;
       virtual void elaborate_scope(Design*des, NetScope*sc) const;
       virtual bool elaborate_sig(Design*des, NetScope*scope) const;
 
-    protected:
-      const vector<PExpr*>& get_pins() const { return pins_; }
+      SymbolType symbol_type() const;
 
-      void dump_pins(ostream&out) const;
-      void dump_delays(ostream&out) const;
+    protected:
+      const std::vector<PExpr*>& get_pins() const { return pins_; }
+
+      unsigned calculate_array_size_(Design*, NetScope*,
+				     long&high, long&low) const;
+
+      void dump_pins(std::ostream&out) const;
+      void dump_delays(std::ostream&out) const;
+      void dump_ranges(std::ostream&out) const;
 
     private:
       perm_string name_;
       PDelays delay_;
-      vector<PExpr*>pins_;
+      std::vector<PExpr*>pins_;
+
+      std::list<pform_range_t>*ranges_;
 
       ivl_drive_t str0_, str1_;
 
-      void set_pins_(list<PExpr*>*pins);
+      void set_pins_(std::list<PExpr*>*pins);
 
     private: // not implemented
       PGate(const PGate&);
@@ -115,11 +126,11 @@ class PGate : public LineInfo {
 class PGAssign  : public PGate {
 
     public:
-      explicit PGAssign(list<PExpr*>*pins);
-      explicit PGAssign(list<PExpr*>*pins, list<PExpr*>*dels);
+      explicit PGAssign(std::list<PExpr*>*pins);
+      explicit PGAssign(std::list<PExpr*>*pins, std::list<PExpr*>*dels);
       ~PGAssign();
 
-      void dump(ostream&out, unsigned ind =4) const;
+      void dump(std::ostream&out, unsigned ind =4) const;
       virtual void elaborate(Design*des, NetScope*scope) const;
       virtual bool elaborate_sig(Design*des, NetScope*scope) const;
 
@@ -148,25 +159,21 @@ class PGBuiltin  : public PGate {
 
     public:
       explicit PGBuiltin(Type t, perm_string name,
-			 list<PExpr*>*pins,
-			 list<PExpr*>*del);
+			 std::list<PExpr*>*pins,
+			 std::list<PExpr*>*del);
       explicit PGBuiltin(Type t, perm_string name,
-			 list<PExpr*>*pins,
+			 std::list<PExpr*>*pins,
 			 PExpr*del);
       ~PGBuiltin();
 
       Type type() const { return type_; }
       const char * gate_name() const;
-      void set_range(PExpr*msb, PExpr*lsb);
 
-      virtual void dump(ostream&out, unsigned ind =4) const;
+      virtual void dump(std::ostream&out, unsigned ind =4) const;
       virtual void elaborate(Design*, NetScope*scope) const;
       virtual bool elaborate_sig(Design*des, NetScope*scope) const;
 
     private:
-      unsigned calculate_array_count_(Design*, NetScope*,
-				      long&high, long&low) const;
-
       void calculate_gate_and_lval_count_(unsigned&gate_count,
                                           unsigned&lval_count) const;
 
@@ -177,8 +184,6 @@ class PGBuiltin  : public PGate {
       bool check_delay_count(Design*des) const;
 
       Type type_;
-      PExpr*msb_;
-      PExpr*lsb_;
 };
 
 /*
@@ -195,7 +200,7 @@ class PGModule  : public PGate {
 	// If the binding of ports is by position, this constructor
 	// builds everything all at once.
       explicit PGModule(perm_string type, perm_string name,
-			list<PExpr*>*pins);
+			std::list<PExpr*>*pins);
 
 	// If the binding of ports is by name, this constructor takes
 	// the bindings and stores them for later elaboration.
@@ -210,14 +215,12 @@ class PGModule  : public PGate {
 
 	// Parameter overrides can come as an ordered list, or a set
 	// of named expressions.
-      void set_parameters(list<PExpr*>*o);
+      void set_parameters(std::list<PExpr*>*o);
       void set_parameters(named<PExpr*>*pa, unsigned npa);
 
-	// Modules can be instantiated in ranges. The parser uses this
-	// method to pass the range to the pform.
-      void set_range(PExpr*msb, PExpr*lsb);
+      std::map<perm_string,PExpr*> attributes;
 
-      virtual void dump(ostream&out, unsigned ind =4) const;
+      virtual void dump(std::ostream&out, unsigned ind =4) const;
       virtual void elaborate(Design*, NetScope*scope) const;
       virtual void elaborate_scope(Design*des, NetScope*sc) const;
       virtual bool elaborate_sig(Design*des, NetScope*scope) const;
@@ -229,7 +232,7 @@ class PGModule  : public PGate {
     private:
       Module*bound_type_;
       perm_string type_;
-      list<PExpr*>*overrides_;
+      std::list<PExpr*>*overrides_;
       named<PExpr*>*pins_;
       unsigned npins_;
 
@@ -237,16 +240,9 @@ class PGModule  : public PGate {
       named<PExpr*>*parms_;
       unsigned nparms_;
 
-	// Arrays of modules are give if these are set.
-      PExpr*msb_;
-      PExpr*lsb_;
-
       friend class delayed_elaborate_scope_mod_instances;
       void elaborate_mod_(Design*, Module*mod, NetScope*scope) const;
       void elaborate_udp_(Design*, PUdp  *udp, NetScope*scope) const;
-      unsigned calculate_instance_count_(Design*, NetScope*,
-                                         long&high, long&low,
-                                         perm_string name) const;
       void elaborate_scope_mod_(Design*des, Module*mod, NetScope*sc) const;
       void elaborate_scope_mod_instances_(Design*des, Module*mod, NetScope*sc) const;
       bool elaborate_sig_mod_(Design*des, NetScope*scope, Module*mod) const;

PGenerate.cc

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2011 Stephen Williams ([email protected])
+ * Copyright (c) 2006-2020 Stephen Williams ([email protected])
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -21,11 +21,14 @@
 # include  "PWire.h"
 # include  "ivl_assert.h"
 
+using namespace std;
+
 PGenerate::PGenerate(LexicalScope*parent, unsigned id)
 : LexicalScope(parent), id_number(id)
 {
-      direct_nested_ = false;
       scheme_type = GS_NONE;
+      directly_nested = false;
+      local_index = false;
       loop_init = 0;
       loop_test = 0;
       loop_step = 0;
@@ -40,51 +43,6 @@ void PGenerate::add_gate(PGate*gate)
       gates.push_back(gate);
 }
 
-void PGenerate::probe_for_direct_nesting_(void)
-{
-      direct_nested_ = false;
-
-      ivl_assert(*this, scheme_type==GS_CASE_ITEM || scheme_type==GS_CONDIT || scheme_type==GS_ELSE);
-
-	// If this scheme has received an explicit name, then it
-	// cannot be direct nested.
-      if (scope_name[0] != '$') return;
-
-      if (! tasks.empty()) return;
-      if (! funcs.empty()) return;
-      if (! gates.empty()) return;
-      if (! parameters.empty()) return;
-      if (! localparams.empty()) return;
-      if (! events.empty()) return;
-      if (! wires.empty()) return;
-      if (! genvars.empty()) return;
-      if (! behaviors.empty()) return;
-      if (! analog_behaviors.empty()) return;
-
-      if (generate_schemes.empty()) return;
-
-      switch (generate_schemes.size()) {
-	  case 1: {
-		PGenerate*child = generate_schemes.front();
-		if (child->scheme_type == GS_CONDIT)
-		      direct_nested_ = true;
-		if (child->scheme_type == GS_CASE)
-		      direct_nested_ = true;
-		break;
-	  }
-
-	  case 2: {
-		PGenerate*child1 = generate_schemes.front();
-		PGenerate*child2 = generate_schemes.back();
-		if (child1->scheme_type==GS_CONDIT && child2->scheme_type==GS_ELSE)
-		      direct_nested_ = true;
-		if (child2->scheme_type==GS_CONDIT && child1->scheme_type==GS_ELSE)
-		      direct_nested_ = true;
-		break;
-	  }
-      }
-}
-
 ostream& operator << (ostream&out, PGenerate::scheme_t type)
 {
       switch (type) {
@@ -112,3 +70,8 @@ ostream& operator << (ostream&out, PGenerate::scheme_t type)
       }
       return out;
 }
+
+PNamedItem::SymbolType PGenerate::symbol_type() const
+{
+      return GENBLOCK;
+}

PGenerate.h

@@ -1,7 +1,7 @@
 #ifndef IVL_PGenerate_H
 #define IVL_PGenerate_H
 /*
- * Copyright (c) 2006-2014 Stephen Williams ([email protected])
+ * Copyright (c) 2006-2021 Stephen Williams ([email protected])
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -19,7 +19,7 @@
  *    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
  */
 
-# include  "LineInfo.h"
+# include  "PNamedItem.h"
 # include  "StringHeap.h"
 # include  "HName.h"
 # include  "PScope.h"
@@ -50,7 +50,7 @@ class PWire;
  *    The parent points to the GS_CASE that contains this item.
  *    the loop_test is compared with the parent->loop_test expression.
  */
-class PGenerate : public LineInfo, public LexicalScope {
+class PGenerate : public PNamedItem, public LexicalScope {
 
     public:
       explicit PGenerate(LexicalScope*parent, unsigned id_number);
@@ -69,8 +69,13 @@ class PGenerate : public LineInfo, public LexicalScope {
 		     GS_CASE, GS_CASE_ITEM, GS_NBLOCK};
       scheme_t scheme_type;
 
+      bool directly_nested;
+
 	// generate loops have an index variable and three
 	// expressions: for (index = <init>; <test>; index=<step>)
+	// the index is local if it was declared in the init expression,
+	// e.g. for (genvar index = <init>; <test>; index=<step>)
+      bool local_index;
       perm_string loop_index;
       PExpr*loop_init;
       PExpr*loop_test;
@@ -81,18 +86,18 @@ class PGenerate : public LineInfo, public LexicalScope {
       std::valarray<PExpr*> item_test;
 
 	// defparam assignments found in this scope.
-      typedef pair<pform_name_t,PExpr*> named_expr_t;
-      list<named_expr_t>defparms;
+      typedef std::pair<pform_name_t,PExpr*> named_expr_t;
+      std::list<named_expr_t>defparms;
 
-      list<PGate*> gates;
+      std::list<PGate*> gates;
       void add_gate(PGate*);
 
 	// Tasks instantiated within this scheme.
-      map<perm_string,PTask*> tasks;
-      map<perm_string,PFunction*>funcs;
+      std::map<perm_string,PTask*> tasks;
+      std::map<perm_string,PFunction*>funcs;
 
 	// Generate schemes can contain further generate schemes.
-      list<PGenerate*> generate_schemes;
+      std::list<PGenerate*> generate_schemes;
 //      PGenerate*parent;
 
 	// This method is called by the elaboration of a module to
@@ -105,27 +110,23 @@ class PGenerate : public LineInfo, public LexicalScope {
       bool elaborate_sig(Design*des, NetScope*container) const;
       bool elaborate(Design*des, NetScope*container) const;
 
-      void dump(ostream&out, unsigned indent) const;
+      void dump(std::ostream&out, unsigned indent) const;
+
+      SymbolType symbol_type() const;
 
     private:
+      void check_for_valid_genvar_value_(long value);
       bool generate_scope_loop_(Design*des, NetScope*container);
       bool generate_scope_condit_(Design*des, NetScope*container, bool else_flag);
       bool generate_scope_case_(Design*des, NetScope*container);
       bool generate_scope_nblock_(Design*des, NetScope*container);
 
-	// Call probe during elaborate_scope to calculate the
-	// direct_nested_ flag. It is OK to store the direct_nested_
-	// information here because "direct nested" is a property of
-	// the lexical generate code.
-      void probe_for_direct_nesting_(void);
-      bool direct_nested_;
-
 	// Elaborate_scope within a generated scope.
       void elaborate_subscope_(Design*des, NetScope*scope);
       void elaborate_subscope_direct_(Design*des, NetScope*scope);
 
 	// These are the scopes created by generate_scope.
-      list<NetScope*>scope_list_;
+      std::list<NetScope*>scope_list_;
 	// internal function called on each scope generated by this scheme.
       bool elaborate_sig_(Design*des, NetScope*scope) const;
       bool elaborate_sig_direct_(Design*des, NetScope*scope) const;

PModport.cc

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2003 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 2015-2019 Stephen Williams (steve@icarus.com)
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -17,10 +17,20 @@
  *    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
  */
 
-/*
- * Things that should be statically linked by VPI modules go here.
- */
+# include "config.h"
 
-void __libvpi_c_dummy_function(void)
+# include  "PModport.h"
+
+PModport::PModport(perm_string n)
+: name_(n)
 {
 }
+
+PModport::~PModport()
+{
+}
+
+PNamedItem::SymbolType PModport::symbol_type() const
+{
+      return MODPORT;
+}

PModport.h

@@ -0,0 +1,54 @@
+#ifndef IVL_PModport_H
+#define IVL_PModport_H
+/*
+ * Copyright (c) 2015-2021 Stephen Williams ([email protected])
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+
+# include  "PNamedItem.h"
+# include  "PScope.h"
+# include  "StringHeap.h"
+# include  "netlist.h"
+# include  <vector>
+
+/*
+ * The PModport class represents a parsed SystemVerilog modport list.
+ */
+class PModport : public PNamedItem {
+
+    public:
+	// The name is a perm-allocated string. It is the simple name
+	// of the modport, without any scope.
+      explicit PModport(perm_string name);
+      ~PModport();
+
+      perm_string name() const { return name_; }
+
+      typedef std::pair <NetNet::PortType,PExpr*> simple_port_t;
+      std::map<perm_string,simple_port_t> simple_ports;
+
+      SymbolType symbol_type() const;
+
+    private:
+      perm_string name_;
+
+    private: // not implemented
+      PModport(const PModport&);
+      PModport& operator= (const PModport&);
+};
+
+#endif /* IVL_PModport_H */

PNamedItem.cc

@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2019 Martin Whitaker ([email protected])
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+
+# include  "PNamedItem.h"
+# include  <ostream>
+
+PNamedItem::PNamedItem()
+{
+}
+
+PNamedItem::~PNamedItem()
+{
+}
+
+PNamedItem::SymbolType PNamedItem::symbol_type() const
+{
+      return ANY;
+}
+
+std::ostream& operator << (std::ostream&o, PNamedItem::SymbolType st)
+{
+      switch (st) {
+          case PNamedItem::ANY:
+            o << "a symbol";
+            break;
+          case PNamedItem::PARAM:
+            o << "a parameter";
+            break;
+          case PNamedItem::NET:
+            o << "a net";
+            break;
+          case PNamedItem::VAR:
+            o << "a variable";
+            break;
+          case PNamedItem::GENVAR:
+            o << "a genvar";
+            break;
+          case PNamedItem::EVENT:
+            o << "an event";
+            break;
+          case PNamedItem::TYPE:
+            o << "a type";
+            break;
+          case PNamedItem::ENUM:
+            o << "an enum type or value";
+            break;
+          case PNamedItem::CLASS:
+            o << "a class";
+            break;
+          case PNamedItem::FUNCTION:
+            o << "a function";
+            break;
+          case PNamedItem::TASK:
+            o << "a task";
+            break;
+          case PNamedItem::BLOCK:
+            o << "a named block";
+            break;
+          case PNamedItem::GENBLOCK:
+            o << "a generate block";
+            break;
+          case PNamedItem::MODPORT:
+            o << "a modport";
+            break;
+          case PNamedItem::PACKAGE:
+            o << "a package";
+            break;
+          case PNamedItem::MODULE:
+            o << "a module";
+            break;
+          case PNamedItem::PROGRAM:
+            o << "a program";
+            break;
+          case PNamedItem::INTERFACE:
+            o << "an interface";
+            break;
+          case PNamedItem::PRIMITIVE:
+            o << "a primitive";
+            break;
+          case PNamedItem::INSTANCE:
+            o << "an instance name";
+            break;
+          default:
+            break;
+      }
+      return o;
+}
+
+PGenvar::PGenvar()
+{
+}
+
+PGenvar::~PGenvar()
+{
+}
+
+PNamedItem::SymbolType PGenvar::symbol_type() const
+{
+      return GENVAR;
+}

PNamedItem.h

@@ -0,0 +1,57 @@
+#ifndef IVL_PNamedItem_H
+#define IVL_PNamedItem_H
+/*
+ * Copyright (c) 2019 Martin Whitaker ([email protected])
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+
+# include  "LineInfo.h"
+
+/*
+ * The PNamedItem class is the base class for all items that can be added
+ * to a scope's local symbol map.
+ */
+class PNamedItem : virtual public LineInfo {
+
+    public:
+      enum SymbolType { ANY, PARAM, NET, VAR, GENVAR, EVENT, TYPE, ENUM,
+                        CLASS, FUNCTION, TASK, BLOCK, GENBLOCK, MODPORT,
+                        PACKAGE, MODULE, PROGRAM, INTERFACE, PRIMITIVE,
+                        INSTANCE };
+
+      explicit PNamedItem();
+      virtual ~PNamedItem();
+
+      virtual SymbolType symbol_type() const;
+};
+
+extern std::ostream& operator << (std::ostream&, PNamedItem::SymbolType);
+
+/*
+ * The PGenvar class represents a genvar. This is only used to represent
+ * genvar in a scope's local symbol map.
+ */
+class PGenvar : public PNamedItem {
+
+    public:
+      explicit PGenvar();
+      virtual ~PGenvar();
+
+      SymbolType symbol_type() const;
+};
+
+#endif /* IVL_PNamedItem_H */

PScope.cc

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008,2010 Stephen Williams ([email protected])
+ * Copyright (c) 2008-2021 Stephen Williams ([email protected])
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -19,21 +19,11 @@
 
 # include  "PScope.h"
 
-PScope::PScope(perm_string n, LexicalScope*parent)
-: LexicalScope(parent), name_(n)
-{
-}
+using namespace std;
 
-PScope::PScope(perm_string n)
-: LexicalScope(0), name_(n)
+bool LexicalScope::var_init_needs_explicit_lifetime() const
 {
-}
-
-PScope::~PScope()
-{
-    for(map<perm_string, data_type_t*>::iterator it = typedefs.begin();
-        it != typedefs.end(); ++it)
-        delete it->second;
+      return false;
 }
 
 PWire* LexicalScope::wires_find(perm_string name)
@@ -45,17 +35,34 @@ PWire* LexicalScope::wires_find(perm_string name)
 	    return (*cur).second;
 }
 
+PNamedItem::SymbolType LexicalScope::param_expr_t::symbol_type() const
+{
+      return PARAM;
+}
+
+PScope::PScope(perm_string n, LexicalScope*parent)
+: LexicalScope(parent), name_(n)
+{
+      time_unit = 0;
+      time_precision = 0;
+      time_unit_is_default = true;
+      time_prec_is_default = true;
+}
+
+PScope::~PScope()
+{
+    for(map<perm_string, data_type_t*>::iterator it = typedefs.begin();
+        it != typedefs.end(); ++it)
+        delete it->second;
+}
+
 PScopeExtra::PScopeExtra(perm_string n, LexicalScope*parent)
 : PScope(n, parent)
 {
-}
-
-PScopeExtra::PScopeExtra(perm_string n)
-: PScope(n)
-{
+      time_unit_is_local = false;
+      time_prec_is_local = false;
 }
 
 PScopeExtra::~PScopeExtra()
 {
 }
-

PScope.h

@@ -1,7 +1,7 @@
 #ifndef IVL_PScope_H
 #define IVL_PScope_H
 /*
- * Copyright (c) 2008-2014 Stephen Williams ([email protected])
+ * Copyright (c) 2008-2019 Stephen Williams ([email protected])
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -19,7 +19,7 @@
  *    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
  */
 
-# include  "LineInfo.h"
+# include  "PNamedItem.h"
 # include  "StringHeap.h"
 # include  "pform_types.h"
 # include  "ivl_target.h"
@@ -36,6 +36,7 @@ class PProcess;
 class PClass;
 class PTask;
 class PWire;
+class Statement;
 
 class Design;
 class NetScope;
@@ -52,10 +53,33 @@ class NetScope;
 class LexicalScope {
 
     public:
-      explicit LexicalScope(LexicalScope*parent) : parent_(parent) { }
+      enum lifetime_t { INHERITED, STATIC, AUTOMATIC };
+
+      explicit LexicalScope(LexicalScope*parent)
+        : default_lifetime(INHERITED), generate_counter(0), parent_(parent) { }
 	// A virtual destructor is so that dynamic_cast can work.
       virtual ~LexicalScope() { }
 
+      lifetime_t default_lifetime;
+
+	// Symbols that are defined or declared in this scope.
+      std::map<perm_string,PNamedItem*>local_symbols;
+
+	// Symbols that are explicitly imported. Bind the imported name
+	// to the package from which the name is imported.
+      std::map<perm_string,PPackage*>explicit_imports;
+
+	// Packages that are wildcard imported. When identifiers from
+	// these packages are referenced, they will be added to the
+	// explicit imports (IEEE 1800-2012 26.3).
+      std::list<PPackage*>potential_imports;
+
+	// A task or function call may reference a task or function defined
+	// later in the scope. So here we stash the potential imports for
+	// task and function calls. They will be added to the explicit
+	// imports if we don't find a local definition.
+      std::map<perm_string,PPackage*>possible_imports;
+
       struct range_t {
 	      // True if this is an exclude
 	    bool exclude_flag;
@@ -74,7 +98,7 @@ class LexicalScope {
 	/* The scope has parameters that are evaluated when the scope
 	   is elaborated. During parsing, I put the parameters into
 	   this map. */
-      struct param_expr_t : public LineInfo {
+      struct param_expr_t : public PNamedItem {
 	    param_expr_t() : type(IVL_VT_NO_TYPE), msb(0), lsb(0), signed_flag(false), expr(0), range(0) { }
 	      // Type information
 	    ivl_variable_type_t type;
@@ -85,50 +109,62 @@ class LexicalScope {
 	    PExpr*expr;
 	      // If there are range constraints, list them here
 	    range_t*range;
+
+	    SymbolType symbol_type() const;
       };
-      map<perm_string,param_expr_t>parameters;
-      map<perm_string,param_expr_t>localparams;
+      std::map<perm_string,param_expr_t*>parameters;
+      std::map<perm_string,param_expr_t*>localparams;
 
 	// Defined types in the scope.
-      map<perm_string,data_type_t*>typedefs;
+      std::map<perm_string,data_type_t*>typedefs;
 
 	// Named events in the scope.
-      map<perm_string,PEvent*>events;
-
-	// Symbols that are imported. Bind the imported name to the
-	// package from which the name is imported.
-      std::map<perm_string,PPackage*>imports;
+      std::map<perm_string,PEvent*>events;
 
 	// Nets and variables (wires) in the scope
-      map<perm_string,PWire*>wires;
+      std::map<perm_string,PWire*>wires;
       PWire* wires_find(perm_string name);
 
         // Genvars in the scope. These will only be present in module
         // scopes, but are listed here to allow them to be found when
         // creating implicit nets.
-      map<perm_string,LineInfo*> genvars;
+      std::map<perm_string,LineInfo*> genvars;
+
+	// Variable initializations in this scope
+      std::vector<Statement*> var_inits;
 
 	// Behaviors (processes) in this scope
-      list<PProcess*> behaviors;
-      list<AProcess*> analog_behaviors;
+      std::list<PProcess*> behaviors;
+      std::list<AProcess*> analog_behaviors;
 
 	// Enumeration sets.
       std::set<enum_type_t*> enum_sets;
 
+        // A count of the generate constructs in this scope. This is
+        // used to automatically name unnamed generate blocks, as
+        // specified in the LRM.
+      unsigned generate_counter;
+
       LexicalScope* parent_scope() const { return parent_; }
 
+      virtual bool var_init_needs_explicit_lifetime() const;
+
     protected:
-      void dump_typedefs_(ostream&out, unsigned indent) const;
+      void dump_typedefs_(std::ostream&out, unsigned indent) const;
 
-      void dump_parameters_(ostream&out, unsigned indent) const;
+      void dump_parameters_(std::ostream&out, unsigned indent) const;
 
-      void dump_localparams_(ostream&out, unsigned indent) const;
+      void dump_localparams_(std::ostream&out, unsigned indent) const;
 
-      void dump_enumerations_(ostream&out, unsigned indent) const;
+      void dump_enumerations_(std::ostream&out, unsigned indent) const;
 
-      void dump_events_(ostream&out, unsigned indent) const;
+      void dump_events_(std::ostream&out, unsigned indent) const;
 
-      void dump_wires_(ostream&out, unsigned indent) const;
+      void dump_wires_(std::ostream&out, unsigned indent) const;
+
+      void dump_var_inits_(std::ostream&out, unsigned indent) const;
+
+      bool elaborate_var_inits_(Design*des, NetScope*scope) const;
 
     private:
       LexicalScope*parent_;
@@ -145,12 +181,24 @@ class PScope : public LexicalScope {
 	// modules do not nest in Verilog, the parent must be nil for
 	// modules. Scopes for tasks and functions point to their
 	// containing module.
-      PScope(perm_string name, LexicalScope*parent);
-      PScope(perm_string name);
+      explicit PScope(perm_string name, LexicalScope*parent =0);
       virtual ~PScope();
 
       perm_string pscope_name() const { return name_; }
 
+	/* These are the timescale for this scope. The value is
+	   set by the `timescale directive or, in SystemVerilog,
+	   by timeunit and timeprecision statements. */
+      int time_unit, time_precision;
+
+	/* Flags used to support warnings about timescales. */
+      bool time_unit_is_default;
+      bool time_prec_is_default;
+
+      bool has_explicit_timescale() const {
+	     return !(time_unit_is_default || time_prec_is_default);
+	   }
+
     protected:
       bool elaborate_sig_wires_(Design*des, NetScope*scope) const;
 
@@ -168,23 +216,26 @@ class PScope : public LexicalScope {
 class PScopeExtra : public PScope {
 
     public:
-      PScopeExtra(perm_string, LexicalScope*parent);
-      PScopeExtra(perm_string);
+      explicit PScopeExtra(perm_string, LexicalScope*parent =0);
       ~PScopeExtra();
 
 	/* Task definitions within this module */
       std::map<perm_string,PTask*> tasks;
       std::map<perm_string,PFunction*> funcs;
-	/* class definitions within this module. */
+	/* Class definitions within this module. */
       std::map<perm_string,PClass*> classes;
 	/* This is the lexical order of the classes, and is used by
 	   elaboration to choose an elaboration order. */
       std::vector<PClass*> classes_lexical;
 
+	/* Flags used to support warnings about timescales. */
+      bool time_unit_is_local;
+      bool time_prec_is_local;
+
     protected:
-      void dump_classes_(ostream&out, unsigned indent) const;
-      void dump_tasks_(ostream&out, unsigned indent) const;
-      void dump_funcs_(ostream&out, unsigned indent) const;
+      void dump_classes_(std::ostream&out, unsigned indent) const;
+      void dump_tasks_(std::ostream&out, unsigned indent) const;
+      void dump_funcs_(std::ostream&out, unsigned indent) const;
 };
 
 #endif /* IVL_PScope_H */

PTask.cc

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1999-2008,2010 Stephen Williams ([email protected])
+ * Copyright (c) 1999-2021 Stephen Williams ([email protected])
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -21,6 +21,8 @@
 # include  "PTask.h"
 # include  <cassert>
 
+using namespace std;
+
 PTaskFunc::PTaskFunc(perm_string n, LexicalScope*p)
 : PScope(n,p), this_type_(0), ports_(0)
 {
@@ -30,6 +32,11 @@ PTaskFunc::~PTaskFunc()
 {
 }
 
+bool PTaskFunc::var_init_needs_explicit_lifetime() const
+{
+      return default_lifetime == STATIC;
+}
+
 void PTaskFunc::set_ports(vector<pform_tf_port_t>*p)
 {
       assert(ports_ == 0);
@@ -41,7 +48,7 @@ void PTaskFunc::set_this(class_type_t*type, PWire*this_wire)
       assert(this_type_ == 0);
       this_type_ = type;
 
-	// Push a synthethis argument that is the "this" value.
+	// Push a synthesis argument that is the "this" value.
       if (ports_==0)
 	    ports_ = new vector<pform_tf_port_t>;
 
@@ -68,3 +75,8 @@ void PTask::set_statement(Statement*s)
       assert(statement_ == 0);
       statement_ = s;
 }
+
+PNamedItem::SymbolType PTask::symbol_type() const
+{
+      return TASK;
+}

PTask.h

@@ -1,7 +1,7 @@
 #ifndef IVL_PTask_H
 #define IVL_PTask_H
 /*
- * Copyright (c) 1999-2014 Stephen Williams ([email protected])
+ * Copyright (c) 1999-2019 Stephen Williams ([email protected])
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -19,8 +19,8 @@
  *    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
  */
 
-# include  "LineInfo.h"
 # include  "PScope.h"
+# include  "PNamedItem.h"
 # include  "StringHeap.h"
 # include  <string>
 # include  <vector>
@@ -35,12 +35,14 @@ class Statement;
 class PExpr;
 
 
-class PTaskFunc : public PScope, public LineInfo {
+class PTaskFunc : public PScope, public PNamedItem {
 
     public:
       PTaskFunc(perm_string name, LexicalScope*parent);
       ~PTaskFunc();
 
+      bool var_init_needs_explicit_lifetime() const;
+
       void set_ports(std::vector<pform_tf_port_t>*p);
 
       void set_this(class_type_t*use_type, PWire*this_wire);
@@ -95,7 +97,9 @@ class PTask  : public PTaskFunc {
 
       bool is_auto() const { return is_auto_; };
 
-      void dump(ostream&, unsigned) const;
+      void dump(std::ostream&, unsigned) const;
+
+      SymbolType symbol_type() const;
 
     private:
       Statement*statement_;
@@ -144,7 +148,9 @@ class PFunction : public PTaskFunc {
 
       bool is_auto() const { return is_auto_; };
 
-      void dump(ostream&, unsigned) const;
+      void dump(std::ostream&, unsigned) const;
+
+      SymbolType symbol_type() const;
 
     private:
       data_type_t* return_type_;

PUdp.h

@@ -1,7 +1,7 @@
 #ifndef IVL_PUdp_H
 #define IVL_PUdp_H
 /*
- * Copyright (c) 1998-2014 Stephen Williams ([email protected])
+ * Copyright (c) 1998-2021 Stephen Williams ([email protected])
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -53,20 +53,20 @@ class PUdp : public LineInfo {
     public:
       explicit PUdp(perm_string n, unsigned nports);
 
-      svector<string>ports;
+      svector<std::string>ports;
       unsigned find_port(const char*name);
 
       bool sequential;
 
-      svector<string>tinput;
+      svector<std::string>tinput;
       svector<char>  tcurrent;
       svector<char>  toutput;
 
       verinum::V initial;
 
-      map<string,PExpr*> attributes;
+      std::map<std::string,PExpr*> attributes;
 
-      void dump(ostream&out) const;
+      void dump(std::ostream&out) const;
 
       perm_string name_;
     private:

PWire.cc

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1999-2012 Stephen Williams ([email protected])
+ * Copyright (c) 1999-2021 Stephen Williams ([email protected])
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -22,6 +22,8 @@
 # include  "PExpr.h"
 # include  <cassert>
 
+using namespace std;
+
 PWire::PWire(perm_string n,
 	     NetNet::Type t,
 	     NetNet::PortType pt,
@@ -29,7 +31,7 @@ PWire::PWire(perm_string n,
 : name_(n), type_(t), port_type_(pt), data_type_(dt),
   signed_(false), isint_(false),
   port_set_(false), net_set_(false), is_scalar_(false),
-  error_cnt_(0), set_data_type_(0),
+  error_cnt_(0), uarray_type_(0), set_data_type_(0),
   discipline_(0)
 {
       if (t == NetNet::INTEGER) {
@@ -67,6 +69,7 @@ bool PWire::set_wire_type(NetNet::Type t)
 		  isint_ = true;
 		  return true;
 	    }
+	    if (t == NetNet::IMPLICIT_REG) return true;
 	    return false;
 	  case NetNet::REG:
 	    if (t == NetNet::INTEGER) {
@@ -131,7 +134,13 @@ ivl_variable_type_t PWire::get_data_type() const
 
 void PWire::set_signed(bool flag)
 {
-      signed_ = flag;
+	// For a non-ANSI style port declaration where the data type is
+	// specified in a corresponding variable declaration, the signed
+	// attribute may be attached to either the port declaration or to
+	// the variable declaration (IEEE 1364-2005 section 12.3.3). The
+	// signal is signed if either the port or the variable is signed.
+	// Handle that here.
+      signed_ = signed_ || flag;
 }
 
 bool PWire::get_signed() const
@@ -263,7 +272,7 @@ void PWire::set_unpacked_idx(const list<pform_range_t>&ranges)
 
 void PWire::set_data_type(data_type_t*type)
 {
-      assert(set_data_type_ == 0);
+      assert(set_data_type_ == 0 || set_data_type_ == type);
       set_data_type_ = type;
 
       if (vector_type_t*tmp = dynamic_cast<vector_type_t*>(type)) {
@@ -282,3 +291,15 @@ ivl_discipline_t PWire::get_discipline(void) const
 {
       return discipline_;
 }
+
+PNamedItem::SymbolType PWire::symbol_type() const
+{
+      switch (type_) {
+          case NetNet::IMPLICIT_REG:
+          case NetNet::INTEGER:
+          case NetNet::REG:
+            return VAR;
+          default:
+            return NET;
+    }
+}

PWire.h

@@ -1,7 +1,7 @@
 #ifndef IVL_PWire_H
 #define IVL_PWire_H
 /*
- * Copyright (c) 1998-2014 Stephen Williams ([email protected])
+ * Copyright (c) 1998-2021 Stephen Williams ([email protected])
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -20,7 +20,7 @@
  */
 
 # include  "netlist.h"
-# include  "LineInfo.h"
+# include  "PNamedItem.h"
 # include  <list>
 # include  <map>
 # include  "StringHeap.h"
@@ -28,7 +28,7 @@
 #ifdef HAVE_IOSFWD
 # include  <iosfwd>
 #else
-class ostream;
+# include  <iostream>
 #endif
 
 class PExpr;
@@ -51,7 +51,7 @@ enum PWSRType {SR_PORT, SR_NET, SR_BOTH};
  * from that perspective, sub-scopes within the module are a part of
  * the wire name.
  */
-class PWire : public LineInfo {
+class PWire : public PNamedItem {
 
     public:
       PWire(perm_string name,
@@ -80,19 +80,22 @@ class PWire : public LineInfo {
       void set_range(const std::list<pform_range_t>&ranges, PWSRType type);
 
       void set_unpacked_idx(const std::list<pform_range_t>&ranges);
+      void set_uarray_type(uarray_type_t*type) { uarray_type_ = type; }
 
       void set_data_type(data_type_t*type);
 
       void set_discipline(ivl_discipline_t);
       ivl_discipline_t get_discipline(void) const;
 
-      map<perm_string,PExpr*> attributes;
+      std::map<perm_string,PExpr*> attributes;
 
 	// Write myself to the specified stream.
-      void dump(ostream&out, unsigned ind=4) const;
+      void dump(std::ostream&out, unsigned ind=4) const;
 
       NetNet* elaborate_sig(Design*, NetScope*scope) const;
 
+      SymbolType symbol_type() const;
+
     private:
       perm_string name_;
       NetNet::Type type_;
@@ -117,6 +120,7 @@ class PWire : public LineInfo {
 	// If this wire is actually a memory, these indices will give
 	// me the size and address ranges of the memory.
       std::list<pform_range_t>unpacked_;
+      uarray_type_t*uarray_type_;
 
 	// This is the complex type of the wire. the data_type_ may
 	// modify how this is interpreted.

README.txt

@@ -1,12 +1,12 @@
 		THE ICARUS VERILOG COMPILATION SYSTEM
-		Copyright 2000-2004 Stephen Williams
+		Copyright 2000-2019 Stephen Williams
 
 
 1.0 What is ICARUS Verilog?
 
 Icarus Verilog is intended to compile ALL of the Verilog HDL as
 described in the IEEE-1364 standard. Of course, it's not quite there
-yet. It does currently handle a mix of structural and behavioral
+yet. It does currently handle a mix of structural and behavioural
 constructs. For a view of the current state of Icarus Verilog, see its
 home page at <http://iverilog.icarus.com/>.
 
@@ -20,13 +20,13 @@ tools.
 
 2.0 Building/Installing Icarus Verilog From Source
 
-If you are starting from source, the build process is designed to be
+If you are starting from the source, the build process is designed to be
 as simple as practical. Someone basically familiar with the target
 system and C/C++ compilation should be able to build the source
 distribution with little effort. Some actual programming skills are
 not required, but helpful in case of problems.
 
-If you are building for Windows, see the mingw.txt file.
+If you are building on Windows, see the mingw.txt file.
 
 2.1 Compile Time Prerequisites
 
@@ -46,8 +46,12 @@ on a UNIX-like system:
 	  to work. MSVC++ 5 and 6 are known to definitely *not* work.
 
 	- bison and flex
+          OSX note: bison 2.3 shipped with MacOS including Catalina generates
+          broken code, but bison 3+ works. We recommend using the Fink
+          project version of bison and flex (finkproject.org), brew version
+          works fine either.
 
-	- gperf 2.7
+	- gperf 3.0 or later
 	  The lexical analyzer doesn't recognize keywords directly,
 	  but instead matches symbols and looks them up in a hash
 	  table in order to get the proper lexical code. The gperf
@@ -56,34 +60,40 @@ on a UNIX-like system:
 	  A version problem with this program is the most common cause
 	  of difficulty. See the Icarus Verilog FAQ.
 
-	- readline 4.2
+	- readline 4.2 or later
 	  On Linux systems, this usually means the readline-devel
 	  rpm. In any case, it is the development headers of readline
 	  that are needed.
 
 	- termcap
-	  The readline library in turn uses termcap.
+	  The readline library, in turn, uses termcap.
 
 If you are building from git, you will also need software to generate
 the configure scripts.
 
-	- autoconf 2.53
-	  This generates configure scripts from configure.in. The 2.53
+	- autoconf 2.53 or later
+	  This generates configure scripts from configure.ac. The 2.53
 	  or later versions are known to work, autoconf 2.13 is
 	  reported to *not* work.
 
 2.2 Compilation
 
 Unpack the tar-ball and cd into the verilog-######### directory
-(presumably that is how you got to this README) and compile the source
+(presumably, that is how you got to this README) and compile the source
 with the commands:
 
   ./configure
   make
 
+If you are building from git, you have to run the command below before
+compiling the source. This will generate the "configure" file, which is
+automatically done when building from tarball.
+
+  sh autoconf.sh
+
 Normally, this command automatically figures out everything it needs
 to know. It generally works pretty well. There are a few flags to the
-configure script that modify its behavior:
+configure script that modify its behaviour:
 
 	--prefix=<root>
 	    The default is /usr/local, which causes the tool suite to
@@ -106,6 +116,12 @@ configure script that modify its behavior:
 	    with the same prefix but different suffix are guaranteed
 	    to not interfere with each other.
 
+	--host=<host-type>
+	    Compile iverilog for a different platform. You can use:
+                x64_64-w64-mingw32 for building 64-bit Windows executables
+                i686-w64-mingw32 for building 32-bit Windows executables
+            Both options require installing the required mingw-w64 packages.
+
 2.3 (Optional) Testing
 
 To run a simple test before installation, execute
@@ -155,7 +171,7 @@ output of the parse is a list of Module objects in "pform". The pform
 step. There may be dangling references, and it is not yet clear which
 module is the root.
 
-One can see a human readable version of the final pform by using the
+One can see a human-readable version of the final pform by using the
 ``-P <path>'' flag to the ``ivl'' subcommand. This will cause ivl
 to dump the pform into the file named <path>. (Note that this is not
 normally done, unless debugging the ``ivl'' subcommand.)
@@ -167,17 +183,17 @@ This phase takes the pform and generates a netlist. The driver selects
 resolves references and expands the instantiations to form the design
 netlist. (See netlist.txt.) Final semantic checks are performed during
 elaboration, and some simple optimizations are performed. The netlist
-includes all the behavioral descriptions, as well as gates and wires.
+includes all the behavioural descriptions, as well as gates and wires.
 
 The elaborate() function performs the elaboration.
 
-One can see a human readable version of the final, elaborated and
+One can see a human-readable version of the final, elaborated and
 optimized netlist by using the ``-N <path>'' flag to the compiler. If
 elaboration succeeds, the final netlist (i.e., after optimizations but
 before code generation) will be dumped into the file named <path>.
 
-Elaboration is actually performed in two steps: scopes and parameters
-first, followed by the structural and behavioral elaboration.
+Elaboration is performed in two steps: scopes and parameters
+first, followed by the structural and behavioural elaboration.
 
 3.3.1 Scope Elaboration
 
@@ -186,7 +202,7 @@ tree of NetScope objects is built up and placed in the Design object,
 with the root module represented by the root NetScope object. The
 elab_scope.cc file contains most of the code for handling this phase.
 
-The tail of the elaborate_scope behavior (after the pform is
+The tail of the elaborate_scope behaviour (after the pform is
 traversed) includes a scan of the NetScope tree to locate defparam
 assignments that were collected during scope elaboration. This is when
 the defparam overrides are applied to the parameters.
@@ -195,14 +211,14 @@ the defparam overrides are applied to the parameters.
 
 After the scopes and parameters are generated and the NetScope tree
 fully formed, the elaboration runs through the pform again, this time
-generating the structural and behavioral netlist. Parameters are
+generating the structural and behavioural netlist. Parameters are
 elaborated and evaluated by now so all the constants of code
 generation are now known locally, so the netlist can be generated by
 simply passing through the pform.
 
 3.4 Optimization
 
-This is actually a collection of processing steps that perform
+This is a collection of processing steps that perform
 optimizations that do not depend on the target technology. Examples of
 some useful transformations are
 
@@ -220,7 +236,7 @@ generator (see target.h). This may require transforming the
 design to suit the technology.
 
 The emit() method of the Design class performs this step. It runs
-through the design elements, calling target functions as need arises
+through the design elements, calling target functions as the need arises
 to generate actual output.
 
 The user selects the target code generator with the -t flag on the
@@ -228,7 +244,7 @@ command line.
 
 3.6 ATTRIBUTES
 
-    NOTE: The $attribute syntax will soon be deprecated in favor of the
+    NOTE: The $attribute syntax will soon be deprecated in favour of the
     Verilog-2001 attribute syntax, which is cleaner and standardized.
 
 The parser accepts, as an extension to Verilog, the $attribute module
@@ -251,7 +267,7 @@ Attributes can also be applied to gate types. When this is done, the
 attribute is given to every instantiation of the primitive. The syntax
 for the attribute statement is the same, except that the <identifier>
 names a primitive earlier in the compilation unit and the statement is
-placed in global scope, instead of within a module. The semicolon is
+placed in the global scope, instead of within a module. The semicolon is
 not part of a type attribute.
 
 Note that attributes are also occasionally used for communication
@@ -310,7 +326,7 @@ by the compiler. See the iverilog(1) man page.
 
 Icarus Verilog is in development - as such it still only supports a
 (growing) subset of Verilog.  Below is a description of some of the
-currently unsupported Verilog features. This list is not exhaustive,
+currently unsupported Verilog features. This list is not exhaustive
 and does not account for errors in the compiler. See the Icarus
 Verilog web page for the current state of support for Verilog, and in
 particular, browse the bug report database for reported unsupported
@@ -339,7 +355,7 @@ constructs.
 5.1 Nonstandard Constructs or Behaviors
 
 Icarus Verilog includes some features that are not part of the
-IEEE1364 standard, but have well defined meaning, and also sometimes
+IEEE1364 standard, but have well-defined meaning, and also sometimes
 gives nonstandard (but extended) meanings to some features of the
 language that are defined. See the "extensions.txt" documentation for
 more details.
@@ -356,7 +372,7 @@ more details.
 	function is undefined if the argument doesn't have a
 	self-determined size.
 
-	The $sizeof function is deprecated in favor of $bits, which is
+	The $sizeof function is deprecated in favour of $bits, which is
 	the same thing, but included in the SystemVerilog definition.
 
     $simtime
@@ -382,8 +398,8 @@ more details.
 
     Builtin system functions
 
-	Certain of the system functions have well defined meanings, so
-	can theoretically be evaluated at compile time, instead of
+	Certain of the system functions have well-defined meanings, so
+	can theoretically be evaluated at compile-time, instead of
 	using runtime VPI code. Doing so means that VPI cannot
 	override the definitions of functions handled in this
 	manner. On the other hand, this makes them synthesizable, and
@@ -402,8 +418,8 @@ more details.
 
 	Icarus Verilog does preprocess modules that are loaded from
 	libraries via the -y mechanism. However, the only macros
-	defined during compilation of that file are those that it
-	defines itself (or includes) or that are defined on the
+	defined during the compilation of that file are those that it
+	defines itself (or includes) or that are defined in the
 	command line or command file.
 
 	Specifically, macros defined in the non-library source files
@@ -420,7 +436,7 @@ more details.
 	Standard Verilog does not allow width fields in the %t formats
 	of display strings. For example, this is illegal:
 
-		$display("Time is %0t", %time);
+		$display("Time is %0t", $time);
 
 	Standard Verilog instead relies on the $timeformat to
 	completely specify the format.
@@ -444,7 +460,7 @@ more details.
 
     time 0 race resolution.
 
-	Combinational logic is routinely modeled using always
+	Combinational logic is routinely modelled using always
 	blocks. However, this can lead to race conditions if the
 	inputs to the combinational block are initialized in initial
 	statements. Icarus Verilog slightly modifies time 0 scheduling
@@ -455,7 +471,7 @@ more details.
 
     Nets with Types
 
-	Icarus Verilog support an extension syntax that allows nets
+	Icarus Verilog supports an extended syntax that allows nets
 	and regs to be explicitly typed. The currently supported types
 	are logic, bool and real. This implies that "logic" and "bool"
 	are new keywords. Typical syntax is:
@@ -472,6 +488,6 @@ more details.
 Except where otherwise noted, Icarus Verilog, ivl and ivlpp are
 Copyright Stephen Williams. The proper notices are in the head of each
 file. However, I have early on received aid in the form of fixes,
-Verilog guidance, and especially testing from many people. Testers in
-particular include a larger community of people interested in a GPL
+Verilog guidance, and especially testing from many people. Testers, in
+particular, include a larger community of people interested in a GPL
 Verilog for Linux.

Statement.cc

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1998-2013 Stephen Williams ([email protected])
+ * Copyright (c) 1998-2019 Stephen Williams ([email protected])
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -23,6 +23,8 @@
 # include  "PExpr.h"
 # include  "ivl_assert.h"
 
+using namespace std;
+
 Statement::~Statement()
 {
 }
@@ -115,6 +117,11 @@ PBlock::~PBlock()
 	    delete list_[idx];
 }
 
+bool PBlock::var_init_needs_explicit_lifetime() const
+{
+      return default_lifetime == STATIC;
+}
+
 PChainConstructor* PBlock::extract_chain_constructor()
 {
       if (list_.empty())
@@ -153,6 +160,11 @@ void PBlock::push_statement_front(Statement*that)
       list_[0] = that;
 }
 
+PNamedItem::SymbolType PBlock::symbol_type() const
+{
+      return BLOCK;
+}
+
 PCallTask::PCallTask(const pform_name_t&n, const list<PExpr*>&p)
 : package_(0), path_(n), parms_(p.size())
 {
@@ -196,8 +208,8 @@ const pform_name_t& PCallTask::path() const
       return path_;
 }
 
-PCase::PCase(NetCase::TYPE t, PExpr*ex, svector<PCase::Item*>*l)
-: type_(t), expr_(ex), items_(l)
+PCase::PCase(ivl_case_quality_t q, NetCase::TYPE t, PExpr*ex, svector<PCase::Item*>*l)
+: quality_(q), type_(t), expr_(ex), items_(l)
 {
 }
 
@@ -289,20 +301,20 @@ PDoWhile::~PDoWhile()
 }
 
 PEventStatement::PEventStatement(const svector<PEEvent*>&ee)
-: expr_(ee), statement_(0)
+: expr_(ee), statement_(0), always_sens_(false)
 {
       assert(expr_.count() > 0);
 }
 
 
 PEventStatement::PEventStatement(PEEvent*ee)
-: expr_(1), statement_(0)
+: expr_(1), statement_(0), always_sens_(false)
 {
       expr_[0] = ee;
 }
 
-PEventStatement::PEventStatement(void)
-: statement_(0)
+PEventStatement::PEventStatement(bool always_sens)
+: statement_(0), always_sens_(always_sens)
 {
 }
 
@@ -406,8 +418,8 @@ PReturn::~PReturn()
       delete expr_;
 }
 
-PTrigger::PTrigger(const pform_name_t&e)
-: event_(e)
+PTrigger::PTrigger(PPackage*pkg, const pform_name_t&e)
+: package_(pkg), event_(e)
 {
 }
 

Statement.h

@@ -1,7 +1,7 @@
 #ifndef IVL_Statement_H
 #define IVL_Statement_H
 /*
- * Copyright (c) 1998-2014 Stephen Williams ([email protected])
+ * Copyright (c) 1998-2020 Stephen Williams ([email protected])
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -61,9 +61,9 @@ class PProcess : public LineInfo {
       ivl_process_type_t type() const { return type_; }
       Statement*statement() { return statement_; }
 
-      map<perm_string,PExpr*> attributes;
+      std::map<perm_string,PExpr*> attributes;
 
-      virtual void dump(ostream&out, unsigned ind) const;
+      virtual void dump(std::ostream&out, unsigned ind) const;
 
     private:
       ivl_process_type_t type_;
@@ -75,18 +75,18 @@ class PProcess : public LineInfo {
  * fact, the Statement class is abstract and represents all the
  * possible kinds of statements that exist in Verilog.
  */
-class Statement : public LineInfo {
+class Statement : virtual public LineInfo {
 
     public:
       Statement() { }
       virtual ~Statement() =0;
 
-      virtual void dump(ostream&out, unsigned ind) const;
+      virtual void dump(std::ostream&out, unsigned ind) const;
       virtual NetProc* elaborate(Design*des, NetScope*scope) const;
       virtual void elaborate_scope(Design*des, NetScope*scope) const;
       virtual void elaborate_sig(Design*des, NetScope*scope) const;
 
-      map<perm_string,PExpr*> attributes;
+      std::map<perm_string,PExpr*> attributes;
 };
 
 /*
@@ -108,7 +108,8 @@ class PAssign_  : public Statement {
       NetAssign_* elaborate_lval(Design*, NetScope*scope) const;
       NetExpr* elaborate_rval_(Design*, NetScope*, ivl_type_t lv_net_type,
 			       ivl_variable_type_t lv_type,
-			       unsigned lv_width) const;
+			       unsigned lv_width,
+			       bool force_unsigned =false) const;
       NetExpr* elaborate_rval_(Design*, NetScope*, ivl_type_t ntype) const;
 
       NetExpr* elaborate_rval_obj_(Design*, NetScope*,
@@ -138,7 +139,7 @@ class PAssign  : public PAssign_ {
       explicit PAssign(PExpr*lval, PExpr*ex, bool is_constant);
       ~PAssign();
 
-      virtual void dump(ostream&out, unsigned ind) const;
+      virtual void dump(std::ostream&out, unsigned ind) const;
       virtual NetProc* elaborate(Design*des, NetScope*scope) const;
 
     private:
@@ -154,7 +155,7 @@ class PAssignNB  : public PAssign_ {
       explicit PAssignNB(PExpr*lval, PExpr*cnt, PEventStatement*de, PExpr*ex);
       ~PAssignNB();
 
-      virtual void dump(ostream&out, unsigned ind) const;
+      virtual void dump(std::ostream&out, unsigned ind) const;
       virtual NetProc* elaborate(Design*des, NetScope*scope) const;
 
     private:
@@ -169,7 +170,7 @@ class PAssignNB  : public PAssign_ {
  * statements before constructing this object, so it knows a priori
  * what is contained.
  */
-class PBlock  : public PScope, public Statement {
+class PBlock  : public PScope, public Statement, public PNamedItem {
 
     public:
       enum BL_TYPE { BL_SEQ, BL_PAR, BL_JOIN_NONE, BL_JOIN_ANY };
@@ -182,6 +183,8 @@ class PBlock  : public PScope, public Statement {
 
       BL_TYPE bl_type() const { return bl_type_; }
 
+      bool var_init_needs_explicit_lifetime() const;
+
 	// This is only used if this block is the statement list for a
 	// constructor. We look for a PChainConstructor as the first
 	// statement, and if it is there, extract it.
@@ -197,11 +200,13 @@ class PBlock  : public PScope, public Statement {
 	// block.
       void push_statement_front(Statement*that);
 
-      virtual void dump(ostream&out, unsigned ind) const;
+      virtual void dump(std::ostream&out, unsigned ind) const;
       virtual NetProc* elaborate(Design*des, NetScope*scope) const;
       virtual void elaborate_scope(Design*des, NetScope*scope) const;
       virtual void elaborate_sig(Design*des, NetScope*scope) const;
 
+      SymbolType symbol_type() const;
+
     private:
       BL_TYPE bl_type_;
       std::vector<Statement*>list_;
@@ -210,14 +215,14 @@ class PBlock  : public PScope, public Statement {
 class PCallTask  : public Statement {
 
     public:
-      explicit PCallTask(PPackage*pkg, const pform_name_t&n, const list<PExpr*>&parms);
-      explicit PCallTask(const pform_name_t&n, const list<PExpr*>&parms);
-      explicit PCallTask(perm_string n, const list<PExpr*>&parms);
+      explicit PCallTask(PPackage*pkg, const pform_name_t&n, const std::list<PExpr*>&parms);
+      explicit PCallTask(const pform_name_t&n, const std::list<PExpr*>&parms);
+      explicit PCallTask(perm_string n, const std::list<PExpr*>&parms);
       ~PCallTask();
 
       const pform_name_t& path() const;
 
-      virtual void dump(ostream&out, unsigned ind) const;
+      virtual void dump(std::ostream&out, unsigned ind) const;
       virtual NetProc* elaborate(Design*des, NetScope*scope) const;
 
     private:
@@ -227,6 +232,8 @@ class PCallTask  : public Statement {
       NetProc*elaborate_method_(Design*des, NetScope*scope,
                                 bool add_this_flag = false) const;
       NetProc*elaborate_function_(Design*des, NetScope*scope) const;
+      NetProc*elaborate_void_function_(Design*des, NetScope*scope,
+				       NetFuncDef*def) const;
 
       NetProc*elaborate_build_call_(Design*des, NetScope*scope,
 				    NetScope*task, NetExpr*use_this) const;
@@ -234,30 +241,42 @@ class PCallTask  : public Statement {
 					 NetNet*net,
 					 perm_string method_name,
 					 const char*sys_task_name) const;
+      NetProc*elaborate_queue_method_(Design*des, NetScope*scope,
+				      NetNet*net,
+				      perm_string method_name,
+				      const char*sys_task_name) const;
+      NetProc*elaborate_method_func_(NetScope*scope,
+				     NetNet*net,
+				     ivl_variable_type_t type,
+				     unsigned width,
+				     bool signed_flag,
+				     perm_string method_name,
+				     const char*sys_task_name) const;
       bool test_task_calls_ok_(Design*des, NetScope*scope) const;
 
       PPackage*package_;
       pform_name_t path_;
-      vector<PExpr*> parms_;
+      std::vector<PExpr*> parms_;
 };
 
 class PCase  : public Statement {
 
     public:
       struct Item {
-	    list<PExpr*>expr;
+	    std::list<PExpr*>expr;
 	    Statement*stat;
       };
 
-      PCase(NetCase::TYPE, PExpr*ex, svector<Item*>*);
+      PCase(ivl_case_quality_t, NetCase::TYPE, PExpr*ex, svector<Item*>*);
       ~PCase();
 
       virtual NetProc* elaborate(Design*des, NetScope*scope) const;
       virtual void elaborate_scope(Design*des, NetScope*scope) const;
       virtual void elaborate_sig(Design*des, NetScope*scope) const;
-      virtual void dump(ostream&out, unsigned ind) const;
+      virtual void dump(std::ostream&out, unsigned ind) const;
 
     private:
+      ivl_case_quality_t quality_;
       NetCase::TYPE type_;
       PExpr*expr_;
 
@@ -275,7 +294,7 @@ class PCAssign  : public Statement {
       ~PCAssign();
 
       virtual NetCAssign* elaborate(Design*des, NetScope*scope) const;
-      virtual void dump(ostream&out, unsigned ind) const;
+      virtual void dump(std::ostream&out, unsigned ind) const;
 
     private:
       PExpr*lval_;
@@ -289,11 +308,11 @@ class PCAssign  : public Statement {
  */
 class PChainConstructor : public Statement {
     public:
-      PChainConstructor(const list<PExpr*>&parms);
+      explicit PChainConstructor(const std::list<PExpr*>&parms);
       ~PChainConstructor();
 
       virtual NetProc* elaborate(Design*des, NetScope*scope) const;
-      virtual void dump(ostream&out, unsigned ind) const;
+      virtual void dump(std::ostream&out, unsigned ind) const;
 
       inline const std::vector<PExpr*>& chain_args(void) const
       { return parms_; }
@@ -311,7 +330,7 @@ class PCondit  : public Statement {
       virtual NetProc* elaborate(Design*des, NetScope*scope) const;
       virtual void elaborate_scope(Design*des, NetScope*scope) const;
       virtual void elaborate_sig(Design*des, NetScope*scope) const;
-      virtual void dump(ostream&out, unsigned ind) const;
+      virtual void dump(std::ostream&out, unsigned ind) const;
 
     private:
       PExpr*expr_;
@@ -330,7 +349,7 @@ class PDeassign  : public Statement {
       ~PDeassign();
 
       virtual NetDeassign* elaborate(Design*des, NetScope*scope) const;
-      virtual void dump(ostream&out, unsigned ind) const;
+      virtual void dump(std::ostream&out, unsigned ind) const;
 
     private:
       PExpr*lval_;
@@ -342,7 +361,7 @@ class PDelayStatement  : public Statement {
       PDelayStatement(PExpr*d, Statement*st);
       ~PDelayStatement();
 
-      virtual void dump(ostream&out, unsigned ind) const;
+      virtual void dump(std::ostream&out, unsigned ind) const;
       virtual NetProc* elaborate(Design*des, NetScope*scope) const;
       virtual void elaborate_scope(Design*des, NetScope*scope) const;
       virtual void elaborate_sig(Design*des, NetScope*scope) const;
@@ -362,7 +381,7 @@ class PDisable  : public Statement {
       explicit PDisable(const pform_name_t&sc);
       ~PDisable();
 
-      virtual void dump(ostream&out, unsigned ind) const;
+      virtual void dump(std::ostream&out, unsigned ind) const;
       virtual NetProc* elaborate(Design*des, NetScope*scope) const;
 
     private:
@@ -378,7 +397,7 @@ class PDoWhile  : public Statement {
       virtual NetProc* elaborate(Design*des, NetScope*scope) const;
       virtual void elaborate_scope(Design*des, NetScope*scope) const;
       virtual void elaborate_sig(Design*des, NetScope*scope) const;
-      virtual void dump(ostream&out, unsigned ind) const;
+      virtual void dump(std::ostream&out, unsigned ind) const;
 
     private:
       PExpr*cond_;
@@ -399,17 +418,18 @@ class PEventStatement  : public Statement {
 
       explicit PEventStatement(const svector<PEEvent*>&ee);
       explicit PEventStatement(PEEvent*ee);
-	// Make an @* statement.
-      explicit PEventStatement(void);
+	// Make an @* statement or make a special @* version with the items
+	// from functions added and outputs removed for always_comb/latch.
+      explicit PEventStatement(bool always_sens = false);
 
       ~PEventStatement();
 
       void set_statement(Statement*st);
 
-      virtual void dump(ostream&out, unsigned ind) const;
+      virtual void dump(std::ostream&out, unsigned ind) const;
 	// Call this with a NULL statement only. It is used to print
 	// the event expression for inter-assignment event controls.
-      virtual void dump_inline(ostream&out) const;
+      virtual void dump_inline(std::ostream&out) const;
       virtual NetProc* elaborate(Design*des, NetScope*scope) const;
       virtual void elaborate_scope(Design*des, NetScope*scope) const;
       virtual void elaborate_sig(Design*des, NetScope*scope) const;
@@ -426,9 +446,10 @@ class PEventStatement  : public Statement {
     private:
       svector<PEEvent*>expr_;
       Statement*statement_;
+      bool always_sens_;
 };
 
-ostream& operator << (ostream&o, const PEventStatement&obj);
+std::ostream& operator << (std::ostream&o, const PEventStatement&obj);
 
 class PForce  : public Statement {
 
@@ -437,7 +458,7 @@ class PForce  : public Statement {
       ~PForce();
 
       virtual NetForce* elaborate(Design*des, NetScope*scope) const;
-      virtual void dump(ostream&out, unsigned ind) const;
+      virtual void dump(std::ostream&out, unsigned ind) const;
 
     private:
       PExpr*lval_;
@@ -452,7 +473,7 @@ class PForeach : public Statement {
       virtual NetProc* elaborate(Design*des, NetScope*scope) const;
       virtual void elaborate_scope(Design*des, NetScope*scope) const;
       virtual void elaborate_sig(Design*des, NetScope*scope) const;
-      virtual void dump(ostream&out, unsigned ind) const;
+      virtual void dump(std::ostream&out, unsigned ind) const;
 
     private:
       NetProc* elaborate_static_array_(Design*des, NetScope*scope,
@@ -472,7 +493,7 @@ class PForever : public Statement {
       virtual NetProc* elaborate(Design*des, NetScope*scope) const;
       virtual void elaborate_scope(Design*des, NetScope*scope) const;
       virtual void elaborate_sig(Design*des, NetScope*scope) const;
-      virtual void dump(ostream&out, unsigned ind) const;
+      virtual void dump(std::ostream&out, unsigned ind) const;
 
     private:
       Statement*statement_;
@@ -488,7 +509,7 @@ class PForStatement  : public Statement {
       virtual NetProc* elaborate(Design*des, NetScope*scope) const;
       virtual void elaborate_scope(Design*des, NetScope*scope) const;
       virtual void elaborate_sig(Design*des, NetScope*scope) const;
-      virtual void dump(ostream&out, unsigned ind) const;
+      virtual void dump(std::ostream&out, unsigned ind) const;
 
     private:
       PExpr* name1_;
@@ -516,7 +537,7 @@ class PRepeat : public Statement {
       virtual NetProc* elaborate(Design*des, NetScope*scope) const;
       virtual void elaborate_scope(Design*des, NetScope*scope) const;
       virtual void elaborate_sig(Design*des, NetScope*scope) const;
-      virtual void dump(ostream&out, unsigned ind) const;
+      virtual void dump(std::ostream&out, unsigned ind) const;
 
     private:
       PExpr*expr_;
@@ -530,7 +551,7 @@ class PRelease  : public Statement {
       ~PRelease();
 
       virtual NetProc* elaborate(Design*des, NetScope*scope) const;
-      virtual void dump(ostream&out, unsigned ind) const;
+      virtual void dump(std::ostream&out, unsigned ind) const;
 
     private:
       PExpr*lval_;
@@ -556,13 +577,14 @@ class PReturn  : public Statement {
 class PTrigger  : public Statement {
 
     public:
-      explicit PTrigger(const pform_name_t&ev);
+      explicit PTrigger(PPackage*pkg, const pform_name_t&ev);
       ~PTrigger();
 
       virtual NetProc* elaborate(Design*des, NetScope*scope) const;
-      virtual void dump(ostream&out, unsigned ind) const;
+      virtual void dump(std::ostream&out, unsigned ind) const;
 
     private:
+      PPackage*package_;
       pform_name_t event_;
 };
 
@@ -575,7 +597,7 @@ class PWhile  : public Statement {
       virtual NetProc* elaborate(Design*des, NetScope*scope) const;
       virtual void elaborate_scope(Design*des, NetScope*scope) const;
       virtual void elaborate_sig(Design*des, NetScope*scope) const;
-      virtual void dump(ostream&out, unsigned ind) const;
+      virtual void dump(std::ostream&out, unsigned ind) const;
 
     private:
       PExpr*cond_;

aclocal.m4

@@ -6,7 +6,7 @@
 # different builds. Remember to change the default suffix string to some
 # value appropriate for the current version.
 AC_DEFUN([AX_ENABLE_SUFFIX],
-[AC_ARG_ENABLE([suffix],[AC_HELP_STRING([--enable-suffix],
+[AC_ARG_ENABLE([suffix],[AS_HELP_STRING([--enable-suffix],
                                         [Use/set the installation command suffix])],
                [true],[enable_suffix=no])
 if test X$enable_suffix = Xyes; then
@@ -23,11 +23,13 @@ AC_SUBST(install_suffix)
 # ------------------------------
 # Sub-macro for AX_C_UNDERSCORES_LEADING and AX_C_UNDERSCORES_TRAILING.
 # Unwarranted assumptions:
-#   - the object file produced by AC_COMPILE_IFELSE is called "conftest.$ac_objext"
-#   - the nm(1) utility is available, and its name is "nm".
+#   - the object file produced by AC_COMPILE_IFELSE is called
+#     "conftest.$ac_objext"
+#   - the nm(1) utility or an equivalent is available, and its name
+#     is defined by the $NM variable.
 AC_DEFUN([_AX_C_UNDERSCORES_MATCH_IF],
 [AC_COMPILE_IFELSE([AC_LANG_SOURCE([void underscore(void){}])],
-[AS_IF([nm conftest.$ac_objext|grep $1 >/dev/null 2>/dev/null],[$2],[$3])],
+[AS_IF([$NM conftest.$ac_objext|grep $1 >/dev/null 2>/dev/null],[$2],[$3])],
 [AC_MSG_ERROR([underscore test crashed])]
 )])
 
@@ -223,8 +225,11 @@ AC_SUBST(strip_dynamic)
 # -------------
 AC_DEFUN([AX_C99_STRTOD],
 [# On MinGW we need to jump through hoops to get a C99 compliant strtod().
+ # mingw-w64 doesn't need this, and the 64-bit version doesn't support it.
 case "${host}" in
-    *-*-mingw*)
+    x86_64-w64-mingw32)
+        ;;
+    *-*-mingw32)
         LDFLAGS+=" -Wl,--undefined=___strtod,--wrap,strtod,--defsym,___wrap_strtod=___strtod"
         ;;
 esac
@@ -243,3 +248,143 @@ _config_header=$1
 _stamp_name=stamp-`expr //$_config_header : '.*/\([[^./]]*\)\.[[^./]]*$'`-h
 echo "timestamp for $_config_header" > `AS_DIRNAME(["$_config_header"])`/[]$_stamp_name
 ]) #_AC_AM_CONFIG_HEADER_HOOK
+
+# ===========================================================================
+#   https://www.gnu.org/software/autoconf-archive/ax_prog_cc_for_build.html
+# ===========================================================================
+#
+# SYNOPSIS
+#
+#   AX_PROG_CC_FOR_BUILD
+#
+# DESCRIPTION
+#
+#   This macro searches for a C compiler that generates native executables,
+#   that is a C compiler that surely is not a cross-compiler. This can be
+#   useful if you have to generate source code at compile-time like for
+#   example GCC does.
+#
+#   The macro sets the CC_FOR_BUILD and CPP_FOR_BUILD macros to anything
+#   needed to compile or link (CC_FOR_BUILD) and preprocess (CPP_FOR_BUILD).
+#   The value of these variables can be overridden by the user by specifying
+#   a compiler with an environment variable (like you do for standard CC).
+#
+#   It also sets BUILD_EXEEXT and BUILD_OBJEXT to the executable and object
+#   file extensions for the build platform, and GCC_FOR_BUILD to `yes' if
+#   the compiler we found is GCC. All these variables but GCC_FOR_BUILD are
+#   substituted in the Makefile.
+#
+# LICENSE
+#
+#   Copyright (c) 2008 Paolo Bonzini <[email protected]>
+#
+#   Copying and distribution of this file, with or without modification, are
+#   permitted in any medium without royalty provided the copyright notice
+#   and this notice are preserved. This file is offered as-is, without any
+#   warranty.
+
+#serial 18
+
+AU_ALIAS([AC_PROG_CC_FOR_BUILD], [AX_PROG_CC_FOR_BUILD])
+AC_DEFUN([AX_PROG_CC_FOR_BUILD], [dnl
+AC_REQUIRE([AC_PROG_CC])dnl
+AC_REQUIRE([AC_PROG_CPP])dnl
+AC_REQUIRE([AC_CANONICAL_BUILD])dnl
+
+dnl Use the standard macros, but make them use other variable names
+dnl
+pushdef([ac_cv_prog_CPP], ac_cv_build_prog_CPP)dnl
+pushdef([ac_cv_prog_cc_c89], ac_cv_build_prog_cc_c89)dnl
+pushdef([ac_cv_prog_gcc], ac_cv_build_prog_gcc)dnl
+pushdef([ac_cv_prog_cc_works], ac_cv_build_prog_cc_works)dnl
+pushdef([ac_cv_prog_cc_cross], ac_cv_build_prog_cc_cross)dnl
+pushdef([ac_cv_prog_cc_g], ac_cv_build_prog_cc_g)dnl
+pushdef([ac_cv_c_compiler_gnu], ac_cv_build_c_compiler_gnu)dnl
+pushdef([ac_cv_exeext], ac_cv_build_exeext)dnl
+pushdef([ac_cv_objext], ac_cv_build_objext)dnl
+pushdef([ac_exeext], ac_build_exeext)dnl
+pushdef([ac_objext], ac_build_objext)dnl
+pushdef([CC], CC_FOR_BUILD)dnl
+pushdef([CPP], CPP_FOR_BUILD)dnl
+pushdef([GCC], GCC_FOR_BUILD)dnl
+pushdef([CFLAGS], CFLAGS_FOR_BUILD)dnl
+pushdef([CPPFLAGS], CPPFLAGS_FOR_BUILD)dnl
+pushdef([EXEEXT], BUILD_EXEEXT)dnl
+pushdef([LDFLAGS], LDFLAGS_FOR_BUILD)dnl
+pushdef([OBJEXT], BUILD_OBJEXT)dnl
+pushdef([host], build)dnl
+pushdef([host_alias], build_alias)dnl
+pushdef([host_cpu], build_cpu)dnl
+pushdef([host_vendor], build_vendor)dnl
+pushdef([host_os], build_os)dnl
+pushdef([ac_cv_host], ac_cv_build)dnl
+pushdef([ac_cv_host_alias], ac_cv_build_alias)dnl
+pushdef([ac_cv_host_cpu], ac_cv_build_cpu)dnl
+pushdef([ac_cv_host_vendor], ac_cv_build_vendor)dnl
+pushdef([ac_cv_host_os], ac_cv_build_os)dnl
+pushdef([ac_tool_prefix], ac_build_tool_prefix)dnl
+pushdef([am_cv_CC_dependencies_compiler_type], am_cv_build_CC_dependencies_compiler_type)dnl
+pushdef([am_cv_prog_cc_c_o], am_cv_build_prog_cc_c_o)dnl
+pushdef([cross_compiling], cross_compiling_build)dnl
+
+cross_compiling_build=no
+
+ac_build_tool_prefix=
+AS_IF([test -n "$build"],      [ac_build_tool_prefix="$build-"],
+      [test -n "$build_alias"],[ac_build_tool_prefix="$build_alias-"])
+
+AC_LANG_PUSH([C])
+AC_PROG_CC
+_AC_COMPILER_EXEEXT
+_AC_COMPILER_OBJEXT
+AC_PROG_CPP
+
+dnl Restore the old definitions
+dnl
+popdef([cross_compiling])dnl
+popdef([am_cv_prog_cc_c_o])dnl
+popdef([am_cv_CC_dependencies_compiler_type])dnl
+popdef([ac_tool_prefix])dnl
+popdef([ac_cv_host_os])dnl
+popdef([ac_cv_host_vendor])dnl
+popdef([ac_cv_host_cpu])dnl
+popdef([ac_cv_host_alias])dnl
+popdef([ac_cv_host])dnl
+popdef([host_os])dnl
+popdef([host_vendor])dnl
+popdef([host_cpu])dnl
+popdef([host_alias])dnl
+popdef([host])dnl
+popdef([OBJEXT])dnl
+popdef([LDFLAGS])dnl
+popdef([EXEEXT])dnl
+popdef([CPPFLAGS])dnl
+popdef([CFLAGS])dnl
+popdef([GCC])dnl
+popdef([CPP])dnl
+popdef([CC])dnl
+popdef([ac_objext])dnl
+popdef([ac_exeext])dnl
+popdef([ac_cv_objext])dnl
+popdef([ac_cv_exeext])dnl
+popdef([ac_cv_c_compiler_gnu])dnl
+popdef([ac_cv_prog_cc_g])dnl
+popdef([ac_cv_prog_cc_cross])dnl
+popdef([ac_cv_prog_cc_works])dnl
+popdef([ac_cv_prog_cc_c89])dnl
+popdef([ac_cv_prog_gcc])dnl
+popdef([ac_cv_prog_CPP])dnl
+
+dnl restore global variables ac_ext, ac_cpp, ac_compile,
+dnl ac_link, ac_compiler_gnu (dependant on the current
+dnl language after popping):
+AC_LANG_POP([C])
+
+dnl Finally, set Makefile variables
+dnl
+AC_SUBST(BUILD_EXEEXT)dnl
+AC_SUBST(BUILD_OBJEXT)dnl
+AC_SUBST([CFLAGS_FOR_BUILD])dnl
+AC_SUBST([CPPFLAGS_FOR_BUILD])dnl
+AC_SUBST([LDFLAGS_FOR_BUILD])dnl
+])

cadpli/Makefile.in

@@ -59,7 +59,7 @@ distclean: clean
 	rm -f Makefile config.log
 
 cppcheck: $(O:.o=.c)
-	cppcheck --enable=all -f $(INCLUDE_PATH) $^
+	cppcheck --enable=all --std=posix --std=c99 --std=c++03 -f $(INCLUDE_PATH) $^
 
 Makefile: $(srcdir)/Makefile.in ../config.status
 	cd ..; ./config.status --file=cadpli/$@
@@ -71,17 +71,19 @@ dep:
 	$(CC) $(CPPFLAGS) $(CFLAGS) @DEPENDENCY_FLAG@ -c $<
 	mv $*.d dep
 
-SYSTEM_VPI_LDFLAGS = -L../vvp -lvpi
+SYSTEM_VPI_LDFLAGS = -L../vpi -lvpi
 ifeq (@MINGW32@,yes)
     SYSTEM_VPI_LDFLAGS += @EXTRALIBS@
 endif
 
-cadpli.vpl: $O ../vvp/libvpi.a ../libveriuser/libveriuser.o
+cadpli.vpl: $O ../vpi/libvpi.a ../libveriuser/libveriuser.o
 	$(CC) @shared@ $(LDFLAGS) -o $@ $O ../libveriuser/libveriuser.o $(SYSTEM_VPI_LDFLAGS)
 
-install: all installdirs $(vpidir)/cadpli.vpl
+install: all installdirs installfiles
 
-$(vpidir)/cadpli.vpl: ./cadpli.vpl
+F = ./cadpli.vpl
+
+installfiles: $(F) | installdirs
 	$(INSTALL_PROGRAM) ./cadpli.vpl "$(DESTDIR)$(vpidir)/cadpli.vpl"
 
 installdirs: $(srcdir)/../mkinstalldirs

compiler.h

@@ -1,7 +1,7 @@
 #ifndef IVL_compiler_H
 #define IVL_compiler_H
 /*
- * Copyright (c) 1999-2014 Stephen Williams ([email protected])
+ * Copyright (c) 1999-2019 Stephen Williams ([email protected])
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -80,6 +80,10 @@ extern unsigned recursive_mod_limit;
 /* Implicit definitions of wires. */
 extern bool warn_implicit;
 
+/* Warn if dimensions of port or var/net are implicitly taken from
+   the input/output/inout declaration. */
+extern bool warn_implicit_dimensions;
+
 /* inherit timescales across files. */
 extern bool warn_timescale;
 
@@ -100,6 +104,9 @@ extern bool warn_sens_entire_arr;
 /* Warn about level-appropriate anachronisms. */
 extern bool warn_anachronisms;
 
+/* Warn about nets that are references but not driven. */
+extern bool warn_floating_nets;
+
 /* This is true if verbose output is requested. */
 extern bool verbose_flag;
 
@@ -110,6 +117,13 @@ extern bool debug_emit;
 extern bool debug_synth2;
 extern bool debug_optimizer;
 
+/* Ignore errors about missing modules */
+extern bool ignore_missing_modules;
+
+/* Treat each source file as a separate compilation unit (as defined
+   by SystemVerilog). */
+extern bool separate_compilation;
+
 /* Control evaluation of functions at compile time:
  *   0 = only for functions in constant expressions
  *   1 = only for automatic functions
@@ -133,12 +147,13 @@ extern unsigned long array_size_limit;
 extern const char*basedir;
 
 /* This is an ordered list of library suffixes to search. */
-extern list<const char*>library_suff;
+extern std::list<const char*>library_suff;
 extern int build_library_index(const char*path, bool key_case_sensitive);
 
 /* This is the generation of Verilog that the compiler is asked to
    support. Then there are also more detailed controls for more
-   specific language features. */
+   specific language features. Note that the compiler often assumes
+   this is an ordered list. */
 enum generation_t {
       GN_VER1995  = 1,
       GN_VER2001_NOCONFIG  = 2,
@@ -162,9 +177,12 @@ extern bool gn_icarus_misc_flag;
    is false, then skip elaboration of specify behavior. */
 extern bool gn_specify_blocks_flag;
 
-/* If this flag is true, then elaborate assertions. If this flag is
-   false, then stub out assertion statements. */
-extern bool gn_assertions_flag;
+/* If this flag is true, then elaborate supported assertion statements. If
+   this flag is false, then stub out supported assertion statements. */
+extern bool gn_supported_assertions_flag;
+/* If this flag is true, then error on unsupported assertion statements. If
+   this flag is false, then stub out unsupported assertion statements. */
+extern bool gn_unsupported_assertions_flag;
 
 /* If this flag is true, then support/elaborate Verilog-AMS. */
 extern bool gn_verilog_ams_flag;
@@ -182,25 +200,24 @@ extern bool gn_strict_ca_eval_flag;
    standard expression width rules. */
 extern bool gn_strict_expr_width_flag;
 
-/* If variables can be converted to uwires by a continuous assignment
-   (assuming no procedural assign, then return true. This will be true
-   for SystemVerilog */
-static inline bool gn_var_can_be_uwire(void)
+/* If this flag is true, then don't add a for-loop control variable
+   to an implicit event_expression list if it is only used inside the
+   loop. */
+extern bool gn_shared_loop_index_flag;
+
+static inline bool gn_system_verilog(void)
 {
-      if (generation_flag == GN_VER2005_SV ||
-          generation_flag == GN_VER2009  ||
-          generation_flag == GN_VER2012)
+      if (generation_flag >= GN_VER2005_SV)
 	    return true;
       return false;
 }
 
-static inline bool gn_system_verilog(void)
+/* If variables can be converted to uwires by a continuous assignment
+   (assuming no procedural assign), then return true. This will be true
+   for SystemVerilog */
+static inline bool gn_var_can_be_uwire(void)
 {
-      if (generation_flag == GN_VER2005_SV ||
-          generation_flag == GN_VER2009  ||
-          generation_flag == GN_VER2012)
-	    return true;
-      return false;
+      return gn_system_verilog();
 }
 
 static inline bool gn_modules_nest(void)
@@ -227,14 +244,14 @@ extern int lexor_keyword_mask;
   /* This is the string to use to invoke the preprocessor. */
 extern char*ivlpp_string;
 
-extern map<perm_string,unsigned> missing_modules;
+extern std::map<perm_string,unsigned> missing_modules;
 
   /* Files that are library files are in this map. The lexor compares
      file names as it processes `line directives, and if the file name
      matches an entry in this table, it will turn on the
      library_active_flag so that modules know that they are in a
      library. */
-extern map<perm_string,bool> library_file_map;
+extern std::map<perm_string,bool> library_file_map;
 
 /*
  * the lex_strings are perm_strings made up of tokens from the source
@@ -269,12 +286,20 @@ struct sfunc_return_type {
       const char*   name;
       ivl_variable_type_t type;
       unsigned      wid;
-      int           signed_flag;
+      bool          signed_flag;
+      bool          override_flag;
 };
 
+extern void add_sys_func(const struct sfunc_return_type&ret_type);
 extern const struct sfunc_return_type* lookup_sys_func(const char*name);
 extern int load_sys_func_table(const char*path);
 extern void cleanup_sys_func_table();
+/*
+ * This temporarily loads a VPI module, to determine the return values
+ * of system functions provided by that module, and adds the return values
+ * to the system function table.
+ */
+extern bool load_vpi_module(const char*path);
 
 /*
  * In system Verilog it is allowed with a warning to call a function

config.h.in

@@ -1,7 +1,7 @@
 #ifndef IVL_config_H                                           /* -*- c++ -*- */
 #define IVL_config_H
 /*
- * Copyright (c) 2001-2014 Stephen Williams ([email protected])
+ * Copyright (c) 2001-2021 Stephen Williams ([email protected])
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -19,14 +19,6 @@
  *    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
  */
 
-#if defined(__cplusplus)
-#  if !defined(__GNUC__)
-     using namespace std;
-#  elif (__GNUC__ == 3)
-     using namespace std;
-#  endif
-#endif
-
 # undef NEED_LU
 # undef NEED_TU
 # undef WLU
@@ -55,6 +47,7 @@
 # undef HAVE_FSEEKO
 /* And this is needed by the fst files (copied from GTKWave). */
 # undef HAVE_LIBPTHREAD
+# undef HAVE_REALPATH
 
 /*
  * Define this if you want to compile vvp with memory freeing and

config.sub

@@ -1,44 +1,40 @@
 #! /bin/sh
 # Configuration validation subroutine script.
-#   Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
-#   2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
-#   Free Software Foundation, Inc.
+#   Copyright 1992-2015 Free Software Foundation, Inc.
 
-timestamp='2009-04-17'
+timestamp='2015-03-08'
 
-# This file is (in principle) common to ALL GNU software.
-# The presence of a machine in this file suggests that SOME GNU software
-# can handle that machine.  It does not imply ALL GNU software can.
-#
-# This file is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2 of the License, or
+# This file is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
 # (at your option) any later version.
 #
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
+# This program is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+# General Public License for more details.
 #
 # You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
-# 02110-1301, USA.
+# along with this program; if not, see <http://www.gnu.org/licenses/>.
 #
 # As a special exception to the GNU General Public License, if you
 # distribute this file as part of a program that contains a
 # configuration script generated by Autoconf, you may include it under
-# the same distribution terms that you use for the rest of that program.
+# the same distribution terms that you use for the rest of that
+# program.  This Exception is an additional permission under section 7
+# of the GNU General Public License, version 3 ("GPLv3").
 
 
-# Please send patches to <[email protected]>.  Submit a context
-# diff and a properly formatted ChangeLog entry.
+# Please send patches to <[email protected]>.
 #
 # Configuration subroutine to validate and canonicalize a configuration type.
 # Supply the specified configuration type as an argument.
 # If it is invalid, we print an error message on stderr and exit with code 1.
 # Otherwise, we print the canonical config type on stdout and succeed.
 
+# You can get the latest version of this script from:
+# http://git.savannah.gnu.org/gitweb/?p=config.git;a=blob_plain;f=config.sub;hb=HEAD
+
 # This file is supposed to be the same for all GNU packages
 # and recognize all the CPU types, system types and aliases
 # that are meaningful with *any* GNU software.
@@ -72,8 +68,7 @@ Report bugs and patches to <[email protected]>."
 version="\
 GNU config.sub ($timestamp)
 
-Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
-2002, 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
+Copyright 1992-2015 Free Software Foundation, Inc.
 
 This is free software; see the source for copying conditions.  There is NO
 warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE."
@@ -120,13 +115,18 @@ esac
 # Here we must recognize all the valid KERNEL-OS combinations.
 maybe_os=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\2/'`
 case $maybe_os in
-  nto-qnx* | linux-gnu* | linux-dietlibc | linux-newlib* | linux-uclibc* | \
-  uclinux-uclibc* | uclinux-gnu* | kfreebsd*-gnu* | knetbsd*-gnu* | netbsd*-gnu* | \
+  nto-qnx* | linux-gnu* | linux-android* | linux-dietlibc | linux-newlib* | \
+  linux-musl* | linux-uclibc* | uclinux-uclibc* | uclinux-gnu* | kfreebsd*-gnu* | \
+  knetbsd*-gnu* | netbsd*-gnu* | netbsd*-eabi* | \
   kopensolaris*-gnu* | \
   storm-chaos* | os2-emx* | rtmk-nova*)
     os=-$maybe_os
     basic_machine=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\1/'`
     ;;
+  android-linux)
+    os=-linux-android
+    basic_machine=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\1/'`-unknown
+    ;;
   *)
     basic_machine=`echo $1 | sed 's/-[^-]*$//'`
     if [ $basic_machine != $1 ]
@@ -149,10 +149,13 @@ case $os in
 	-convergent* | -ncr* | -news | -32* | -3600* | -3100* | -hitachi* |\
 	-c[123]* | -convex* | -sun | -crds | -omron* | -dg | -ultra | -tti* | \
 	-harris | -dolphin | -highlevel | -gould | -cbm | -ns | -masscomp | \
-	-apple | -axis | -knuth | -cray)
+	-apple | -axis | -knuth | -cray | -microblaze*)
 		os=
 		basic_machine=$1
 		;;
+	-bluegene*)
+		os=-cnk
+		;;
 	-sim | -cisco | -oki | -wec | -winbond)
 		os=
 		basic_machine=$1
@@ -167,10 +170,10 @@ case $os in
 		os=-chorusos
 		basic_machine=$1
 		;;
- 	-chorusrdb)
- 		os=-chorusrdb
+	-chorusrdb)
+		os=-chorusrdb
 		basic_machine=$1
- 		;;
+		;;
 	-hiux*)
 		os=-hiuxwe2
 		;;
@@ -215,6 +218,12 @@ case $os in
 	-isc*)
 		basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'`
 		;;
+	-lynx*178)
+		os=-lynxos178
+		;;
+	-lynx*5)
+		os=-lynxos5
+		;;
 	-lynx*)
 		os=-lynxos
 		;;
@@ -239,20 +248,28 @@ case $basic_machine in
 	# Some are omitted here because they have special meanings below.
 	1750a | 580 \
 	| a29k \
+	| aarch64 | aarch64_be \
 	| alpha | alphaev[4-8] | alphaev56 | alphaev6[78] | alphapca5[67] \
 	| alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] | alpha64pca5[67] \
 	| am33_2.0 \
-	| arc | arm | arm[bl]e | arme[lb] | armv[2345] | armv[345][lb] | avr | avr32 \
+	| arc | arceb \
+	| arm | arm[bl]e | arme[lb] | armv[2-8] | armv[3-8][lb] | armv7[arm] \
+	| avr | avr32 \
+	| be32 | be64 \
 	| bfin \
-	| c4x | clipper \
+	| c4x | c8051 | clipper \
 	| d10v | d30v | dlx | dsp16xx \
-	| fido | fr30 | frv \
+	| e2k | epiphany \
+	| fido | fr30 | frv | ft32 \
 	| h8300 | h8500 | hppa | hppa1.[01] | hppa2.0 | hppa2.0[nw] | hppa64 \
+	| hexagon \
 	| i370 | i860 | i960 | ia64 \
 	| ip2k | iq2000 \
+	| k1om \
+	| le32 | le64 \
 	| lm32 \
 	| m32c | m32r | m32rle | m68000 | m68k | m88k \
-	| maxq | mb | microblaze | mcore | mep | metag \
+	| maxq | mb | microblaze | microblazeel | mcore | mep | metag \
 	| mips | mipsbe | mipseb | mipsel | mipsle \
 	| mips16 \
 	| mips64 | mips64el \
@@ -266,36 +283,55 @@ case $basic_machine in
 	| mips64vr5900 | mips64vr5900el \
 	| mipsisa32 | mipsisa32el \
 	| mipsisa32r2 | mipsisa32r2el \
+	| mipsisa32r6 | mipsisa32r6el \
 	| mipsisa64 | mipsisa64el \
 	| mipsisa64r2 | mipsisa64r2el \
+	| mipsisa64r6 | mipsisa64r6el \
 	| mipsisa64sb1 | mipsisa64sb1el \
 	| mipsisa64sr71k | mipsisa64sr71kel \
+	| mipsr5900 | mipsr5900el \
 	| mipstx39 | mipstx39el \
 	| mn10200 | mn10300 \
 	| moxie \
 	| mt \
 	| msp430 \
-	| nios | nios2 \
+	| nds32 | nds32le | nds32be \
+	| nios | nios2 | nios2eb | nios2el \
 	| ns16k | ns32k \
-	| or32 \
+	| open8 | or1k | or1knd | or32 \
 	| pdp10 | pdp11 | pj | pjl \
-	| powerpc | powerpc64 | powerpc64le | powerpcle | ppcbe \
+	| powerpc | powerpc64 | powerpc64le | powerpcle \
 	| pyramid \
+	| riscv32 | riscv64 \
+	| rl78 | rx \
 	| score \
 	| sh | sh[1234] | sh[24]a | sh[24]aeb | sh[23]e | sh[34]eb | sheb | shbe | shle | sh[1234]le | sh3ele \
 	| sh64 | sh64le \
 	| sparc | sparc64 | sparc64b | sparc64v | sparc86x | sparclet | sparclite \
 	| sparcv8 | sparcv9 | sparcv9b | sparcv9v \
-	| spu | strongarm \
-	| tahoe | thumb | tic4x | tic80 | tron \
-	| v850 | v850e \
+	| spu \
+	| tahoe | tic4x | tic54x | tic55x | tic6x | tic80 | tron \
+	| ubicom32 \
+	| v850 | v850e | v850e1 | v850e2 | v850es | v850e2v3 \
+	| visium \
 	| we32k \
-	| x86 | xc16x | xscale | xscalee[bl] | xstormy16 | xtensa \
+	| x86 | xc16x | xstormy16 | xtensa \
 	| z8k | z80)
 		basic_machine=$basic_machine-unknown
 		;;
-	m6811 | m68hc11 | m6812 | m68hc12)
-		# Motorola 68HC11/12.
+	c54x)
+		basic_machine=tic54x-unknown
+		;;
+	c55x)
+		basic_machine=tic55x-unknown
+		;;
+	c6x)
+		basic_machine=tic6x-unknown
+		;;
+	leon|leon[3-9])
+		basic_machine=sparc-$basic_machine
+		;;
+	m6811 | m68hc11 | m6812 | m68hc12 | m68hcs12x | nvptx | picochip)
 		basic_machine=$basic_machine-unknown
 		os=-none
 		;;
@@ -305,6 +341,21 @@ case $basic_machine in
 		basic_machine=mt-unknown
 		;;
 
+	strongarm | thumb | xscale)
+		basic_machine=arm-unknown
+		;;
+	xgate)
+		basic_machine=$basic_machine-unknown
+		os=-none
+		;;
+	xscaleeb)
+		basic_machine=armeb-unknown
+		;;
+
+	xscaleel)
+		basic_machine=armel-unknown
+		;;
+
 	# We use `pc' rather than `unknown'
 	# because (1) that's what they normally are, and
 	# (2) the word "unknown" tends to confuse beginning users.
@@ -319,25 +370,31 @@ case $basic_machine in
 	# Recognize the basic CPU types with company name.
 	580-* \
 	| a29k-* \
+	| aarch64-* | aarch64_be-* \
 	| alpha-* | alphaev[4-8]-* | alphaev56-* | alphaev6[78]-* \
 	| alpha64-* | alpha64ev[4-8]-* | alpha64ev56-* | alpha64ev6[78]-* \
-	| alphapca5[67]-* | alpha64pca5[67]-* | arc-* \
+	| alphapca5[67]-* | alpha64pca5[67]-* | arc-* | arceb-* \
 	| arm-*  | armbe-* | armle-* | armeb-* | armv*-* \
 	| avr-* | avr32-* \
+	| be32-* | be64-* \
 	| bfin-* | bs2000-* \
-	| c[123]* | c30-* | [cjt]90-* | c4x-* | c54x-* | c55x-* | c6x-* \
-	| clipper-* | craynv-* | cydra-* \
+	| c[123]* | c30-* | [cjt]90-* | c4x-* \
+	| c8051-* | clipper-* | craynv-* | cydra-* \
 	| d10v-* | d30v-* | dlx-* \
-	| elxsi-* \
+	| e2k-* | elxsi-* \
 	| f30[01]-* | f700-* | fido-* | fr30-* | frv-* | fx80-* \
 	| h8300-* | h8500-* \
 	| hppa-* | hppa1.[01]-* | hppa2.0-* | hppa2.0[nw]-* | hppa64-* \
+	| hexagon-* \
 	| i*86-* | i860-* | i960-* | ia64-* \
 	| ip2k-* | iq2000-* \
+	| k1om-* \
+	| le32-* | le64-* \
 	| lm32-* \
 	| m32c-* | m32r-* | m32rle-* \
 	| m68000-* | m680[012346]0-* | m68360-* | m683?2-* | m68k-* \
 	| m88110-* | m88k-* | maxq-* | mcore-* | metag-* \
+	| microblaze-* | microblazeel-* \
 	| mips-* | mipsbe-* | mipseb-* | mipsel-* | mipsle-* \
 	| mips16-* \
 	| mips64-* | mips64el-* \
@@ -351,32 +408,42 @@ case $basic_machine in
 	| mips64vr5900-* | mips64vr5900el-* \
 	| mipsisa32-* | mipsisa32el-* \
 	| mipsisa32r2-* | mipsisa32r2el-* \
+	| mipsisa32r6-* | mipsisa32r6el-* \
 	| mipsisa64-* | mipsisa64el-* \
 	| mipsisa64r2-* | mipsisa64r2el-* \
+	| mipsisa64r6-* | mipsisa64r6el-* \
 	| mipsisa64sb1-* | mipsisa64sb1el-* \
 	| mipsisa64sr71k-* | mipsisa64sr71kel-* \
+	| mipsr5900-* | mipsr5900el-* \
 	| mipstx39-* | mipstx39el-* \
 	| mmix-* \
 	| mt-* \
 	| msp430-* \
-	| nios-* | nios2-* \
+	| nds32-* | nds32le-* | nds32be-* \
+	| nios-* | nios2-* | nios2eb-* | nios2el-* \
 	| none-* | np1-* | ns16k-* | ns32k-* \
+	| open8-* \
+	| or1k*-* \
 	| orion-* \
 	| pdp10-* | pdp11-* | pj-* | pjl-* | pn-* | power-* \
-	| powerpc-* | powerpc64-* | powerpc64le-* | powerpcle-* | ppcbe-* \
+	| powerpc-* | powerpc64-* | powerpc64le-* | powerpcle-* \
 	| pyramid-* \
-	| romp-* | rs6000-* \
+	| rl78-* | romp-* | rs6000-* | rx-* \
 	| sh-* | sh[1234]-* | sh[24]a-* | sh[24]aeb-* | sh[23]e-* | sh[34]eb-* | sheb-* | shbe-* \
 	| shle-* | sh[1234]le-* | sh3ele-* | sh64-* | sh64le-* \
 	| sparc-* | sparc64-* | sparc64b-* | sparc64v-* | sparc86x-* | sparclet-* \
 	| sparclite-* \
-	| sparcv8-* | sparcv9-* | sparcv9b-* | sparcv9v-* | strongarm-* | sv1-* | sx?-* \
-	| tahoe-* | thumb-* \
-	| tic30-* | tic4x-* | tic54x-* | tic55x-* | tic6x-* | tic80-* | tile-* \
+	| sparcv8-* | sparcv9-* | sparcv9b-* | sparcv9v-* | sv1-* | sx?-* \
+	| tahoe-* \
+	| tic30-* | tic4x-* | tic54x-* | tic55x-* | tic6x-* | tic80-* \
+	| tile*-* \
 	| tron-* \
-	| v850-* | v850e-* | vax-* \
+	| ubicom32-* \
+	| v850-* | v850e-* | v850e1-* | v850es-* | v850e2-* | v850e2v3-* \
+	| vax-* \
+	| visium-* \
 	| we32k-* \
-	| x86-* | x86_64-* | xc16x-* | xps100-* | xscale-* | xscalee[bl]-* \
+	| x86-* | x86_64-* | xc16x-* | xps100-* \
 	| xstormy16-* | xtensa*-* \
 	| ymp-* \
 	| z8k-* | z80-*)
@@ -401,7 +468,7 @@ case $basic_machine in
 		basic_machine=a29k-amd
 		os=-udi
 		;;
-    	abacus)
+	abacus)
 		basic_machine=abacus-unknown
 		;;
 	adobe68k)
@@ -451,6 +518,9 @@ case $basic_machine in
 		basic_machine=i386-pc
 		os=-aros
 		;;
+        asmjs)
+		basic_machine=asmjs-unknown
+		;;
 	aux)
 		basic_machine=m68k-apple
 		os=-aux
@@ -467,11 +537,24 @@ case $basic_machine in
 		basic_machine=bfin-`echo $basic_machine | sed 's/^[^-]*-//'`
 		os=-linux
 		;;
+	bluegene*)
+		basic_machine=powerpc-ibm
+		os=-cnk
+		;;
+	c54x-*)
+		basic_machine=tic54x-`echo $basic_machine | sed 's/^[^-]*-//'`
+		;;
+	c55x-*)
+		basic_machine=tic55x-`echo $basic_machine | sed 's/^[^-]*-//'`
+		;;
+	c6x-*)
+		basic_machine=tic6x-`echo $basic_machine | sed 's/^[^-]*-//'`
+		;;
 	c90)
 		basic_machine=c90-cray
 		os=-unicos
 		;;
-        cegcc)
+	cegcc)
 		basic_machine=arm-unknown
 		os=-cegcc
 		;;
@@ -503,7 +586,7 @@ case $basic_machine in
 		basic_machine=craynv-cray
 		os=-unicosmp
 		;;
-	cr16)
+	cr16 | cr16-*)
 		basic_machine=cr16-unknown
 		os=-elf
 		;;
@@ -661,7 +744,6 @@ case $basic_machine in
 	i370-ibm* | ibm*)
 		basic_machine=i370-ibm
 		;;
-# I'm not sure what "Sysv32" means.  Should this be sysv3.2?
 	i*86v32)
 		basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'`
 		os=-sysv32
@@ -700,6 +782,9 @@ case $basic_machine in
 		basic_machine=m68k-isi
 		os=-sysv
 		;;
+	leon-*|leon[3-9]-*)
+		basic_machine=sparc-`echo $basic_machine | sed 's/-.*//'`
+		;;
 	m68knommu)
 		basic_machine=m68k-unknown
 		os=-linux
@@ -719,8 +804,15 @@ case $basic_machine in
 		basic_machine=ns32k-utek
 		os=-sysv
 		;;
+	microblaze*)
+		basic_machine=microblaze-xilinx
+		;;
+	mingw64)
+		basic_machine=x86_64-pc
+		os=-mingw64
+		;;
 	mingw32)
-		basic_machine=i386-pc
+		basic_machine=i686-pc
 		os=-mingw32
 		;;
 	mingw32ce)
@@ -748,6 +840,10 @@ case $basic_machine in
 		basic_machine=powerpc-unknown
 		os=-morphos
 		;;
+	moxiebox)
+		basic_machine=moxie-unknown
+		os=-moxiebox
+		;;
 	msdos)
 		basic_machine=i386-pc
 		os=-msdos
@@ -755,10 +851,18 @@ case $basic_machine in
 	ms1-*)
 		basic_machine=`echo $basic_machine | sed -e 's/ms1-/mt-/'`
 		;;
+	msys)
+		basic_machine=i686-pc
+		os=-msys
+		;;
 	mvs)
 		basic_machine=i370-ibm
 		os=-mvs
 		;;
+	nacl)
+		basic_machine=le32-unknown
+		os=-nacl
+		;;
 	ncr3000)
 		basic_machine=i486-ncr
 		os=-sysv4
@@ -823,6 +927,12 @@ case $basic_machine in
 	np1)
 		basic_machine=np1-gould
 		;;
+	neo-tandem)
+		basic_machine=neo-tandem
+		;;
+	nse-tandem)
+		basic_machine=nse-tandem
+		;;
 	nsr-tandem)
 		basic_machine=nsr-tandem
 		;;
@@ -905,9 +1015,10 @@ case $basic_machine in
 		;;
 	power)	basic_machine=power-ibm
 		;;
-	ppc)	basic_machine=powerpc-unknown
+	ppc | ppcbe)	basic_machine=powerpc-unknown
 		;;
-	ppc-*)	basic_machine=powerpc-`echo $basic_machine | sed 's/^[^-]*-//'`
+	ppc-* | ppcbe-*)
+		basic_machine=powerpc-`echo $basic_machine | sed 's/^[^-]*-//'`
 		;;
 	ppcle | powerpclittle | ppc-le | powerpc-little)
 		basic_machine=powerpcle-unknown
@@ -932,7 +1043,11 @@ case $basic_machine in
 		basic_machine=i586-unknown
 		os=-pw32
 		;;
-	rdos)
+	rdos | rdos64)
+		basic_machine=x86_64-pc
+		os=-rdos
+		;;
+	rdos32)
 		basic_machine=i386-pc
 		os=-rdos
 		;;
@@ -1001,6 +1116,9 @@ case $basic_machine in
 		basic_machine=i860-stratus
 		os=-sysv4
 		;;
+	strongarm-* | thumb-*)
+		basic_machine=arm-`echo $basic_machine | sed 's/^[^-]*-//'`
+		;;
 	sun2)
 		basic_machine=m68000-sun
 		;;
@@ -1057,20 +1175,8 @@ case $basic_machine in
 		basic_machine=t90-cray
 		os=-unicos
 		;;
-	tic54x | c54x*)
-		basic_machine=tic54x-unknown
-		os=-coff
-		;;
-	tic55x | c55x*)
-		basic_machine=tic55x-unknown
-		os=-coff
-		;;
-	tic6x | c6x*)
-		basic_machine=tic6x-unknown
-		os=-coff
-		;;
 	tile*)
-		basic_machine=tile-unknown
+		basic_machine=$basic_machine-unknown
 		os=-linux-gnu
 		;;
 	tx39)
@@ -1140,6 +1246,9 @@ case $basic_machine in
 	xps | xps100)
 		basic_machine=xps100-honeywell
 		;;
+	xscale-* | xscalee[bl]-*)
+		basic_machine=`echo $basic_machine | sed 's/^xscale/arm/'`
+		;;
 	ymp)
 		basic_machine=ymp-cray
 		os=-unicos
@@ -1237,9 +1346,12 @@ esac
 if [ x"$os" != x"" ]
 then
 case $os in
-        # First match some system type aliases
-        # that might get confused with valid system types.
+	# First match some system type aliases
+	# that might get confused with valid system types.
 	# -solaris* is a basic system type, with this one exception.
+	-auroraux)
+		os=-auroraux
+		;;
 	-solaris1 | -solaris1.*)
 		os=`echo $os | sed -e 's|solaris1|sunos4|'`
 		;;
@@ -1260,30 +1372,31 @@ case $os in
 	# Each alternative MUST END IN A *, to match a version number.
 	# -sysv* is not here because it comes later, after sysvr4.
 	-gnu* | -bsd* | -mach* | -minix* | -genix* | -ultrix* | -irix* \
-	      | -*vms* | -sco* | -esix* | -isc* | -aix* | -sunos | -sunos[34]*\
-	      | -hpux* | -unos* | -osf* | -luna* | -dgux* | -solaris* | -sym* \
-	      | -kopensolaris* \
+	      | -*vms* | -sco* | -esix* | -isc* | -aix* | -cnk* | -sunos | -sunos[34]*\
+	      | -hpux* | -unos* | -osf* | -luna* | -dgux* | -auroraux* | -solaris* \
+	      | -sym* | -kopensolaris* | -plan9* \
 	      | -amigaos* | -amigados* | -msdos* | -newsos* | -unicos* | -aof* \
-	      | -aos* | -aros* \
+	      | -aos* | -aros* | -cloudabi* \
 	      | -nindy* | -vxsim* | -vxworks* | -ebmon* | -hms* | -mvs* \
 	      | -clix* | -riscos* | -uniplus* | -iris* | -rtu* | -xenix* \
 	      | -hiux* | -386bsd* | -knetbsd* | -mirbsd* | -netbsd* \
-	      | -openbsd* | -solidbsd* \
+	      | -bitrig* | -openbsd* | -solidbsd* \
 	      | -ekkobsd* | -kfreebsd* | -freebsd* | -riscix* | -lynxos* \
 	      | -bosx* | -nextstep* | -cxux* | -aout* | -elf* | -oabi* \
 	      | -ptx* | -coff* | -ecoff* | -winnt* | -domain* | -vsta* \
 	      | -udi* | -eabi* | -lites* | -ieee* | -go32* | -aux* \
 	      | -chorusos* | -chorusrdb* | -cegcc* \
-	      | -cygwin* | -pe* | -psos* | -moss* | -proelf* | -rtems* \
-	      | -mingw32* | -linux-gnu* | -linux-newlib* | -linux-uclibc* \
-	      | -uxpv* | -beos* | -mpeix* | -udk* \
+	      | -cygwin* | -msys* | -pe* | -psos* | -moss* | -proelf* | -rtems* \
+	      | -mingw32* | -mingw64* | -linux-gnu* | -linux-android* \
+	      | -linux-newlib* | -linux-musl* | -linux-uclibc* \
+	      | -uxpv* | -beos* | -mpeix* | -udk* | -moxiebox* \
 	      | -interix* | -uwin* | -mks* | -rhapsody* | -darwin* | -opened* \
 	      | -openstep* | -oskit* | -conix* | -pw32* | -nonstopux* \
 	      | -storm-chaos* | -tops10* | -tenex* | -tops20* | -its* \
 	      | -os2* | -vos* | -palmos* | -uclinux* | -nucleus* \
 	      | -morphos* | -superux* | -rtmk* | -rtmk-nova* | -windiss* \
 	      | -powermax* | -dnix* | -nx6 | -nx7 | -sei* | -dragonfly* \
-	      | -skyos* | -haiku* | -rdos* | -toppers* | -drops*)
+	      | -skyos* | -haiku* | -rdos* | -toppers* | -drops* | -es* | -tirtos*)
 	# Remember, each alternative MUST END IN *, to match a version number.
 		;;
 	-qnx*)
@@ -1322,7 +1435,7 @@ case $os in
 	-opened*)
 		os=-openedition
 		;;
-        -os400*)
+	-os400*)
 		os=-os400
 		;;
 	-wince*)
@@ -1371,7 +1484,7 @@ case $os in
 	-sinix*)
 		os=-sysv4
 		;;
-        -tpf*)
+	-tpf*)
 		os=-tpf
 		;;
 	-triton*)
@@ -1407,15 +1520,14 @@ case $os in
 	-aros*)
 		os=-aros
 		;;
-	-kaos*)
-		os=-kaos
-		;;
 	-zvmoe)
 		os=-zvmoe
 		;;
 	-dicos*)
 		os=-dicos
 		;;
+	-nacl*)
+		;;
 	-none)
 		;;
 	*)
@@ -1438,10 +1550,10 @@ else
 # system, and we'll never get to this point.
 
 case $basic_machine in
-        score-*)
+	score-*)
 		os=-elf
 		;;
-        spu-*)
+	spu-*)
 		os=-elf
 		;;
 	*-acorn)
@@ -1453,8 +1565,23 @@ case $basic_machine in
 	arm*-semi)
 		os=-aout
 		;;
-        c4x-* | tic4x-*)
-        	os=-coff
+	c4x-* | tic4x-*)
+		os=-coff
+		;;
+	c8051-*)
+		os=-elf
+		;;
+	hexagon-*)
+		os=-elf
+		;;
+	tic54x-*)
+		os=-coff
+		;;
+	tic55x-*)
+		os=-coff
+		;;
+	tic6x-*)
+		os=-coff
 		;;
 	# This must come before the *-dec entry.
 	pdp10-*)
@@ -1474,14 +1601,11 @@ case $basic_machine in
 		;;
 	m68000-sun)
 		os=-sunos3
-		# This also exists in the configure program, but was not the
-		# default.
-		# os=-sunos4
 		;;
 	m68*-cisco)
 		os=-aout
 		;;
-        mep-*)
+	mep-*)
 		os=-elf
 		;;
 	mips*-cisco)
@@ -1508,7 +1632,7 @@ case $basic_machine in
 	*-ibm)
 		os=-aix
 		;;
-    	*-knuth)
+	*-knuth)
 		os=-mmixware
 		;;
 	*-wec)
@@ -1613,7 +1737,7 @@ case $basic_machine in
 			-sunos*)
 				vendor=sun
 				;;
-			-aix*)
+			-cnk*|-aix*)
 				vendor=ibm
 				;;
 			-beos*)

configure.ac

@@ -1,21 +1,22 @@
 dnl Process this file with autoconf to produce a configure script.
-AC_INIT(netlist.h)
-AC_CONFIG_HEADER(config.h)
-AC_CONFIG_HEADER(_pli_types.h)
-AC_CONFIG_HEADER(vhdlpp/vhdlpp_config.h)
-AC_CONFIG_HEADER(vvp/config.h)
-AC_CONFIG_HEADER(vpi/vpi_config.h)
-AC_CONFIG_HEADER(libveriuser/config.h)
-AC_CONFIG_HEADER(tgt-vvp/vvp_config.h)
-AC_CONFIG_HEADER(tgt-vhdl/vhdl_config.h)
-AC_CONFIG_HEADER(tgt-pcb/pcb_config.h)
+AC_INIT
+AC_CONFIG_SRCDIR([netlist.h])
+AC_CONFIG_HEADERS([config.h])
+AC_CONFIG_HEADERS([_pli_types.h])
+AC_CONFIG_HEADERS([vhdlpp/vhdlpp_config.h])
+AC_CONFIG_HEADERS([vvp/config.h])
+AC_CONFIG_HEADERS([vpi/vpi_config.h])
+AC_CONFIG_HEADERS([libveriuser/config.h])
+AC_CONFIG_HEADERS([tgt-vvp/vvp_config.h])
+AC_CONFIG_HEADERS([tgt-vhdl/vhdl_config.h])
+AC_CONFIG_HEADERS([tgt-pcb/pcb_config.h])
 
 AC_CANONICAL_HOST
 dnl Checks for programs.
 AC_PROG_CC
-# AC_PROG_CC_C99 is only available in autoconf version 2.60 and later.
-AC_PREREQ([2.60])
-AC_PROG_CC_C99
+AX_PROG_CC_FOR_BUILD
+AC_PREREQ([2.62])
+m4_version_prereq([2.70], [], [AC_PROG_CC_C99])
 AC_PROG_CXX
 AC_PROG_RANLIB
 AC_CHECK_TOOL(LD, ld, false)
@@ -54,6 +55,10 @@ then
         exit 1
 fi
 
+if test "x$NM" = "x"; then
+	NM=nm
+fi
+
 AC_EXEEXT
 AC_SUBST(EXEEXT)
 
@@ -82,13 +87,13 @@ CFLAGS="$iverilog_temp_cflags"
 
 AC_SUBST(DEPENDENCY_FLAG, [-MD])
 AC_SUBST(WARNING_FLAGS, ["-Wall $iverilog_wextra_flag -Wshadow"])
-AC_SUBST(WARNING_FLAGS_CC, [""])
+AC_SUBST(WARNING_FLAGS_CC, ["-Wstrict-prototypes"])
 AC_SUBST(WARNING_FLAGS_CXX, [""])
 fi
 
 AC_LANG(C++)
 
-AC_ARG_WITH([m32], [AC_HELP_STRING([--with-m32], [Compile 32-bit on x86_64])],
+AC_ARG_WITH([m32], [AS_HELP_STRING([--with-m32],[Compile 32-bit on x86_64])],
             [ with_m32=yes ],[ with_m32=no ])
 
 AS_IF( [test "x$with_m32" = xyes],
@@ -131,11 +136,18 @@ CXXFLAGS="$iverilog_temp_cxxflags"
 AC_CHECK_SIZEOF(unsigned long long)
 AC_CHECK_SIZEOF(unsigned long)
 AC_CHECK_SIZEOF(unsigned)
+AC_CHECK_SIZEOF(void *)
 
 # vvp uses these...
 AC_CHECK_LIB(termcap, tputs)
 AC_CHECK_LIB(readline, readline)
+AC_CHECK_LIB(readline, add_history, NEED_LIBHISTORY=no, NEED_LIBHISTORY=yes)
+if test "$NEED_LIBHISTORY" = "yes"; then
 AC_CHECK_LIB(history, add_history)
+else
+# libreadline includes libhistory functions
+AC_DEFINE(HAVE_LIBHISTORY, 1)
+fi
 AC_CHECK_HEADERS(readline/readline.h readline/history.h sys/resource.h)
 case "${host}" in *linux*) AC_DEFINE([LINUX], [1], [Host operating system is Linux.]) ;; esac
 
@@ -159,8 +171,7 @@ AC_FUNC_ALLOCA
 AC_FUNC_FSEEKO
 
 # valgrind checks
-AC_ARG_WITH([valgrind], [AC_HELP_STRING([--with-valgrind],
-                                        [Add valgrind hooks])],
+AC_ARG_WITH([valgrind], [AS_HELP_STRING([--with-valgrind],[Add valgrind hooks])],
             [], [check_valgrind=yes])
 
 AS_IF([test "x$check_valgrind" = xyes],
@@ -171,14 +182,11 @@ AS_IF([test "x$check_valgrind" = xyes],
                        [AC_MSG_ERROR([Could not find <valgrind/memcheck.h>])])])
 
 AC_MSG_CHECKING(for sys/times)
-AC_TRY_LINK(
-#include <unistd.h>
+AC_LINK_IFELSE([AC_LANG_PROGRAM([[#include <unistd.h>
 #include <sys/times.h>
-,{clock_t a = times(0)/sysconf(_SC_CLK_TCK);},
-do_times=yes
-AC_DEFINE([HAVE_TIMES], [1], [The times system call is available in the host operating system.]),
-do_times=no
-)
+]], [[{clock_t a = times(0)/sysconf(_SC_CLK_TCK);}]])],[do_times=yes
+AC_DEFINE(HAVE_TIMES, 1, The times system call is available in the host operating system.)],[do_times=no
+])
 AC_MSG_RESULT($do_times)
 
 # --
@@ -223,6 +231,10 @@ case "${host}" in
 	CPPFLAGS="-mieee $CPPFLAGS"
 	CFLAGS="-mieee $CFLAGS"
 	;;
+    *-*-mingw*)
+	CXXFLAGS="-D__USE_MINGW_ANSI_STDIO=1 $CXXFLAGS"
+	CFLAGS="-D__USE_MINGW_ANSI_STDIO=1 $CFLAGS"
+	;;
 esac
 
 # Do some more operating system specific setup. We put the file64_support
@@ -238,13 +250,17 @@ case "${host}" in
 esac
 AC_SUBST(file64_support)
 
+# fstapi.c (from GTKWave) needs this define.
+AC_CHECK_FUNCS(realpath)
+
 # Check that these functions exist. They are mostly C99
 # functions that older compilers may not yet support.
 AC_CHECK_FUNCS(fopen64)
 # The following math functions may be defined in the math library so look
 # in the default libraries first and then look in -lm for them. On some
 # systems we may need to use the compiler in C99 mode to get a definition.
-# We requested C99 mode earlier with AC_PROG_CC_C99.
+# autoconf >= 2.70 will enable C99 if it is available. For older autoconf
+# versions, we requested C99 mode earlier with AC_PROG_CC_C99.
 AC_SEARCH_LIBS([lround], [m], [AC_DEFINE([HAVE_LROUND], [1])])
 AC_SEARCH_LIBS([llround], [m], [AC_DEFINE([HAVE_LLROUND], [1])])
 AC_SEARCH_LIBS([nan], [m], [AC_DEFINE([HAVE_NAN], [1])])
@@ -318,5 +334,5 @@ then
 AC_MSG_ERROR(cannot configure white space in libdir: $libdir)
 fi
 AC_MSG_RESULT(ok)
-
-AC_OUTPUT(Makefile ivlpp/Makefile vhdlpp/Makefile vvp/Makefile vpi/Makefile driver/Makefile driver-vpi/Makefile cadpli/Makefile libveriuser/Makefile tgt-null/Makefile tgt-stub/Makefile tgt-vvp/Makefile tgt-vhdl/Makefile tgt-fpga/Makefile tgt-verilog/Makefile tgt-pal/Makefile tgt-vlog95/Makefile tgt-pcb/Makefile tgt-blif/Makefile tgt-sizer/Makefile)
+AC_CONFIG_FILES([Makefile ivlpp/Makefile vhdlpp/Makefile vvp/Makefile vpi/Makefile driver/Makefile driver-vpi/Makefile cadpli/Makefile libveriuser/Makefile tgt-null/Makefile tgt-stub/Makefile tgt-vvp/Makefile tgt-vhdl/Makefile tgt-fpga/Makefile tgt-verilog/Makefile tgt-pal/Makefile tgt-vlog95/Makefile tgt-pcb/Makefile tgt-blif/Makefile tgt-sizer/Makefile])
+AC_OUTPUT

cppcheck.sup

@@ -1,3 +1,619 @@
 // These are correct and are used to find the base (zero) pin.
-thisSubtraction:netlist.h:4938
-thisSubtraction:netlist.h:4947
+thisSubtraction:netlist.h:5126
+thisSubtraction:netlist.h:5135
+
+// These are the functions that the compiler exports to the targets.
+//ivl_branch_island()
+unusedFunction:t-dll-api.cc:39
+//ivl_branch_terminal()
+unusedFunction:t-dll-api.cc:45
+
+//ivl_const_bits()
+unusedFunction:t-dll-api.cc:196
+//ivl_const_delay()
+unusedFunction:t-dll-api.cc:214
+//ivl_const_file()
+unusedFunction:t-dll-api.cc:221
+//ivl_const_lineno()
+unusedFunction:t-dll-api.cc:227
+//ivl_const_nex()
+unusedFunction:t-dll-api.cc:233
+//ivl_const_real()
+unusedFunction:t-dll-api.cc:239
+//ivl_const_scope()
+unusedFunction:t-dll-api.cc:246
+//ivl_const_signed()
+unusedFunction:t-dll-api.cc:252
+//ivl_const_type()
+unusedFunction:t-dll-api.cc:190
+//ivl_const_width()
+unusedFunction:t-dll-api.cc:258
+
+//ivl_design_const()
+unusedFunction:t-dll-api.cc:127
+//ivl_design_consts()
+unusedFunction:t-dll-api.cc:121
+//ivl_design_delay_sel()
+unusedFunction:t-dll-api.cc:52
+//ivl_design_discipline()
+unusedFunction:t-dll-api.cc:140
+//ivl_design_disciplines()
+unusedFunction:t-dll-api.cc:134
+//ivl_design_flag()
+unusedFunction:t-dll-api.cc:59
+//ivl_design_process()
+unusedFunction:t-dll-api.cc:66
+//ivl_design_root()
+unusedFunction:t-dll-api.cc:80
+//ivl_design_roots()
+unusedFunction:t-dll-api.cc:89
+//ivl_design_time_precision()
+unusedFunction:t-dll-api.cc:115
+
+//ivl_discipline_domain()
+unusedFunction:t-dll-api.cc:147
+//ivl_discipline_flow()
+unusedFunction:t-dll-api.cc:153
+//ivl_discipline_name()
+unusedFunction:t-dll-api.cc:159
+//ivl_discipline_potential()
+unusedFunction:t-dll-api.cc:165
+
+//ivl_enum_bits()
+unusedFunction:t-dll-api.cc:277
+//ivl_enum_file()
+unusedFunction:t-dll-api.cc:302
+//ivl_enum_lineno()
+unusedFunction:t-dll-api.cc:308
+//ivl_enum_name()
+unusedFunction:t-dll-api.cc:270
+//ivl_enum_names()
+unusedFunction:t-dll-api.cc:264
+//ivl_enum_signed()
+unusedFunction:t-dll-api.cc:296
+//ivl_enum_type()
+unusedFunction:t-dll-api.cc:284
+//ivl_enum_width()
+unusedFunction:t-dll-api.cc:290
+
+//ivl_event_any()
+unusedFunction:t-dll-api.cc:369
+//ivl_event_file()
+unusedFunction:t-dll-api.cc:345
+//ivl_event_lineno()
+unusedFunction:t-dll-api.cc:351
+//ivl_event_name()
+unusedFunction:t-dll-api.cc:314
+//ivl_event_nany()
+unusedFunction:t-dll-api.cc:363
+//ivl_event_neg()
+unusedFunction:t-dll-api.cc:382
+//ivl_event_nneg()
+unusedFunction:t-dll-api.cc:376
+//ivl_event_npos()
+unusedFunction:t-dll-api.cc:389
+//ivl_event_pos()
+unusedFunction:t-dll-api.cc:395
+//ivl_event_scope()
+unusedFunction:t-dll-api.cc:357
+
+//ivl_expr_bits()
+unusedFunction:t-dll-api.cc:402
+//ivl_expr_branch()
+unusedFunction:t-dll-api.cc:409
+//ivl_expr_def()
+unusedFunction:t-dll-api.cc:416
+//ivl_expr_delay_val()
+unusedFunction:t-dll-api.cc:432
+//ivl_expr_dvalue()
+unusedFunction:t-dll-api.cc:439
+//ivl_expr_enumtype()
+unusedFunction:t-dll-api.cc:446
+//ivl_expr_event()
+unusedFunction:t-dll-api.cc:656
+//ivl_expr_file()
+unusedFunction:t-dll-api.cc:178
+//ivl_expr_lineno()
+unusedFunction:t-dll-api.cc:184
+//ivl_expr_name()
+unusedFunction:t-dll-api.cc:459
+//ivl_expr_nature()
+unusedFunction:t-dll-api.cc:483
+//ivl_expr_net_type()
+unusedFunction:t-dll-api.cc:453
+//ivl_expr_opcode()
+unusedFunction:t-dll-api.cc:490
+//ivl_expr_oper1()
+unusedFunction:t-dll-api.cc:506
+//ivl_expr_oper2()
+unusedFunction:t-dll-api.cc:544
+//ivl_expr_oper3()
+unusedFunction:t-dll-api.cc:570
+//ivl_expr_parameter()
+unusedFunction:t-dll-api.cc:584
+//ivl_expr_parm()
+unusedFunction:t-dll-api.cc:599
+//ivl_expr_parms()
+unusedFunction:t-dll-api.cc:626
+//ivl_expr_repeat()
+unusedFunction:t-dll-api.cc:649
+//ivl_expr_scope()
+unusedFunction:t-dll-api.cc:670
+//ivl_expr_sel_type()
+unusedFunction:t-dll-api.cc:677
+//ivl_expr_signed()
+unusedFunction:t-dll-api.cc:702
+//ivl_expr_sized()
+unusedFunction:t-dll-api.cc:708
+//ivl_expr_string()
+unusedFunction:t-dll-api.cc:714
+//ivl_expr_type()
+unusedFunction:t-dll-api.cc:171
+//ivl_expr_uvalue()
+unusedFunction:t-dll-api.cc:721
+//ivl_expr_value()
+unusedFunction:t-dll-api.cc:747
+//ivl_expr_width()
+unusedFunction:t-dll-api.cc:753
+
+//ivl_file_table_index()
+unusedFunction:t-dll-api.cc:795
+//ivl_file_table_item()
+unusedFunction:t-dll-api.cc:785
+//ivl_file_table_size()
+unusedFunction:t-dll-api.cc:813
+
+//ivl_island_flag_set()
+unusedFunction:t-dll-api.cc:822
+//ivl_island_flag_test()
+unusedFunction:t-dll-api.cc:837
+
+//ivl_logic_attr()
+unusedFunction:t-dll-api.cc:864
+//ivl_logic_attr_cnt()
+unusedFunction:t-dll-api.cc:880
+//ivl_logic_attr_val()
+unusedFunction:t-dll-api.cc:886
+//ivl_logic_basename()
+unusedFunction:t-dll-api.cc:935
+//ivl_logic_delay()
+unusedFunction:t-dll-api.cc:974
+//ivl_logic_drive0()
+unusedFunction:t-dll-api.cc:894
+//ivl_logic_drive1()
+unusedFunction:t-dll-api.cc:911
+//ivl_logic_file()
+unusedFunction:t-dll-api.cc:846
+//ivl_logic_is_cassign()
+unusedFunction:t-dll-api.cc:858
+//ivl_logic_lineno()
+unusedFunction:t-dll-api.cc:852
+//ivl_logic_name()
+unusedFunction:t-dll-api.cc:928
+//ivl_logic_pins()
+unusedFunction:t-dll-api.cc:953
+//ivl_logic_scope()
+unusedFunction:t-dll-api.cc:941
+//ivl_logic_type()
+unusedFunction:t-dll-api.cc:947
+//ivl_logic_udp()
+unusedFunction:t-dll-api.cc:966
+//ivl_logic_width()
+unusedFunction:t-dll-api.cc:981
+
+//ivl_lpm_array()
+unusedFunction:t-dll-api.cc:1109
+//ivl_lpm_aset_value()
+unusedFunction:t-dll-api.cc:1160
+//ivl_lpm_async_clr()
+unusedFunction:t-dll-api.cc:1054
+//ivl_lpm_async_set()
+unusedFunction:t-dll-api.cc:1085
+//ivl_lpm_base()
+unusedFunction:t-dll-api.cc:1121
+//ivl_lpm_basename()
+unusedFunction:t-dll-api.cc:1048
+//ivl_lpm_clk()
+unusedFunction:t-dll-api.cc:1148
+//ivl_lpm_data()
+unusedFunction:t-dll-api.cc:1221
+//ivl_lpm_datab()
+unusedFunction:t-dll-api.cc:1321
+//ivl_lpm_define()
+unusedFunction:t-dll-api.cc:1183
+//ivl_lpm_delay()
+unusedFunction:t-dll-api.cc:1078
+//ivl_lpm_drive0()
+unusedFunction:t-dll-api.cc:1453
+//ivl_lpm_drive1()
+unusedFunction:t-dll-api.cc:1470
+//ivl_lpm_enable()
+unusedFunction:t-dll-api.cc:1195
+//ivl_lpm_file()
+unusedFunction:t-dll-api.cc:1209
+//ivl_lpm_lineno()
+unusedFunction:t-dll-api.cc:1215
+//ivl_lpm_name()
+unusedFunction:t-dll-api.cc:1355
+//ivl_lpm_negedge()
+unusedFunction:t-dll-api.cc:1136
+//ivl_lpm_select()
+unusedFunction:t-dll-api.cc:1493
+//ivl_lpm_selects()
+unusedFunction:t-dll-api.cc:1510
+//ivl_lpm_signed()
+unusedFunction:t-dll-api.cc:1528
+//ivl_lpm_size()
+unusedFunction:t-dll-api.cc:1587
+//ivl_lpm_sset_value()
+unusedFunction:t-dll-api.cc:1171
+//ivl_lpm_string()
+unusedFunction:t-dll-api.cc:1640
+//ivl_lpm_sync_clr()
+unusedFunction:t-dll-api.cc:1066
+//ivl_lpm_sync_set()
+unusedFunction:t-dll-api.cc:1097
+//ivl_lpm_trigger()
+unusedFunction:t-dll-api.cc:1659
+//ivl_lpm_type()
+unusedFunction:t-dll-api.cc:1647
+//ivl_lpm_width()
+unusedFunction:t-dll-api.cc:1653
+
+//ivl_lval_idx()
+unusedFunction:t-dll-api.cc:1681
+//ivl_lval_mux()
+unusedFunction:t-dll-api.cc:1676
+//ivl_lval_nest()
+unusedFunction:t-dll-api.cc:1726
+//ivl_lval_part_off()
+unusedFunction:t-dll-api.cc:1690
+//ivl_lval_property_idx()
+unusedFunction:t-dll-api.cc:1708
+//ivl_lval_sel_type()
+unusedFunction:t-dll-api.cc:1696
+//ivl_lval_sig()
+unusedFunction:t-dll-api.cc:1714
+
+//ivl_nature_name()
+unusedFunction:t-dll-api.cc:1735
+
+//ivl_nexus_get_private()
+unusedFunction:t-dll-api.cc:1756
+//ivl_nexus_name()
+unusedFunction:t-dll-api.cc:1745
+//ivl_nexus_ptr_branch()
+unusedFunction:t-dll-api.cc:1799
+//ivl_nexus_ptr_con()
+unusedFunction:t-dll-api.cc:1808
+//ivl_nexus_ptr_sig()
+unusedFunction:t-dll-api.cc:1835
+//ivl_nexus_ptr_switch()
+unusedFunction:t-dll-api.cc:1844
+//ivl_nexus_set_private()
+unusedFunction:t-dll-api.cc:1762
+
+//ivl_parameter_basename()
+unusedFunction:t-dll-api.cc:1853
+//ivl_parameter_expr()
+unusedFunction:t-dll-api.cc:1896
+//ivl_parameter_file()
+unusedFunction:t-dll-api.cc:1902
+//ivl_parameter_lineno()
+unusedFunction:t-dll-api.cc:1908
+//ivl_parameter_local()
+unusedFunction:t-dll-api.cc:1859
+//ivl_parameter_lsb()
+unusedFunction:t-dll-api.cc:1877
+//ivl_parameter_msb()
+unusedFunction:t-dll-api.cc:1871
+//ivl_parameter_scope()
+unusedFunction:t-dll-api.cc:1914
+//ivl_parameter_signed()
+unusedFunction:t-dll-api.cc:1865
+//ivl_parameter_width()
+unusedFunction:t-dll-api.cc:1887
+
+//ivl_path_condit()
+unusedFunction:t-dll-api.cc:1920
+//ivl_path_delay()
+unusedFunction:t-dll-api.cc:1932
+//ivl_path_is_condit()
+unusedFunction:t-dll-api.cc:1926
+//ivl_path_scope()
+unusedFunction:t-dll-api.cc:1938
+//ivl_path_source()
+unusedFunction:t-dll-api.cc:1945
+//ivl_path_source_negedge()
+unusedFunction:t-dll-api.cc:1957
+//ivl_path_source_posedge()
+unusedFunction:t-dll-api.cc:1951
+
+//ivl_process_analog()
+unusedFunction:t-dll-api.cc:1981
+//ivl_process_attr_cnt()
+unusedFunction:t-dll-api.cc:1999
+//ivl_process_attr_val()
+unusedFunction:t-dll-api.cc:2005
+//ivl_process_file()
+unusedFunction:t-dll-api.cc:1963
+//ivl_process_lineno()
+unusedFunction:t-dll-api.cc:1969
+//ivl_process_scope()
+unusedFunction:t-dll-api.cc:1987
+//ivl_process_stmt()
+unusedFunction:t-dll-api.cc:1993
+//ivl_process_type()
+unusedFunction:t-dll-api.cc:1975
+
+//ivl_scope_attr_cnt()
+unusedFunction:t-dll-api.cc:2013
+//ivl_scope_attr_val()
+unusedFunction:t-dll-api.cc:2019
+//ivl_scope_basename()
+unusedFunction:t-dll-api.cc:2027
+//ivl_scope_child()
+unusedFunction:t-dll-api.cc:2054
+//ivl_scope_children()
+unusedFunction:t-dll-api.cc:2033
+//ivl_scope_childs()
+unusedFunction:t-dll-api.cc:2047
+//ivl_scope_class()
+unusedFunction:t-dll-api.cc:2061
+//ivl_scope_classes()
+unusedFunction:t-dll-api.cc:2068
+//ivl_scope_def()
+unusedFunction:t-dll-api.cc:2075
+//ivl_scope_def_file()
+unusedFunction:t-dll-api.cc:2081
+//ivl_scope_def_lineno()
+unusedFunction:t-dll-api.cc:2087
+//ivl_scope_enumerate()
+unusedFunction:t-dll-api.cc:2099
+//ivl_scope_enumerates()
+unusedFunction:t-dll-api.cc:2093
+//ivl_scope_event()
+unusedFunction:t-dll-api.cc:2112
+//ivl_scope_events()
+unusedFunction:t-dll-api.cc:2106
+//ivl_scope_file()
+unusedFunction:t-dll-api.cc:2119
+//ivl_scope_func_signed
+unusedFunction:t-dll-api.cc:2132
+//ivl_scope_func_type
+unusedFunction:t-dll-api.cc:2125
+//ivl_scope_func_width
+unusedFunction:t-dll-api.cc:2140
+//ivl_scope_is_auto()
+unusedFunction:t-dll-api.cc:2148
+//ivl_scope_is_cell()
+unusedFunction:t-dll-api.cc:2154
+//ivl_scope_lineno()
+unusedFunction:t-dll-api.cc:2160
+//ivl_scope_log()
+unusedFunction:t-dll-api.cc:2172
+//ivl_scope_logs()
+unusedFunction:t-dll-api.cc:2166
+//ivl_scope_lpm()
+unusedFunction:t-dll-api.cc:2185
+//ivl_scope_lpms()
+unusedFunction:t-dll-api.cc:2179
+//ivl_scope_mod_module_port_name()
+unusedFunction:t-dll-api.cc:2264
+//ivl_scope_mod_module_port_type()
+unusedFunction:t-dll-api.cc:2273
+//ivl_scope_mod_module_port_width()
+unusedFunction:t-dll-api.cc:2285
+//ivl_scope_mod_module_ports()
+unusedFunction:t-dll-api.cc:2257
+//ivl_scope_mod_port()
+unusedFunction:t-dll-api.cc:2310
+//ivl_scope_param()
+unusedFunction:t-dll-api.cc:2243
+//ivl_scope_params()
+unusedFunction:t-dll-api.cc:2237
+//ivl_scope_parent()
+unusedFunction:t-dll-api.cc:2250
+//ivl_scope_port()
+unusedFunction:t-dll-api.cc:2301
+//ivl_scope_ports()
+unusedFunction:t-dll-api.cc:2292
+//ivl_scope_sig()
+unusedFunction:t-dll-api.cc:2324
+//ivl_scope_sigs()
+unusedFunction:t-dll-api.cc:2318
+//ivl_scope_switch()
+unusedFunction:t-dll-api.cc:2337
+//ivl_scope_switches()
+unusedFunction:t-dll-api.cc:2331
+//ivl_scope_time_precision()
+unusedFunction:t-dll-api.cc:2344
+//ivl_scope_time_units()
+unusedFunction:t-dll-api.cc:2350
+//ivl_scope_tname()
+unusedFunction:t-dll-api.cc:2362
+//ivl_scope_type()
+unusedFunction:t-dll-api.cc:2356
+
+//ivl_signal_array_addr_swapped()
+unusedFunction:t-dll-api.cc:2380
+//ivl_signal_array_base()
+unusedFunction:t-dll-api.cc:2368
+//ivl_signal_array_count()
+unusedFunction:t-dll-api.cc:2374
+//ivl_signal_attr()
+unusedFunction:t-dll-api.cc:2398
+//ivl_signal_attr_cnt()
+unusedFunction:t-dll-api.cc:2414
+//ivl_signal_attr_val()
+unusedFunction:t-dll-api.cc:2420
+//ivl_signal_basename()
+unusedFunction:t-dll-api.cc:2427
+//ivl_signal_data_type()
+unusedFunction:t-dll-api.cc:2578
+//ivl_signal_dimensions()
+unusedFunction:t-dll-api.cc:2386
+//ivl_signal_discipline()
+unusedFunction:t-dll-api.cc:2392
+//ivl_signal_file()
+unusedFunction:t-dll-api.cc:2555
+//ivl_signal_forced_net()
+unusedFunction:t-dll-api.cc:2549
+//ivl_signal_integer()
+unusedFunction:t-dll-api.cc:2567
+//ivl_signal_lineno()
+unusedFunction:t-dll-api.cc:2561
+//ivl_signal_local()
+unusedFunction:t-dll-api.cc:2536
+//ivl_signal_lsb()
+unusedFunction:t-dll-api.cc:2501
+//ivl_signal_module_port_index()
+unusedFunction:t-dll-api.cc:2530
+//ivl_signal_msb()
+unusedFunction:t-dll-api.cc:2491
+//ivl_signal_name()
+unusedFunction:t-dll-api.cc:2433
+//ivl_signal_nex()
+unusedFunction:t-dll-api.cc:2454
+//ivl_signal_npath()
+unusedFunction:t-dll-api.cc:2591
+//ivl_signal_packed_dimensions()
+unusedFunction:t-dll-api.cc:2471
+//ivl_signal_packed_lsb()
+unusedFunction:t-dll-api.cc:2484
+//ivl_signal_packed_msb()
+unusedFunction:t-dll-api.cc:2477
+//ivl_signal_path()
+unusedFunction:t-dll-api.cc:2597
+//ivl_signal_port()
+unusedFunction:t-dll-api.cc:2524
+//ivl_signal_scope()
+unusedFunction:t-dll-api.cc:2511
+//ivl_signal_signed()
+unusedFunction:t-dll-api.cc:2542
+//ivl_signal_width()
+unusedFunction:t-dll-api.cc:2517
+
+//ivl_statement_type()
+unusedFunction:t-dll-api.cc:2610
+
+//ivl_stmt_block_count()
+unusedFunction:t-dll-api.cc:2643
+//ivl_stmt_block_scope()
+unusedFunction:t-dll-api.cc:2628
+//ivl_stmt_block_stmt()
+unusedFunction:t-dll-api.cc:2658
+//ivl_stmt_call()
+unusedFunction:t-dll-api.cc:2674
+//ivl_stmt_case_count()
+unusedFunction:t-dll-api.cc:2695
+//ivl_stmt_case_expr()
+unusedFunction:t-dll-api.cc:2710
+//ivl_stmt_case_stmt()
+unusedFunction:t-dll-api.cc:2727
+//ivl_stmt_cond_expr()
+unusedFunction:t-dll-api.cc:2744
+//ivl_stmt_cond_false()
+unusedFunction:t-dll-api.cc:2771
+//ivl_stmt_cond_true()
+unusedFunction:t-dll-api.cc:2781
+//ivl_stmt_delay_expr()
+unusedFunction:t-dll-api.cc:2791
+//ivl_stmt_delay_val()
+unusedFunction:t-dll-api.cc:2808
+//ivl_stmt_events()
+unusedFunction:t-dll-api.cc:2834
+//ivl_stmt_file()
+unusedFunction:t-dll-api.cc:2616
+//ivl_stmt_lexp()
+unusedFunction:t-dll-api.cc:2862
+//ivl_stmt_lineno()
+unusedFunction:t-dll-api.cc:2622
+//ivl_stmt_lval()
+unusedFunction:t-dll-api.cc:2874
+//ivl_stmt_lvals()
+unusedFunction:t-dll-api.cc:2893
+//ivl_stmt_lwidth()
+unusedFunction:t-dll-api.cc:2911
+//ivl_stmt_name()
+unusedFunction:t-dll-api.cc:2944
+//ivl_stmt_nevent()
+unusedFunction:t-dll-api.cc:2815
+//ivl_stmt_opcode()
+unusedFunction:t-dll-api.cc:2957
+//ivl_stmt_parm()
+unusedFunction:t-dll-api.cc:2969
+//ivl_stmt_parm_count()
+unusedFunction:t-dll-api.cc:2983
+//ivl_stmt_rval()
+unusedFunction:t-dll-api.cc:2995
+//ivl_stmt_sfunc_as_task()
+unusedFunction:t-dll-api.cc:3013
+//ivl_stmt_sub_stmt()
+unusedFunction:t-dll-api.cc:3026
+
+//ivl_switch_a()
+unusedFunction:t-dll-api.cc:3067
+//ivl_switch_b()
+unusedFunction:t-dll-api.cc:3073
+//ivl_switch_basename()
+unusedFunction:t-dll-api.cc:3049
+//ivl_switch_delay()
+unusedFunction:t-dll-api.cc:3103
+//ivl_switch_enable()
+unusedFunction:t-dll-api.cc:3079
+//ivl_switch_file()
+unusedFunction:t-dll-api.cc:3110
+//ivl_switch_island()
+unusedFunction:t-dll-api.cc:3116
+//ivl_switch_lineno()
+unusedFunction:t-dll-api.cc:3122
+//ivl_switch_offset()
+unusedFunction:t-dll-api.cc:3097
+//ivl_switch_part()
+unusedFunction:t-dll-api.cc:3091
+//ivl_switch_scope()
+unusedFunction:t-dll-api.cc:3055
+//ivl_switch_type()
+unusedFunction:t-dll-api.cc:3061
+//ivl_switch_width()
+unusedFunction:t-dll-api.cc:3085
+
+//ivl_type_base()
+unusedFunction:t-dll-api.cc:3128
+//ivl_type_element()
+unusedFunction:t-dll-api.cc:3134
+//ivl_type_name()
+unusedFunction:t-dll-api.cc:3166
+//ivl_type_packed_dimensions()
+unusedFunction:t-dll-api.cc:3143
+//ivl_type_packed_lsb()
+unusedFunction:t-dll-api.cc:3150
+//ivl_type_packed_msb()
+unusedFunction:t-dll-api.cc:3158
+//ivl_type_prop_type()
+unusedFunction:t-dll-api.cc:3191
+//ivl_type_properties()
+unusedFunction:t-dll-api.cc:3174
+//ivl_type_signed()
+unusedFunction:t-dll-api.cc:3199
+
+//ivl_udp_file()
+unusedFunction:t-dll-api.cc:1036
+//ivl_udp_init()
+unusedFunction:t-dll-api.cc:999
+//ivl_udp_lineno()
+unusedFunction:t-dll-api.cc:1042
+//ivl_udp_name()
+unusedFunction:t-dll-api.cc:1029
+//ivl_udp_nin()
+unusedFunction:t-dll-api.cc:993
+//ivl_udp_port()
+unusedFunction:t-dll-api.cc:1005
+//ivl_udp_row()
+unusedFunction:t-dll-api.cc:1014
+//ivl_udp_rows()
+unusedFunction:t-dll-api.cc:1023
+// ivl_udp_sequ()
+unusedFunction:t-dll-api.cc:987
+

cprop.cc

@@ -28,6 +28,7 @@
 # include  "compiler.h"
 # include  "ivl_assert.h"
 
+using namespace std;
 
 /*
  * The cprop function below invokes constant propagation where

design_dump.cc

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1998-2014 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 1998-2020 Stephen Williams (steve@icarus.com)
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -35,6 +35,8 @@
 # include  "ivl_assert.h"
 # include  "PExpr.h"
 
+using namespace std;
+
 static ostream& operator<< (ostream&o, NetBlock::Type t)
 {
       switch (t) {
@@ -187,9 +189,15 @@ ostream& operator << (ostream&fd, NetCaseCmp::kind_t that)
 	  case NetCaseCmp::NEQ:
 	    fd << "!==";
 	    break;
-	  case NetCaseCmp::XEQ:
+	  case NetCaseCmp::WEQ:
 	    fd << "==?";
 	    break;
+	  case NetCaseCmp::WNE:
+	    fd << "!=?";
+	    break;
+	  case NetCaseCmp::XEQ:
+	    fd << "==x?";
+	    break;
 	  case NetCaseCmp::ZEQ:
 	    fd << "==z?";
 	    break;
@@ -226,13 +234,15 @@ ostream& netdarray_t::debug_dump(ostream&o) const
 
 ostream& netqueue_t::debug_dump(ostream&fd) const
 {
-      fd << "queue of " << *element_type();
+      fd << "queue of ";
+      if (max_idx_ >= 0) fd << "(maximum of " << max_idx_+1 << " elements) ";
+      fd << *element_type();
       return fd;
 }
 
 ostream& netvector_t::debug_dump(ostream&o) const
 {
-      o << type_ << (signed_? " signed" : " unsigned") << packed_dims_;
+      o << "netvector_t:" << type_ << (signed_? " signed" : " unsigned") << packed_dims_;
       return o;
 }
 
@@ -344,6 +354,10 @@ void NetDelaySrc::dump(ostream&o, unsigned ind) const
 	    if (has_condit()) o << " if";
 	    else o << " ifnone";
       }
+      if (parallel_)
+	    o << " parallel";
+      else
+	    o << " full";
       o << " src "
 	<< "(" << transition_delays_[IVL_PE_01]
 	<< "," << transition_delays_[IVL_PE_10]
@@ -677,13 +691,25 @@ void NetConst::dump_node(ostream&o, unsigned ind) const
 void NetFF::dump_node(ostream&o, unsigned ind) const
 {
       o << setw(ind) << "" << "LPM_FF: " << name()
-	<< " scope=" << scope_path(scope())
-	<< " aset_value=" << aset_value_ << endl;
+	<< " scope=" << scope_path(scope());
+      if (negedge_)
+	    o << " negedge";
+      else
+	    o << " posedge";
+      o << " aset_value=" << aset_value_ << endl;
 
       dump_node_pins(o, ind+4);
       dump_obj_attr(o, ind+4);
 }
 
+void NetLatch::dump_node(ostream&o, unsigned ind) const
+{
+      o << setw(ind) << "" << "LPM_LATCH: " << name()
+	<< " scope=" << scope_path(scope()) << endl;
+      dump_node_pins(o, ind+4);
+      dump_obj_attr(o, ind+4);
+}
+
 void NetLiteral::dump_node(ostream&o, unsigned ind) const
 {
       o << setw(ind) << "" << "constant real " << real_
@@ -717,6 +743,12 @@ void NetLogic::dump_node(ostream&o, unsigned ind) const
 	  case CMOS:
 	    o << "cmos";
 	    break;
+	  case EQUIV:
+	    o << "<->";
+	    break;
+	  case IMPL:
+	    o << "->";
+	    break;
 	  case NAND:
 	    o << "nand";
 	    break;
@@ -972,6 +1004,18 @@ void NetProcTop::dump(ostream&o, unsigned ind) const
 	    o << "always  /* " << get_fileline() << " in "
 	      << scope_path(scope_) << " */" << endl;
 	    break;
+	  case IVL_PR_ALWAYS_COMB:
+	    o << "always_comb  /* " << get_fileline() << " in "
+	      << scope_path(scope_) << " */" << endl;
+	    break;
+	  case IVL_PR_ALWAYS_FF:
+	    o << "always_ff  /* " << get_fileline() << " in "
+	      << scope_path(scope_) << " */" << endl;
+	    break;
+	  case IVL_PR_ALWAYS_LATCH:
+	    o << "always_latch  /* " << get_fileline() << " in "
+	      << scope_path(scope_) << " */" << endl;
+	    break;
 	  case IVL_PR_FINAL:
 	    o << "final  /* " << get_fileline() << " in "
 	      << scope_path(scope_) << " */" << endl;
@@ -999,6 +1043,13 @@ void NetAnalogTop::dump(ostream&o, unsigned ind) const
 	      << scope_path(scope_) << " */" << endl;
 	    break;
 
+	    // These are not used in an analog context.
+	  case IVL_PR_ALWAYS_COMB:
+	  case IVL_PR_ALWAYS_FF:
+	  case IVL_PR_ALWAYS_LATCH:
+	    assert(0);
+	    break;
+
 	  case IVL_PR_FINAL:
 	    o << "analog final /* " << get_fileline() << " in "
 	      << scope_path(scope_) << " */" << endl;
@@ -1016,7 +1067,11 @@ void NetAlloc::dump(ostream&o, unsigned ind) const
 void NetAssign_::dump_lval(ostream&o) const
 {
       if (sig_) o << sig_->name();
-      else if (nest_) nest_->dump_lval(o);
+      else if (nest_) {
+	    o << "(";
+	    nest_->dump_lval(o);
+	    o << ")";
+      }
       else o << "<?>";
 
       if (! member_.nil()) {
@@ -1109,15 +1164,29 @@ void NetBlock::dump(ostream&o, unsigned ind) const
 
 void NetCase::dump(ostream&o, unsigned ind) const
 {
+      o << setw(ind) << "";
+      switch (quality_) {
+	  case IVL_CASE_QUALITY_BASIC:
+	    break;
+	  case IVL_CASE_QUALITY_UNIQUE:
+	    o << "unique ";
+	    break;
+	  case IVL_CASE_QUALITY_UNIQUE0:
+	    o << "unique0 ";
+	    break;
+	  case IVL_CASE_QUALITY_PRIORITY:
+	    o << "priority ";
+	    break;
+      }
       switch (type_) {
 	  case EQ:
-	    o << setw(ind) << "" << "case (" << *expr_ << ")" << endl;
+	    o << "case (" << *expr_ << ")" << endl;
 	    break;
 	  case EQX:
-	    o << setw(ind) << "" << "casex (" << *expr_ << ")" << endl;
+	    o << "casex (" << *expr_ << ")" << endl;
 	    break;
 	  case EQZ:
-	    o << setw(ind) << "" << "casez (" << *expr_ << ")" << endl;
+	    o << "casez (" << *expr_ << ")" << endl;
 	    break;
       }
 
@@ -1375,8 +1444,11 @@ void NetScope::dump(ostream&o) const
       if (is_cell()) o << " (cell)";
       if (nested_module()) o << " (nested)";
       if (program_block()) o << " (program)";
+      if (is_interface()) o << " (interface)";
       o << " " << children_.size() << " children, "
 	<< classes_.size() << " classes" << endl;
+      if (unit() && !is_unit())
+	    o << "    in compilation unit " << unit()->basename() << endl;
 
       for (unsigned idx = 0 ;  idx < attr_cnt() ;  idx += 1)
 	    o << "    (* " << attr_key(idx) << " = "
@@ -1616,11 +1688,14 @@ void NetEBinary::dump(ostream&o) const
 	  case 'A':
 	    o << "~&";
 	    break;
+	  case 'e':
+	    o << "==";
+	    break;
 	  case 'E':
 	    o << "===";
 	    break;
-	  case 'e':
-	    o << "==";
+	  case 'w':
+	    o << "==?";
 	    break;
 	  case 'G':
 	    o << ">=";
@@ -1637,6 +1712,9 @@ void NetEBinary::dump(ostream&o) const
 	  case 'N':
 	    o << "!==";
 	    break;
+	  case 'W':
+	    o << "!=?";
+	    break;
 	  case 'o':
 	    o << "||";
 	    break;
@@ -1646,6 +1724,12 @@ void NetEBinary::dump(ostream&o) const
 	  case 'p':
 	    o << "**";
 	    break;
+	  case 'q':
+	    o << "->";
+	    break;
+	  case 'Q':
+	    o << "<->";
+	    break;
 	  case 'r':
 	    o << ">>";
 	    break;
@@ -1665,7 +1749,7 @@ void NetECast::dump(ostream&fd) const
 {
       if (op_=='2')
 	    fd << "bool<" << expr_width() << ">(" << *expr_ << ")";
-      else if (op_=='4')
+      else if (op_=='v')
 	    fd << "logic<" << expr_width() << ">(" << *expr_ << ")";
       else
 	    NetEUnary::dump(fd);
@@ -1889,18 +1973,6 @@ void Design::dump(ostream&o) const
 	    cur->second->dump(o);
       }
 
-      o << "$ROOT CLASSESS:" << endl;
-      for (map<perm_string,netclass_t*>::const_iterator cur = classes_.begin()
-		 ; cur != classes_.end() ; ++cur) {
-	    cur->second->dump_scope(o);
-      }
-
-      o << "$ROOT TASKS/FUNCTIONS:" << endl;
-      for (map<NetScope*,PTaskFunc*>::const_iterator cur = root_tasks_.begin()
-		 ; cur != root_tasks_.end() ; ++ cur) {
-	    cur->first->dump(o);
-      }
-
       o << "SCOPES:" << endl;
       for (list<NetScope*>::const_iterator scope = root_scopes_.begin();
 	   scope != root_scopes_.end(); ++ scope ) {

discipline.h

@@ -1,7 +1,7 @@
 #ifndef IVL_discipline_H
 #define IVL_discipline_H
 /*
- * Copyright (c) 2008-2014 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 2008-2021 Stephen Williams (steve@icarus.com)
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -69,9 +69,9 @@ class ivl_discipline_s : public LineInfo {
       ivl_discipline_s& operator = (const ivl_discipline_s&);
 };
 
-extern map<perm_string,ivl_nature_t> natures;
-extern map<perm_string,ivl_discipline_t> disciplines;
+extern std::map<perm_string,ivl_nature_t> natures;
+extern std::map<perm_string,ivl_discipline_t> disciplines;
   // Map access function name to the nature that it accesses.
-extern map<perm_string,ivl_nature_t> access_function_nature;
+extern std::map<perm_string,ivl_nature_t> access_function_nature;
 
 #endif /* IVL_discipline_H */

dosify.c

@@ -19,7 +19,7 @@
 
 /*
  * This is a simple program to make a dosified copy of the
- * original. That is, it converts unix style line ends to DOS
+ * original. That is, it converts Unix style line ends to DOS
  * style. This is useful for installing text files.
  *
  * The exact substitution is to replace \n with \r\n. If the line

driver-vpi/Makefile.in

@@ -36,6 +36,7 @@ mandir = @mandir@
 dllib=@DLLIB@
 
 CC = @CC@
+HOSTCC := @CC@
 WINDRES = @WINDRES@
 INSTALL = @INSTALL@
 INSTALL_PROGRAM = @INSTALL_PROGRAM@
@@ -49,6 +50,7 @@ endif
 
 CPPFLAGS = $(INCLUDE_PATH) @CPPFLAGS@ @DEFS@
 CFLAGS = @WARNING_FLAGS@ @WARNING_FLAGS_CC@ @CFLAGS@
+CXXFLAGS = @WARNING_FLAGS@ @WARNING_FLAGS_CXX@ @CXXFLAGS@
 LDFLAGS = @LDFLAGS@
 
 O = main.o res.o
@@ -64,7 +66,7 @@ distclean: clean
 	rm -f Makefile config.log
 
 cppcheck: main.c
-	cppcheck --enable=all -f $(INCLUDE_PATH) $^
+	cppcheck --enable=all --std=posix --std=c99 --std=c++03 -f $(INCLUDE_PATH) $^
 
 Makefile: $(srcdir)/Makefile.in ../config.status
 	cd ..; ./config.status --file=driver-vpi/$@
@@ -80,24 +82,34 @@ config.h: $(srcdir)/config.h.in Makefile
 	sed -e 's;@IVLCC@;@CC@;' -e 's;@IVLCXX@;@CXX@;' \
 	    -e 's;@SUFFIX@;$(suffix);g' \
 	    -e 's;@IVLCFLAGS@;$(CFLAGS);' \
+	    -e 's;@IVLCXXFLAGS@;$(CXXFLAGS);' \
 	    -e 's;@SHARED@;@shared@;' $< > $@
 
 # Windows specific...
 res.rc: $(srcdir)/res.rc.in ../version.exe
-	sed -e 's;@PRODUCTVERSION@;'`../version.exe '%M,%m,%n,0'`';' \
+	sed -e 's;@PRODUCTVERSION@;'`../version.exe '%M,%n,0,0'`';' \
 	$(srcdir)/res.rc.in > $@
 
 res.o: res.rc
 	$(WINDRES) -i res.rc -o res.o
 #
 
-install: all installdirs $(bindir)/iverilog-vpi$(suffix)@EXEEXT@
+install: all installdirs installfiles
 
-$(bindir)/iverilog-vpi$(suffix)@EXEEXT@: ./iverilog-vpi@EXEEXT@
-	$(INSTALL_PROGRAM) ./iverilog-vpi@EXEEXT@ "$(bindir)/iverilog-vpi$(suffix)@EXEEXT@"
+F = ./iverilog-vpi@EXEEXT@
+
+installfiles: $(F) | installdirs
+	$(INSTALL_PROGRAM) ./iverilog-vpi@EXEEXT@ "$(DESTDIR)$(bindir)/iverilog-vpi$(suffix)@EXEEXT@"
+ifeq (@WIN32@,yes)
+ifneq ($(HOSTCC),$(CC))
+	$(INSTALL_PROGRAM) $(shell $(HOSTCC) --print-file-name=libwinpthread-1.dll) "$(DESTDIR)$(bindir)"
+	$(INSTALL_PROGRAM) $(shell $(HOSTCC) --print-file-name=libgcc_s_sjlj-1.dll) "$(DESTDIR)$(bindir)"
+	$(INSTALL_PROGRAM) $(shell $(HOSTCC) --print-file-name=libstdc++-6.dll) "$(DESTDIR)$(bindir)"
+endif
+endif
 
 installdirs: $(srcdir)/../mkinstalldirs
-	$(srcdir)/../mkinstalldirs "$(bindir)"
+	$(srcdir)/../mkinstalldirs "$(DESTDIR)$(bindir)"
 
 uninstall:
-	rm -f $(bindir)/iverilog-vpi$(suffix)@EXEEXT@
+	rm -f $(DESTDIR)$(bindir)/iverilog-vpi$(suffix)@EXEEXT@

driver-vpi/config.h.in

@@ -4,6 +4,7 @@
 #define IVERILOG_VPI_CC        "@IVLCC@"
 #define IVERILOG_VPI_CXX       "@IVLCXX@"
 #define IVERILOG_VPI_CFLAGS    " @IVLCFLAGS@"
+#define IVERILOG_VPI_CXXFLAGS  " @IVLCXXFLAGS@"
 #define IVERILOG_VPI_LDFLAGS   "@SHARED@"
 #define IVERILOG_VPI_LDLIBS    "-lveriuser@SUFFIX@ -lvpi@SUFFIX@"
 #define IVERILOG_SUFFIX        "@SUFFIX@"

driver-vpi/main.c

@@ -1,4 +1,5 @@
 /*
+ * Copyright (c) 2015-2022 Martin Whitaker
  * Copyright (c) 2002 Gus Baldauf (gus@picturel.com)
  *
  *    This source code is free software; you can redistribute it
@@ -20,7 +21,7 @@
 /*
  *	iverilog-vpi.c
  *
- *	this program provides the functionality of iverilog-vpi.sh under Win32
+ *	this program provides the functionality of iverilog-vpi.sh under Windows
  */
 
 #include <stdio.h>
@@ -32,7 +33,7 @@
 
 #include <windows.h>
 
-static void setup_ivl_environment();
+static void setup_ivl_environment(void);
 static void assign(char **ptr, char *str);
 
 /* The compile options: compiler, flags, etc. are in here */
@@ -43,16 +44,17 @@ static void assign(char **ptr, char *str);
 static struct global_strings {
 	char *pCCSRC;		/* list of C source files (*.c) */
 	char *pCXSRC;		/* list of C++ source files (*.cc, *.cpp) */
-	char *pOBJ;			/* list of object files */
-	char *pLIB;			/* list of library files */
-	char *pINCS;			/* list of include directories */
-	char *pDEFS;			/* list of definitions */
-	char *pOUT;			/* output file name (.vpi extension), if 0 length then no source files specified */
+	char *pOBJ;		/* list of object files */
+	char *pLIB;		/* list of library files */
+	char *pINCS;		/* list of include directories */
+	char *pDEFS;		/* list of definitions */
+	char *pOUT;		/* output file name (.vpi extension), if 0 length then no source files specified */
 	char *pMINGW;		/* path to MinGW directory */
-	char *pIVL;			/* path to IVL directory */
-	char *pCFLAGS;		/* CFLAGS option */
-	char *pLDLIBS;		/* LDLIBS option */
-	char *pNewPath;		/* new PATH environment variable setting */
+	char *pIVL;		/* path to IVL directory */
+	char *pCCFLAGS;		/* compiler flags for compiling C source files */
+	char *pCXFLAGS;		/* compiler flags for compiling C++ source files */
+	char *pLDLIBS;		/* linker flags for final linking stage */
+	char *pCCNAME;		/* base name of compiler */
 	char *pLD;		/* what to use for a linker */
 } gstr;
 
@@ -75,21 +77,21 @@ static void myExit(int exitVal)
 	deInitDynString(gstr.pOUT);
 	deInitDynString(gstr.pMINGW);
 	deInitDynString(gstr.pIVL);
-	deInitDynString(gstr.pCFLAGS);
+	deInitDynString(gstr.pCCFLAGS);
+	deInitDynString(gstr.pCXFLAGS);
 	deInitDynString(gstr.pLDLIBS);
-	deInitDynString(gstr.pNewPath);
-	free(gstr.pLD);
+	deInitDynString(gstr.pCCNAME);
+	deInitDynString(gstr.pLD);
 
 	exit(exitVal);
 }
 
 /* display usage summary and exit */
 
-static void usage()
+static void usage(void)
 {
-	fprintf(stderr,"usage: iverilog-vpi" IVERILOG_SUFFIX " [src and obj files]...\n");
-	fprintf(stderr,"   or  iverilog-vpi" IVERILOG_SUFFIX " -mingw=dir\n");
-	fprintf(stderr,"   or  iverilog-vpi" IVERILOG_SUFFIX " -ivl=dir\n");
+	fprintf(stderr, "usage: iverilog-vpi" IVERILOG_SUFFIX " [options] [src and obj files]...\n");
+	fprintf(stderr, "   or  iverilog-vpi" IVERILOG_SUFFIX " -mingw=dir\n");
 	myExit(1);
 }
 
@@ -98,7 +100,7 @@ static void initDynString(char **str)
 	*str = (char *) malloc(1);
 
 	if (!*str) {
-		fprintf(stderr,"error: out of memory\n");
+		fprintf(stderr, "error: out of memory\n");
 		myExit(4);
 	}
 
@@ -107,8 +109,10 @@ static void initDynString(char **str)
 
 /* initialize dynamic memory buffers */
 
-static void init()
+static void init(void)
 {
+	char *ptr;
+
 	initDynString(&gstr.pCCSRC);
 	initDynString(&gstr.pCXSRC);
 	initDynString(&gstr.pOBJ);
@@ -118,9 +122,17 @@ static void init()
 	initDynString(&gstr.pOUT);
 	initDynString(&gstr.pMINGW);
 	initDynString(&gstr.pIVL);
-	initDynString(&gstr.pCFLAGS);
+	initDynString(&gstr.pCCFLAGS);
+	initDynString(&gstr.pCXFLAGS);
 	initDynString(&gstr.pLDLIBS);
-	initDynString(&gstr.pNewPath);
+	initDynString(&gstr.pCCNAME);
+	initDynString(&gstr.pLD);
+
+	  /* Get the base name of the C compiler. */
+	assign(&gstr.pCCNAME, IVERILOG_VPI_CC);
+	ptr = strchr(gstr.pCCNAME, ' ');
+	if (ptr != NULL) *ptr = '\0';
+
 	  /* By default use the C compiler to link the programs. */
 	assign(&gstr.pLD, IVERILOG_VPI_CC);
 }
@@ -136,7 +148,7 @@ static int endsIn (char *end, char *str)
 
 	ext = str + (strlen(str) - strlen(end));
 
-	return stricmp(end,ext) ? 0 : 1;
+	return stricmp(end, ext) ? 0 : 1;
 }
 
 /* return true if "str" begins with "prefix", case insensitive */
@@ -146,35 +158,35 @@ static int startsWith (char *prefix, char *str)
 	if (strlen(prefix) >= strlen(str))
 		return 0;
 
-	return strnicmp(prefix,str,strlen(prefix)) ? 0 : 1;
+	return strnicmp(prefix, str, strlen(prefix)) ? 0 : 1;
 }
 
 /* append "app" to "ptr", allocating memory as needed    */
 /*   if count is zero, then copy all characters of "app" */
 
-static void appendn (char **ptr, char *app, int count)
+static void appendn (char **ptr, char *app, size_t count)
 {
 	char *nptr = (char *) realloc(*ptr, strlen(*ptr) +
-                                            (count?count:strlen(app)) + 1);
+                                            (count ? count : strlen(app)) + 1);
 
 	if (nptr == NULL) {
-		fprintf(stderr,"error: out of memory\n");
+		fprintf(stderr, "error: out of memory\n");
 		free(*ptr);
 		myExit(4);
 	}
 	*ptr = nptr;
 
 	if (count)
-		strncat(*ptr,app,count);
+		strncat(*ptr, app, count);
 	else
-		strcat(*ptr,app);
+		strcat(*ptr, app);
 }
 
 /* append "app" to "ptr", allocating memory as needed    */
 
 static void append (char **ptr, char *app)
 {
-	appendn(ptr,app,0);
+	appendn(ptr, app, 0);
 }
 
 /* if the string does not end with a backslash, add one */
@@ -182,36 +194,36 @@ static void append (char **ptr, char *app)
 static void appendBackSlash(char **str)
 {
 	if ((*str)[strlen(*str)-1] != '\\')
-		append(str,"\\");
+		append(str, "\\");
 }
 
 /* copy count characters of "str" to "ptr", allocating memory as needed */
 /*   if count is zero, then copy all characters of "str"                */
 
-static void assignn (char **ptr, char *str, int count)
+static void assignn (char **ptr, char *str, size_t count)
 {
-	char *nptr = (char *) realloc(*ptr, (count?count:strlen(str)) + 1);
+	char *nptr = (char *) realloc(*ptr, (count ? count : strlen(str)) + 1);
 
 	if (nptr == NULL) {
-		fprintf(stderr,"error: out of memory\n");
+		fprintf(stderr, "error: out of memory\n");
 		free(*ptr);
 		myExit(4);
 	}
 	*ptr = nptr;
 
 	if (count) {
-		strncpy(*ptr,str,count);
+		strncpy(*ptr, str, count);
 		(*ptr)[count] = 0;
 	}
 	else
-		strcpy(*ptr,str);
+		strcpy(*ptr, str);
 }
 
 /* copy count characters of "str" to "ptr", allocating memory as needed */
 
 static void assign (char **ptr, char *str)
 {
-	assignn(ptr,str,0);
+	assignn(ptr, str, 0);
 }
 
 /* get a copy of a Icarus Verilog registry string key */
@@ -223,11 +235,11 @@ static int GetRegistryKey(char *key, char **value)
 	char *regKeyBuffer;
 	DWORD regKeyType, regKeySize;
 
-	lrv = RegOpenKeyEx(HKEY_LOCAL_MACHINE,"Software\\Icarus Verilog",0,KEY_QUERY_VALUE,&hkKey);
+	lrv = RegOpenKeyEx(HKEY_LOCAL_MACHINE, "Software\\Icarus Verilog", 0, KEY_QUERY_VALUE, &hkKey);
 	if (lrv != ERROR_SUCCESS)
 		return 0;
 
-	lrv = RegQueryValueEx(hkKey,key,NULL,&regKeyType,NULL,&regKeySize);
+	lrv = RegQueryValueEx(hkKey, key, NULL, &regKeyType, NULL, &regKeySize);
 	if ((lrv != ERROR_SUCCESS) || (regKeyType != REG_SZ) || (!regKeySize)) {
 		lrv = RegCloseKey(hkKey);
 		return 0;
@@ -236,7 +248,7 @@ static int GetRegistryKey(char *key, char **value)
 	regKeyBuffer = (char *) malloc(regKeySize+1);
 	if (!regKeyBuffer) {
 		lrv = RegCloseKey(hkKey);
-		fprintf(stderr,"error: out of memory\n");
+		fprintf(stderr, "error: out of memory\n");
 		myExit(4);
 	}
 	regKeyBuffer[regKeySize] = 0;		/* makes sure there is a trailing NULL */
@@ -252,7 +264,7 @@ static int GetRegistryKey(char *key, char **value)
 
 	RegCloseKey(hkKey);
 
-	assign(value,regKeyBuffer);
+	assign(value, regKeyBuffer);
 	free(regKeyBuffer);
 
 	return 1;
@@ -262,27 +274,30 @@ static int GetRegistryKey(char *key, char **value)
 
 static void SetRegistryKey(char *key, char *value)
 {
+	long lrv;
 	HKEY hkKey;
 	DWORD res;
 
-	if (RegCreateKeyEx(
-		HKEY_LOCAL_MACHINE,
-		"Software\\Icarus Verilog",
-		0,
-		"",
-		REG_OPTION_NON_VOLATILE,
-		KEY_ALL_ACCESS,NULL,
-		&hkKey,
-		&res) != ERROR_SUCCESS)
-			return;
+	lrv = RegCreateKeyEx(HKEY_LOCAL_MACHINE, "Software\\Icarus Verilog", 0, "",
+			     REG_OPTION_NON_VOLATILE, KEY_ALL_ACCESS, NULL, &hkKey, &res);
+	if (lrv != ERROR_SUCCESS) {
+		char message[1024];
+		FormatMessage(FORMAT_MESSAGE_FROM_SYSTEM, NULL, lrv, LANG_USER_DEFAULT,
+			      message, sizeof(message), NULL);
+		fprintf(stderr, "error: couldn't write to registry - %s\n", message);
+		if (lrv == ERROR_ACCESS_DENIED) {
+			fprintf(stderr, "       try running as administrator\n");
+		}
+		return;
+	}
 
 	/* This needs an unsigned char *, but for MinGW the char is signed. */
 	RegSetValueEx(hkKey, key, 0, REG_SZ, (unsigned char *) value,
 	              strlen(value)+1);
 	RegCloseKey(hkKey);
 
-	printf("info:  storing %s in Windows' registry entry\n",value);
-	printf("       HKEY_LOCAL_MACHINE\\Software\\Icarus Verilog\\%s\n",key);
+	printf("info:  storing %s in Windows' registry entry\n", value);
+	printf("       HKEY_LOCAL_MACHINE\\Software\\Icarus Verilog\\%s\n", key);
 }
 
 /* parse the command line, assign results to global variable strings */
@@ -299,7 +314,6 @@ static int parse(int argc, char *argv[])
 	char lib_option[]   = "-l";
 	char inc_option[]   = "-I";
 	char mingw_option[] = "-mingw=";
-	char ivl_option[]   = "-ivl=";
 	char def_option[]   = "-D";
 
 	if (argc == 1) return 0;
@@ -339,7 +353,7 @@ static int parse(int argc, char *argv[])
 		  /* Check for compiled object files */
 		else if (endsIn(dot_o_ext, argv[idx])) {
 			++srcFileCnt;
-			append(&gstr.pOBJ," ");
+			append(&gstr.pOBJ, " ");
 			append(&gstr.pOBJ, argv[idx]);
 			if (!*gstr.pOUT)
 			   assignn(&gstr.pOUT, argv[idx],
@@ -349,10 +363,6 @@ static int parse(int argc, char *argv[])
 		else if (startsWith(mingw_option, argv[idx]))
 			assignn(&gstr.pMINGW, argv[idx]+sizeof(mingw_option)-1,
 			        strlen(argv[idx])-(sizeof(mingw_option)-1));
-		  /* Check for the -ivl   option */
-		else if (startsWith(ivl_option, argv[idx]))
-			assignn(&gstr.pIVL, argv[idx]+sizeof(ivl_option)-1,
-			        strlen(argv[idx])-(sizeof(ivl_option)-1));
 		  /* Check for the --name option */
 		else if (startsWith(name_option, argv[idx])) {
 			assignn(&gstr.pOUT, argv[idx]+sizeof(name_option)-1,
@@ -376,7 +386,7 @@ static int parse(int argc, char *argv[])
 		  /* Check for the --cflags option */
 		else if (stricmp("--cflags", argv[idx]) == 0) {
 			setup_ivl_environment();
-			printf("%s\n", gstr.pCFLAGS);
+			printf("%s\n", gstr.pCCFLAGS);
 			myExit(0);
 		}
 		  /* Check for the --ldflags option */
@@ -393,7 +403,7 @@ static int parse(int argc, char *argv[])
 		  /* Check for the --install-dir option */
 		else if (stricmp("--install-dir", argv[idx]) == 0) {
 			setup_ivl_environment();
-			printf("%s\\\\lib\\\\ivl" IVERILOG_SUFFIX "\\\\.\n", gstr.pIVL);
+			printf("%s\\lib\\ivl" IVERILOG_SUFFIX "\\.\n", gstr.pIVL);
 			myExit(0);
 		}
 		  /* This is different than iverilog-vpi.sh, we don't
@@ -402,15 +412,16 @@ static int parse(int argc, char *argv[])
 	}
 
 	  /* In case there is a --name without source/object files */
-	if (0 == srcFileCnt) assign(&gstr.pOUT,"");
+	if (0 == srcFileCnt) assign(&gstr.pOUT, "");
 
-	  /* Normally it's an error if there are no source or object files */
-	  /* Unless we are setting the IVL or MinGW registry entries */
-	if (!*gstr.pOUT) {
-		if (!*gstr.pMINGW && !*gstr.pIVL) return 0;
-	} else
+	if (*gstr.pOUT) {
 		  /* We have a valid result file so add the .vpi extension */
 		append(&gstr.pOUT, ".vpi");
+	} else {
+		  /* Unless we are setting the MinGW registry entry, it's
+		     an error if there are no source or object files */
+		if (!*gstr.pMINGW) return 0;
+	}
 
 	return 1;
 }
@@ -421,58 +432,27 @@ static void checkMingwDir(char *root)
 {
 	int irv;
 	struct _stat stat_buf;
-
-	char *path, *comp, *cp;
-	initDynString(&path);
-	assign(&path,gstr.pMINGW);
-	appendBackSlash(&path);
-	append(&path,"bin\\");
-	/* Get just the compiler name (the first word) */
-	comp = strdup(IVERILOG_VPI_CC);
-	cp = strchr(comp, ' ');
-	if (cp != NULL) *cp = '\0';
-        append(&path, comp);
-	append(&path,".exe");
-        free(comp);
-
-	irv = _stat(path,&stat_buf);
-	deInitDynString(path);
-
-	if (irv) {
-		fprintf(stderr,"error: %s does not appear to be the valid root directory\n",root);
-		fprintf(stderr,"       of MinGW.  Use the -mingw option of iverilog-vpi.exe to\n");
-		fprintf(stderr,"       point to the MinGW root directory.  For a Windows command\n");
-		fprintf(stderr,"       shell the option would be something like -mingw=c:\\mingw\n");
-		fprintf(stderr,"       For a Cygwin shell the option would be something like\n");
-		fprintf(stderr,"       -mingw=c:\\\\mingw\n");
-		myExit(5);
-	}
-}
-
-/* do minimal check that the Icarus Verilog root directory looks valid */
-
-static void checkIvlDir(char *root)
-{
-	int irv;
-	struct _stat stat_buf;
-
 	char *path;
+
 	initDynString(&path);
-	assign(&path,gstr.pIVL);
+	assign(&path, gstr.pMINGW);
 	appendBackSlash(&path);
-	append(&path,"bin\\vvp" IVERILOG_SUFFIX ".exe");
+	append(&path, "bin\\");
+        append(&path, gstr.pCCNAME);
+	append(&path, ".exe");
 
 	irv = _stat(path,&stat_buf);
 	deInitDynString(path);
 
 	if (irv) {
-		fprintf(stderr,"error: %s does not appear to be the valid root directory of\n",root);
-		fprintf(stderr,"       Icarus Verilog.  Use the -ivl option of iverilog-vpi" IVERILOG_SUFFIX " to\n");
-		fprintf(stderr,"       point to the Icarus Verilog root directory.  For a Windows\n");
-		fprintf(stderr,"       command shell the option would be something like -ivl=c:\\iverilog\n");
-		fprintf(stderr,"       For a Cygwin shell the option would be something like\n");
-		fprintf(stderr,"       -ivl=c:\\\\iverilog\n");
-		myExit(6);
+		fprintf(stderr, "error: %s\n", root);
+		fprintf(stderr, "       does not appear to be the valid root directory of\n");
+		fprintf(stderr, "       MinGW.  Use the -mingw option of iverilog-vpi.exe to\n");
+		fprintf(stderr, "       point to the MinGW root directory.  For a Windows command\n");
+		fprintf(stderr, "       shell the option would be something like -mingw=c:\\mingw\n");
+		fprintf(stderr, "       For a Cygwin shell the option would be something like\n");
+		fprintf(stderr, "       -mingw=c:\\\\mingw\n");
+		myExit(5);
 	}
 }
 
@@ -480,68 +460,98 @@ static void checkIvlDir(char *root)
 
 #define IVL_REGKEY_MINGW "MingwDir"
 
-static void setup_mingw_environment()
+static void setup_mingw_environment(void)
 {
-	char *pOldPATH = getenv("PATH");		/* get current path */
+	char buffer[1];		/* doesn't matter how big this is, as we don't use the result */
+	char *path;
 
 	if (*gstr.pMINGW) {
 		checkMingwDir(gstr.pMINGW);
-		SetRegistryKey(IVL_REGKEY_MINGW,gstr.pMINGW);
-	} else if (!GetRegistryKey(IVL_REGKEY_MINGW,&gstr.pMINGW)) {
-			fprintf(stderr,"error: can not locate the MinGW root directory, use the -mingw option of\n");
-			fprintf(stderr,"       iverilog-vpi.exe to point to the MinGW root directory.  For\n");
-			fprintf(stderr,"       a Windows command shell the option would be something like\n");
-			fprintf(stderr,"       -mingw=c:\\mingw  For a Cygwin shell the option would be\n");
-			fprintf(stderr,"       something like -mingw=c:\\\\mingw\n");
-			myExit(5);
-		}
+		if (!*gstr.pOUT) SetRegistryKey(IVL_REGKEY_MINGW, gstr.pMINGW);
+
+	} else if (GetRegistryKey(IVL_REGKEY_MINGW, &gstr.pMINGW)) {
+		checkMingwDir(gstr.pMINGW);
+
+	} else if (SearchPath(NULL, gstr.pCCNAME, ".exe", sizeof(buffer), buffer, NULL)) {
+		return;
+
+	} else {
+		fprintf(stderr, "error: cannot locate the MinGW C compiler - either add its location\n");
+		fprintf(stderr, "       to the PATH environment variable or use the -mingw option of\n");
+		fprintf(stderr, "       iverilog-vpi.exe to point to the MinGW root directory.  For\n");
+		fprintf(stderr, "       a Windows command shell the option would be something like\n");
+		fprintf(stderr, "       -mingw=c:\\mingw  For a Cygwin shell the option would be\n");
+		fprintf(stderr, "       something like -mingw=c:\\\\mingw\n");
+		myExit(5);
+	}
 
 	  /* Create new path with MinGW in it */
-	assign(&gstr.pNewPath,"PATH=");
-	append(&gstr.pNewPath,gstr.pMINGW);
-	appendBackSlash(&gstr.pNewPath);
-	append(&gstr.pNewPath, "\\");
-	append(&gstr.pNewPath,"bin;");
-	append(&gstr.pNewPath,pOldPATH);
+	initDynString(&path);
+	assign(&path, "PATH=");
+	append(&path, gstr.pMINGW);
+	appendBackSlash(&path);
+	append(&path, "bin;");
+	append(&path, getenv("PATH"));
 
 	  /* Place new path in environment */
-	_putenv(gstr.pNewPath);
+	_putenv(path);
+	deInitDynString(path);
 }
 
-/* see if we can find iverilog root */
+/* find the iverilog root and initialise the compiler options */
 
-#define IVL_REGKEY_IVL   "InstallDir"
-
-static void setup_ivl_environment()
+static void setup_ivl_environment(void)
 {
-	if (*gstr.pIVL) {
-		checkIvlDir(gstr.pIVL);
-		SetRegistryKey(IVL_REGKEY_IVL,gstr.pIVL);
-	} else if (!GetRegistryKey(IVL_REGKEY_IVL,&gstr.pIVL)) {
-			fprintf(stderr,"error: can not locate the Icarus Verilog root directory, use the -ivl option\n");
-			fprintf(stderr,"       of iverilog-vpi" IVERILOG_SUFFIX " to point to the Icarus Verilog root directory.\n");
-			fprintf(stderr,"       For a Windows command shell the option would be something like\n");
-			fprintf(stderr,"       -ivl=c:\\iverilog  For a Cygwin shell the option would be something\n");
-			fprintf(stderr,"       like -ivl=c:\\\\iverilog\n");
-			myExit(6);
-		}
+	char path[4096];
+	char *ptr;
 
-	  /* Build up the CFLAGS option string */
-	assign(&gstr.pCFLAGS,IVERILOG_VPI_CFLAGS " -I\"");
-	append(&gstr.pCFLAGS,gstr.pIVL);
-	appendBackSlash(&gstr.pCFLAGS);
-	append(&gstr.pCFLAGS,"\\include\\\\iverilog\"" IVERILOG_SUFFIX);
+	  /* Extract the Icarus Verilog root directory from the path to the
+	     command. The command path will look something like this:
+
+		C:\iverilog\bin\iverilog-vpi.exe
+
+	     The corresponding root directory is
+
+		C:\iverilog
+
+	     so we chop off the file name and the last directory. */
+	GetModuleFileName(NULL, path, sizeof(path));
+	ptr = strrchr(path, '\\');
+	if (!ptr) {
+		fprintf(stderr, "error: couldn't find start of program name in command path '%s'\n", path);
+		myExit(6);
+	}
+	*ptr = 0;
+	ptr = strrchr(path, '\\');
+	if (!ptr) {
+		fprintf(stderr, "error: couldn't find start of bin directory in command path '%s'\n", path);
+		myExit(6);
+	}
+	*ptr = 0;
+	assign(&gstr.pIVL, path);
+
+	  /* Build up the CCFLAGS option string */
+	assign(&gstr.pCCFLAGS, IVERILOG_VPI_CFLAGS " -I\"");
+	append(&gstr.pCCFLAGS, gstr.pIVL);
+	appendBackSlash(&gstr.pCCFLAGS);
+	append(&gstr.pCCFLAGS, "include\\iverilog\"" IVERILOG_SUFFIX);
+
+	  /* Build up the CXFLAGS option string */
+	assign(&gstr.pCXFLAGS, IVERILOG_VPI_CXXFLAGS " -I\"");
+	append(&gstr.pCXFLAGS, gstr.pIVL);
+	appendBackSlash(&gstr.pCXFLAGS);
+	append(&gstr.pCXFLAGS, "include\\iverilog\"" IVERILOG_SUFFIX);
 
 	  /* Build up the LDFLAGS option string */
-	assign(&gstr.pLDLIBS,"-L\"");
-	append(&gstr.pLDLIBS,gstr.pIVL);
+	assign(&gstr.pLDLIBS, "-L\"");
+	append(&gstr.pLDLIBS, gstr.pIVL);
 	appendBackSlash(&gstr.pLDLIBS);
-	append(&gstr.pLDLIBS,"\\lib\" " IVERILOG_VPI_LDLIBS);
+	append(&gstr.pLDLIBS, "lib\" " IVERILOG_VPI_LDLIBS);
 }
 
 /* compile source modules */
 
-static void compile(char *pSource, char **pObject, int *compile_errors, char *compiler)
+static void compile(char *pSource, char *pFlags, char **pObject, int *compile_errors, char *compiler)
 {
 	char *ptr1 = pSource;
 	char *ptr2 = strchr(ptr1, ' ');
@@ -554,10 +564,10 @@ static void compile(char *pSource, char **pObject, int *compile_errors, char *co
 		assignn(&src, ptr1, len);
 
 		  /* Build the object file name */
-		ostart = strrchr(ptr1, '/');
-		if (ostart == NULL) ostart = ptr1;
+		ostart = strrchr(src, '/');
+		if (ostart == NULL) ostart = src;
 		else ostart += 1;
-		olen = strrchr(ptr1, '.') - ostart;
+		olen = strrchr(ostart, '.') - ostart;
 		assignn(&obj, ostart, olen);
 		append(&obj, ".o");
 
@@ -568,7 +578,7 @@ static void compile(char *pSource, char **pObject, int *compile_errors, char *co
 		append(&buf, " ");
 		append(&buf, gstr.pDEFS);
 		append(&buf, " ");
-		append(&buf, gstr.pCFLAGS);
+		append(&buf, pFlags);
 		append(&buf, " ");
 		append(&buf, gstr.pINCS);
 		append(&buf, " ");
@@ -593,27 +603,22 @@ static void compile(char *pSource, char **pObject, int *compile_errors, char *co
 
 /* using the global strings, compile and link */
 
-static void compile_and_link()
+static void compile_and_link(void)
 {
 	char *buf=0;
 	int iRet, compile_errors = 0;
 
 	  /* To make the output match iverilog-vpi.sh do not print out the
 	   * root directories */
-
 //	printf("MinGW root directory:  %s.\n", gstr.pMINGW);
-	checkMingwDir(gstr.pMINGW);
-
-//	printf("Icarus Verilog root directory:  %s.\n", gstr.pIVL);
-	checkIvlDir(gstr.pIVL);
 
 	  /* compile the C source files (*.c) */
-	compile(gstr.pCCSRC, &gstr.pOBJ, &compile_errors, IVERILOG_VPI_CC );
+	compile(gstr.pCCSRC, gstr.pCCFLAGS, &gstr.pOBJ, &compile_errors, IVERILOG_VPI_CC );
 	  /* compile the C++ source files (*.cc, *.cpp) */
-	compile(gstr.pCXSRC, &gstr.pOBJ, &compile_errors, IVERILOG_VPI_CXX);
+	compile(gstr.pCXSRC, gstr.pCXFLAGS, &gstr.pOBJ, &compile_errors, IVERILOG_VPI_CXX);
 
 	if (compile_errors) {
-		fprintf(stderr,"iverilog-vpi: %d file(s) failed to compile.\n",
+		fprintf(stderr, "iverilog-vpi: %d file(s) failed to compile.\n",
 		        compile_errors);
 		myExit(2);
 	}
@@ -644,7 +649,7 @@ int main(int argc, char *argv[])
 {
 	init();
 
-	if (!parse(argc,argv)) usage();
+	if (!parse(argc, argv)) usage();
 
 	setup_mingw_environment();
 	setup_ivl_environment();

driver/Makefile.in

@@ -67,7 +67,7 @@ distclean: clean
 	rm -f Makefile config.log
 
 cppcheck: $(O:.o=.c)
-	cppcheck --enable=all -f \
+	cppcheck --enable=all --std=posix --std=c99 --std=c++03 -f \
 	         -UYY_USER_INIT \
 	         -UYYPARSE_PARAM -UYYPRINT -Ushort -Uyyoverflow \
 	         -UYYTYPE_INT8 -UYYTYPE_INT16 -UYYTYPE_UINT8 -UYYTYPE_UINT16 \
@@ -85,10 +85,9 @@ iverilog@EXEEXT@: $O
 cflexor.c: $(srcdir)/cflexor.lex
 	$(LEX) -s -t $< > $@
 
-# Build this in two steps to avoid parallel build issues (see pr3462585)
-cfparse.c: $(srcdir)/cfparse.y
-	$(YACC) --verbose -t -p cf -d -o $@ $<
-cfparse.h: cfparse.c
+# Use pattern rules to avoid parallel build issues (see pr3462585)
+cfparse%c cfparse%h: $(srcdir)/cfparse%y
+	$(YACC) --verbose -t -p cf -d -o cfparse.c $<
 
 %.o: %.c
 	$(CC) $(CPPFLAGS) $(CFLAGS) @DEPENDENCY_FLAG@ -c $< -o $*.o
@@ -112,32 +111,35 @@ iverilog.pdf: iverilog.ps
 
 ifeq (@MINGW32@,yes)
 ifeq ($(MAN),none)
-INSTALL_DOC = $(mandir)/man1/iverilog$(suffix).1
+INSTALL_DOC = installman
 else
 ifeq ($(PS2PDF),none)
-INSTALL_DOC = $(mandir)/man1/iverilog$(suffix).1
+INSTALL_DOC = installman
 else
-INSTALL_DOC = $(prefix)/iverilog$(suffix).pdf $(mandir)/man1/iverilog$(suffix).1
+INSTALL_DOC = installpdf installman
 all: iverilog.pdf
 endif
 endif
 INSTALL_DOCDIR = $(mandir)/man1
 else
-INSTALL_DOC = $(mandir)/man1/iverilog$(suffix).1
+INSTALL_DOC = installman
 INSTALL_DOCDIR = $(mandir)/man1
 endif
 
-install: all installdirs $(bindir)/iverilog$(suffix)@EXEEXT@ $(INSTALL_DOC)
+install: all installdirs installfiles
 
-$(bindir)/iverilog$(suffix)@EXEEXT@: ./iverilog@EXEEXT@
-	$(INSTALL_PROGRAM) ./iverilog@EXEEXT@ "$(DESTDIR)$(bindir)/iverilog$(suffix)@EXEEXT@"
+F = ./iverilog@EXEEXT@ \
+	$(INSTALL_DOC)
 
-$(mandir)/man1/iverilog$(suffix).1: iverilog.man
+installman: iverilog.man installdirs
 	$(INSTALL_DATA) iverilog.man "$(DESTDIR)$(mandir)/man1/iverilog$(suffix).1"
 
-$(prefix)/iverilog$(suffix).pdf: iverilog.pdf
+installpdf: iverilog.pdf installdirs
 	$(INSTALL_DATA) iverilog.pdf "$(DESTDIR)$(prefix)/iverilog$(suffix).pdf"
 
+installfiles: $(F) | installdirs
+	$(INSTALL_PROGRAM) ./iverilog@EXEEXT@ "$(DESTDIR)$(bindir)/iverilog$(suffix)@EXEEXT@"
+
 installdirs: $(srcdir)/../mkinstalldirs
 	$(srcdir)/../mkinstalldirs "$(DESTDIR)$(bindir)" "$(DESTDIR)$(INSTALL_DOCDIR)"
 

driver/cflexor.lex

@@ -4,7 +4,7 @@
 
 %{
 /*
- * Copyright (c) 2001-2014 Stephen Williams ([email protected])
+ * Copyright (c) 2001-2017 Stephen Williams ([email protected])
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -22,11 +22,13 @@
  *    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
  */
 
-# include  "cfparse.h"
 # include  "cfparse_misc.h"
+# include  "cfparse.h"
 # include  "globals.h"
 # include  <string.h>
 
+char *current_file = NULL;
+
 static int comment_enter;
 static char* trim_trailing_white(char*txt, int trim);
 
@@ -124,7 +126,8 @@ int cmdfile_stack_ptr = 0;
 "-c" { return TOK_Dc; }
 "-f" { return TOK_Dc; }
 
-  /* Notice the -v flag. */
+  /* Notice the -l or -v flag. */
+"-l" { return TOK_Dv; }
 "-v" { return TOK_Dv; }
 
   /* Notice the -y flag. */
@@ -251,7 +254,7 @@ void destroy_lexor(void)
 {
 # ifdef FLEX_SCANNER
 #   if YY_FLEX_MAJOR_VERSION >= 2 && YY_FLEX_MINOR_VERSION >= 5
-#     if defined(YY_FLEX_SUBMINOR_VERSION) && YY_FLEX_SUBMINOR_VERSION >= 9
+#     if YY_FLEX_MINOR_VERSION > 5 || defined(YY_FLEX_SUBMINOR_VERSION) && YY_FLEX_SUBMINOR_VERSION >= 9
     yylex_destroy();
 #     endif
 #   endif

driver/cfparse_misc.h

@@ -39,6 +39,6 @@ int cferror(const char *);
 int cfparse(void);
 void switch_to_command_file(const char *);
 void destroy_lexor(void);
-char *current_file;
+extern char *current_file;
 
 #endif /* IVL_cfparse_misc_H */

driver/iverilog.man.in

@@ -1,14 +1,16 @@
-.TH iverilog 1 "February 26th, 2014" "" "Version %M.%m.%n %E"
+.TH iverilog 1 "Jan 14th, 2021" "" "Version %M.%n%E"
 .SH NAME
 iverilog - Icarus Verilog compiler
 
 .SH SYNOPSIS
 .B iverilog
-[\-ESVv] [\-Bpath] [\-ccmdfile|\-fcmdfile] [\-Dmacro[=defn]]
-[\-Pparameter=value] [\-pflag=value]
-[\-dname] [\-g1995|\-g2001|\-g2005|\-g2005-sv|\-g2009|\-g2012|\-g<feature>]
-[\-Iincludedir] [\-mmodule] [\-M[mode=]file] [\-Nfile] [\-ooutputfilename]
-[\-stopmodule] [\-ttype] [\-Tmin/typ/max] [\-Wclass] [\-ypath] sourcefile
+[\-EiSuVv] [\-Bpath] [\-ccmdfile|\-fcmdfile] [\-Dmacro[=defn]]
+[\-Pparameter=value] [\-pflag=value] [\-dname]
+[\-g1995\:|\-g2001\:|\-g2005\:|\-g2005-sv\:|\-g2009\:|\-g2012\:|\-g<feature>]
+[\-Iincludedir] [\-Lmoduledir] [\-mmodule] [\-M[mode=]file] [\-Nfile]
+[\-ooutputfilename] [\-stopmodule] [\-ttype] [\-Tmin/typ/max] [\-Wclass]
+[\-ypath] [\-lfile]
+sourcefile
 
 .SH DESCRIPTION
 .PP
@@ -30,7 +32,7 @@ different set of programs. The path given is used to locate
 \fIivlpp\fP, \fIivl\fP, code generators and the VPI modules.
 .TP 8
 .B -c\fIfile\fP -f\fIfile\fP
-These flags specifies an input file that contains a list of Verilog
+These flags specify an input file that contains a list of Verilog
 source files. This is similar to the \fIcommand file\fP of other
 Verilog simulators, in that it is a file that contains the file names
 instead of taking them on the command line. See \fBCommand Files\fP below.
@@ -79,6 +81,12 @@ use any of the new \fIIEEE1800\fP keywords.
 Enable or disable (default) support for Verilog\-AMS.
 Very little Verilog\-AMS specific functionality is currently supported.
 .TP 8
+.B -gassertions\fI|\fP-gsupported-assertions\fI|\fP-gno-assertions
+Enable (default) or disable SystemVerilog assertions. When enabled,
+assertion statements are elaborated. When disabled, assertion statements
+are parsed but ignored. The \fB\-gsupported-assertions\fP option only
+enables assertions that are currently supported by the compiler.
+.TP 8
 .B -gspecify\fI|\fP-gno-specify
 Enable or disable (default) specify block support. When enabled,
 specify block code is elaborated. When disabled, specify blocks are
@@ -123,7 +131,7 @@ default, parts of the expression that do not depend on the changed
 input value(s) are not re-evaluated. If an expression contains a call
 to a function that doesn't depend solely on its input values or that
 has side effects, the resulting behavior will differ from that
-required by the standard. Using \fI\-gstrict\-ca\-eval\fP will force
+required by the standard. Using \fB\-gstrict\-ca\-eval\fP will force
 standard compliant behavior (with some loss in performance).
 .TP 8
 .B -gstrict-expr-width\fI|\fP-gno-strict-expr-width
@@ -133,12 +141,42 @@ parameter assignment is evaluated as a lossless expression, as is any
 expression containing an unsized constant number, and unsized constant
 numbers are not truncated to integer width.
 .TP 8
+.B -gshared-loop-index\fI|\fP-gno-shared-loop-index
+Enable (default) or disable the exclusion of for-loop control variables
+from implicit event_expression lists. When enabled, if a for-loop control
+variable (loop index) is only used inside the for-loop statement, the
+compiler will not include it in an implicit event_expression list it
+calculates for that statement or any enclosing statement. This allows
+the same control variable to be used in multiple processes without risk
+of entering an infinite loop caused by each process triggering all other
+processes that use the same varaible. For strict compliance with the
+standards, this behaviour should be disabled.
+.TP 8
 .B -I\fIincludedir\fP
 Append directory \fIincludedir\fP to list of directories searched
 for Verilog include files. The \fB\-I\fP switch may be used many times
 to specify several directories to search, the directories are searched
 in the order they appear on the command line.
 .TP 8
+.B -i
+Ignore missing modules. Normally it is an error if a module instantiation
+refers to an undefined module. This option causes the compiler to skip
+over that instantiation. It will also stop the compiler returning an
+error if there are no top level modules. This allows the compiler to be
+used to check incomplete designs for errors.
+.TP 8
+.B -L\fIpath\fP
+This flag adds a directory to the path list used to locate VPI
+modules. The default path includes only the install directory for the
+system.vpi module, but this flag can add other directories. Multiple
+paths are allowed, and the paths will be searched in order.
+.TP 8
+.B -l\fIfile\fP
+Add the specified file to the list of source files to be compiled,
+but mark it as a library file. All modules contained within that
+file will be treated as library modules, and only elaborated if
+they are instantiated by other modules in the design.
+.TP 8
 .B -M\fIpath\fP
 This is equivalent to \fB\-Mall=path\fP. Preserved for backwards
 compatibility.
@@ -159,9 +197,13 @@ prefixed by "I " and other files are prefixed by "M ".
 .B -m\fImodule\fP
 Add this module to the list of VPI modules to be loaded by the
 simulation. Many modules can be specified, and all will be loaded, in
-the order specified. The system module is implicit and always included.
-If a System Function Table file (<module>.sft) exists for the module it
-will be loaded automatically.
+the order specified. The system module is implicit and always included
+(and loaded last).
+
+If the specified name includes at least one directory character, it is
+assumed to be prefixed by the path to the module, otherwise the module
+is searched for in the paths specified by preceding \fB-L\fP options,
+and if not found there, in the \fIiverilog\fP base directory.
 .TP 8
 .B -N\fIpath\fP
 This is used for debugging the compiler proper. Dump the final netlist
@@ -204,6 +246,12 @@ will suppress the warning that the compiler is making a choice.
 Use this switch to specify the target output format. See the
 \fBTARGETS\fP section below for a list of valid output formats.
 .TP 8
+.B -u
+Treat each source file as a separate compilation unit (as defined in
+SystemVerilog). If compiling for an \fIIEEE1364\fP generation, this
+will just reset all compiler directives (including macro definitions)
+before each new file is processed.
+.TP 8
 .B -v
 Turn on verbose messages. This will print the command lines that are
 executed to perform the actual compilation, along with version
@@ -213,6 +261,12 @@ a reference to a key temporary file that passes information to the
 compiler proper.  To keep that file from being deleted at the end
 of the process, provide a file name of your own in the environment
 variable \fBIVERILOG_ICONFIG\fP.
+
+If the selected target is \fIvvp\fP, the \fB\-v\fP switch is appended
+to the shebang line in the compiler output file, so directly executing
+the compiler output file will turn on verbose messages in \fIvvp\fP.
+This extra verbosity can be avoided by using the \fIvvp\fP command to
+indirectly execute the compiler output file.
 .TP 8
 .B -V
 Print the version of the compiler, and exit.
@@ -240,7 +294,7 @@ that contain Verilog source files.  During elaboration, the compiler
 notices the instantiation of undefined module types. If the user
 specifies library search directories, the compiler will search the
 directory for files with the name of the missing module type. If it
-finds such a file, it loads it as a Verilog source file, they tries
+finds such a file, it loads it as a Verilog source file, then tries
 again to elaborate the module.
 
 Library module files should contain only a single module, but this is
@@ -263,7 +317,10 @@ This is the default. The vvp target generates code for the vvp
 runtime. The output is a complete program that simulates the design
 but must be run by the \fBvvp\fP command. The -pfileline=1 option
 can be used to add procedural statement debugging opcodes to the
-generated code.
+generated code. These opcodes are also used to generate file and
+line information for procedural warning/error messages. To enable
+the debug command tracing us the trace command (trace on) from
+the vvp interactive prompt.
 .TP 8
 .B fpga
 This is a synthesis target that supports a variety of fpga devices,
@@ -286,8 +343,14 @@ after a \fB\-Wall\fP argument to suppress isolated warning types.
 
 .TP 8
 .B all
-This enables the implicit, portbind, select\-range, timescale, and
-sensitivity\-entire\-array warning categories.
+This enables the anachronisms, implicit, macro-replacement, portbind,
+select\-range, timescale, and sensitivity\-entire\-array warning
+categories.
+
+.TP 8
+.B anachronisms
+This enables warnings for use of features that have been deprecated
+or removed in the selected generation of the Verilog language.
 
 .TP 8
 .B implicit
@@ -295,6 +358,13 @@ This enables warnings for creation of implicit declarations. For
 example, if a scalar wire X is used but not declared in the Verilog
 source, this will print a warning at its first use.
 
+.TP 8
+.B macro-redefinition\fI | \fPmacro-replacement
+This enables preprocessor warnings when a macro is being redefined.
+The first variant prints a warning any time a macro is redefined.
+The second variant only prints a warning if the macro text changes.
+Use \fBno-macro-redefinition\fP to turn off all warnings of this type.
+
 .TP 8
 .B portbind
 This enables warnings for ports of module instantiations that are not
@@ -346,13 +416,23 @@ sensitivity list. Although this behaviour is prescribed by the IEEE
 standard, it is not what might be expected and can have performance
 implications if the array is large.
 
-.SH "SYSTEM FUNCTION TABLE FILES"
-If the source file name as a \fB.sft\fP suffix, then it is taken to be
-a system function table file. A System function table file is used to
-describe to the compiler the return types for system functions. This
+.SH "VPI MODULES"
+If the source file name has a \fB.vpi\fP or \fB.vpl\fP suffix, then it
+is taken to be a VPI module. VPI modules supplied by the user are scanned
+to determine the return types of any system functions they provide. This
 is necessary because the compiler needs this information to elaborate
-expressions that contain these system functions, but cannot run the
-sizetf functions since it has no run-time.
+expressions that contain these system functions. The module path/name is
+passed on to the target to allow the VPI module to be automatically loaded
+at the start of simulation.
+
+VPI modules may also be supplied using the \fB-L\fP and \fB-m\fP options.
+
+.SH "SYSTEM FUNCTION TABLE FILES [deprecated]"
+If the source file name has a \fB.sft\fP suffix, then it is taken to be a
+system function table file. A system function table file is the old method
+used to describe to the compiler the return types for system functions.
+Users are encouraged to switch to the new method of simply supplying the
+VPI module.
 
 The format of the table is ASCII, one function per line. Empty lines
 are ignored, and lines that start with the '\fI#\fP' character are
@@ -373,6 +453,11 @@ The function returns an integer.
 The function returns a vector with the given width, and is signed or
 unsigned according to the flag.
 
+.TP 8
+.B vpiSysFuncString
+The function returns a string. This is an Icarus-specific extension, not
+available in the VPI standard.
+
 .SH "COMMAND FILES"
 The command file allows the user to place source file names and
 certain command line switches into a text file instead of on a long
@@ -391,6 +476,15 @@ A \fB\-c\fP or \fB\-f\fP token prefixes a command file, exactly like it
 does on the command line. The cmdfile may be on the same line or the
 next non-comment line.
 
+.TP 8
+.B -l\ \fIfile\fP -v\ \fIfile\fP
+A \fB\-l\fP token prefixes a library file in the command file,
+exactly like it does on the command line. The parameter to the \fB\-l\fP
+flag may be on the same line or the next non-comment line. \fB\-v\fP is
+an alias for \fB\-l\fP, provided for compatibility with other simulators.
+
+Variables in the \fIfile\fP are substituted.
+
 .TP 8
 .B -y\ \fIlibdir\fP
 A \fB\-y\fP token prefixes a library directory in the command file,
@@ -411,7 +505,7 @@ Variables in the \fIincludedir\fP are substituted.
 
 .TP 8
 .B +libext+\fIext\fP
-The \fB+libext\fP token in command files fives file extensions to try
+The \fB+libext\fP token in command files lists file extensions to try
 when looking for a library file. This is useful in conjunction with
 \fB\-y\fP flags to list suffixes to try in each directory before moving
 on to the next library directory.
@@ -488,9 +582,31 @@ The following macros are predefined by the compiler:
 .B __ICARUS__ = 1
 This is always defined when compiling with Icarus Verilog.
 
+.TP 8
+.B __ICARUS_SYNTH__ = 1
+This is defined when synthesis is enabled.
+
 .TP 8
 .B __VAMS_ENABLE__ = 1
-This is defined if Verilog\-AMS is enabled.
+This is defined when Verilog\-AMS is enabled.
+
+.SH ENVIRONMENT
+.PP
+\fIiverilog\fP also accepts some environment variables that control
+its behavior. These can be used to make semi-permanent changes.
+
+.TP 8
+.B IVERILOG_ICONFIG=\fIfile-name\fP
+This sets the name used for the temporary file that passes parameters
+to the compiler proper, and prevents that file being deleted after the
+compiler has exited.
+
+.TP 8
+.B IVERILOG_VPI_MODULE_PATH=\fI/some/path:/some/other/path\fP
+This adds additional components to the VPI module search path. Paths
+specified in this way are searched after paths specified with \fB-L\fP,
+but before the default search path. Multiple paths can be separated with
+colons (semicolons if using Windows).
 
 .SH EXAMPLES
 These examples assume that you have a Verilog source file called hello.v in
@@ -514,14 +630,14 @@ Steve Williams ([email protected])
 
 .SH SEE ALSO
 vvp(1),
-.BR "<http://www.icarus.com/eda/verilog/>"
+.BR "<http://iverilog.icarus.com/>"
 
 Tips on using, debugging, and developing the compiler can be found at
 .BR "<http://iverilog.wikia.com/>"
 
 .SH COPYRIGHT
 .nf
-Copyright \(co  2002\-2014 Stephen Williams
+Copyright \(co  2002\-2021 Stephen Williams
 
 This document can be freely redistributed according to the terms of the
 GNU General Public License version 2.0

driver/main.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2000-2014 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 2000-2021 Stephen Williams (steve@icarus.com)
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -38,13 +38,13 @@ const char NOTICE[] =
 ;
 
 const char HELP[] =
-"Usage: iverilog [-ESvV] [-B base] [-c cmdfile|-f cmdfile]\n"
+"Usage: iverilog [-EiSuvV] [-B base] [-c cmdfile|-f cmdfile]\n"
 "                [-g1995|-g2001|-g2005|-g2005-sv|-g2009|-g2012] [-g<feature>]\n"
-"                [-D macro[=defn]] [-I includedir]\n"
+"                [-D macro[=defn]] [-I includedir] [-L moduledir]\n"
 "                [-M [mode=]depfile] [-m module]\n"
 "                [-N file] [-o filename] [-p flag=value]\n"
 "                [-s topmodule] [-t target] [-T min|typ|max]\n"
-"                [-W class] [-y dir] [-Y suf] source_file(s)\n"
+"                [-W class] [-y dir] [-Y suf] [-l file] source_file(s)\n"
 "\n"
 "See the man page for details.";
 
@@ -99,13 +99,16 @@ extern const char*optarg;
 
 #ifdef __MINGW32__
 const char sep = '\\';
+const char path_sep = ';';
 #else
 const char sep = '/';
+const char path_sep = ':';
 #endif
 
 extern void cfreset(FILE*fd, const char*path);
 
 const char*base = 0;
+const char*vpi_dir = 0;
 const char*ivlpp_dir = 0;
 const char*vhdlpp_dir= 0;
 const char*vhdlpp_work = 0;
@@ -128,6 +131,7 @@ const char*gen_icarus = "icarus-misc";
 const char*gen_io_range_error = "io-range-error";
 const char*gen_strict_ca_eval = "no-strict-ca-eval";
 const char*gen_strict_expr_width = "no-strict-expr-width";
+const char*gen_shared_loop_index = "shared-loop-index";
 const char*gen_verilog_ams = "no-verilog-ams";
 
 /* Boolean: true means use a default include dir, false means don't */
@@ -137,7 +141,12 @@ int gen_std_include = 1;
    of the include list. */
 int gen_relative_include = 0;
 
-char warning_flags[16] = "n";
+char warning_flags[17] = "n";
+
+int separate_compilation_flag = 0;
+
+/* Boolean: true means ignore errors about missing modules */
+int ignore_missing_modules = 0;
 
 unsigned integer_width = 32;
 
@@ -163,13 +172,19 @@ char*compiled_defines_path = 0;
 
 static char iconfig_common_path[4096] = "";
 
+static const char**vpi_path_list = 0;
+static unsigned vpi_path_list_size = 0;
+
+static const char**env_vpi_path_list = 0;
+static unsigned env_vpi_path_list_size = 0;
+
 int synth_flag = 0;
 int verbose_flag = 0;
 
 FILE *fp;
 
 char line[MAXSIZE];
-char tmp[MAXSIZE];
+char tmp[MAXSIZE+24];
 
 static char ivl_root[MAXSIZE];
 
@@ -340,10 +355,15 @@ static int t_version_only(void)
 
 static void build_preprocess_command(int e_flag)
 {
-      snprintf(tmp, sizeof tmp, "%s%civlpp %s%s -F\"%s\" -f\"%s\" -p\"%s\" ",
-	       ivlpp_dir, sep, verbose_flag?" -v":"",
-	       e_flag?"":" -L", defines_path, source_path,
-	       compiled_defines_path);
+      snprintf(tmp, sizeof tmp, "%s%civlpp %s%s%s -F\"%s\" -f\"%s\" -p\"%s\"%s",
+	       ivlpp_dir, sep,
+               verbose_flag ? " -v" : "",
+	       e_flag ? "" : " -L",
+               strchr(warning_flags, 'r') ? " -Wredef-all " :
+               strchr(warning_flags, 'R') ? " -Wredef-chg " : "",
+               defines_path, source_path,
+	       compiled_defines_path,
+	       e_flag ? "" : " | ");
 }
 
 static int t_preprocess_only(void)
@@ -406,8 +426,12 @@ static int t_compile(void)
 {
       unsigned rc;
 
-	/* Start by building the preprocess command line. */
-      build_preprocess_command(0);
+	/* Start by building the preprocess command line, if required.
+	   This pipes into the main ivl command. */
+      if (!separate_compilation_flag)
+	    build_preprocess_command(0);
+      else
+	    strcpy(tmp, "");
 
       size_t ncmd = strlen(tmp);
       char*cmd = malloc(ncmd + 1);
@@ -417,8 +441,8 @@ static int t_compile(void)
       int rtn;
 #endif
 
-	/* Build the ivl command and pipe it to the preprocessor. */
-      snprintf(tmp, sizeof tmp, " | %s%civl", base, sep);
+	/* Build the ivl command. */
+      snprintf(tmp, sizeof tmp, "%s%civl", base, sep);
       rc = strlen(tmp);
       cmd = realloc(cmd, ncmd+rc+1);
       strcpy(cmd+ncmd, tmp);
@@ -446,7 +470,16 @@ static int t_compile(void)
       strcpy(cmd+ncmd, tmp);
       ncmd += rc;
 
-      snprintf(tmp, sizeof tmp, " -C\"%s\" -- -", iconfig_common_path);
+      snprintf(tmp, sizeof tmp, " -C\"%s\"", iconfig_common_path);
+      rc = strlen(tmp);
+      cmd = realloc(cmd, ncmd+rc+1);
+      strcpy(cmd+ncmd, tmp);
+      ncmd += rc;
+
+      if (separate_compilation_flag)
+	    snprintf(tmp, sizeof tmp, " -F\"%s\"", source_path);
+      else
+	    snprintf(tmp, sizeof tmp, " -- -");
       rc = strlen(tmp);
       cmd = realloc(cmd, ncmd+rc+1);
       strcpy(cmd+ncmd, tmp);
@@ -496,6 +529,8 @@ static void process_warning_switch(const char*name)
       if (strcmp(name,"all") == 0) {
 	    process_warning_switch("anachronisms");
 	    process_warning_switch("implicit");
+	    process_warning_switch("implicit-dimensions");
+	    process_warning_switch("macro-replacement");
 	    process_warning_switch("portbind");
 	    process_warning_switch("select-range");
 	    process_warning_switch("timescale");
@@ -503,9 +538,21 @@ static void process_warning_switch(const char*name)
       } else if (strcmp(name,"anachronisms") == 0) {
 	    if (! strchr(warning_flags, 'n'))
 		  strcat(warning_flags, "n");
+      } else if (strcmp(name,"floating-nets") == 0) {
+	    if (! strchr(warning_flags, 'f'))
+		  strcat(warning_flags, "f");
       } else if (strcmp(name,"implicit") == 0) {
 	    if (! strchr(warning_flags, 'i'))
 		  strcat(warning_flags, "i");
+      } else if (strcmp(name,"implicit-dimensions") == 0) {
+	    if (! strchr(warning_flags, 'd'))
+		  strcat(warning_flags, "d");
+      } else if (strcmp(name,"macro-redefinition") == 0) {
+	  if (! strchr(warning_flags, 'r'))
+		  strcat(warning_flags, "r");
+      } else if (strcmp(name,"macro-replacement") == 0) {
+	  if (! strchr(warning_flags, 'R'))
+		  strcat(warning_flags, "R");
       } else if (strcmp(name,"portbind") == 0) {
 	    if (! strchr(warning_flags, 'p'))
 		  strcat(warning_flags, "p");
@@ -532,12 +579,35 @@ static void process_warning_switch(const char*name)
 		  cp[0] = cp[1];
 		  cp += 1;
 	    }
+      } else if (strcmp(name,"no-floating-nets") == 0) {
+	    char*cp = strchr(warning_flags, 'f');
+	    if (cp) while (*cp) {
+		  cp[0] = cp[1];
+		  cp += 1;
+	    }
       } else if (strcmp(name,"no-implicit") == 0) {
 	    char*cp = strchr(warning_flags, 'i');
 	    if (cp) while (*cp) {
 		  cp[0] = cp[1];
 		  cp += 1;
 	    }
+      } else if (strcmp(name,"no-implicit-dimensions") == 0) {
+	    char*cp = strchr(warning_flags, 'd');
+	    if (cp) while (*cp) {
+		  cp[0] = cp[1];
+		  cp += 1;
+	    }
+      } else if (strcmp(name,"no-macro-redefinition") == 0) {
+	    char*cp = strchr(warning_flags, 'r');
+	    if (cp) while (*cp) {
+		  cp[0] = cp[1];
+		  cp += 1;
+	    }
+	    cp = strchr(warning_flags, 'R');
+	    if (cp) while (*cp) {
+		  cp[0] = cp[1];
+		  cp += 1;
+	    }
       } else if (strcmp(name,"no-portbind") == 0) {
 	    char*cp = strchr(warning_flags, 'p');
 	    if (cp) while (*cp) {
@@ -568,6 +638,9 @@ static void process_warning_switch(const char*name)
 		  cp[0] = cp[1];
 		  cp += 1;
 	    }
+      } else {
+	    fprintf(stderr, "Ignoring unknown warning class "
+		    "%s\n", name);
       }
 }
 
@@ -609,14 +682,19 @@ void process_timescale(const char*ts_string)
 /*
  * This function is called while processing a file name in a command
  * file, or a file name on the command line. Look to see if there is a
- * .sft suffix, and if so pass that as a sys_func file. Otherwise, it
- * is a Verilog source file to be written into the file list.
+ * .sft or .vpi suffix, and if so pass that as a sys_func or module
+ * file. Otherwise, it is a Verilog source file to be written into the
+ * file list.
  */
 void process_file_name(const char*name, int lib_flag)
 {
       if (strlen(name) > 4 && strcasecmp(".sft", name+strlen(name)-4) == 0) {
+	    fprintf(stderr, "SFT files are deprecated. Please pass the VPI module instead.\n");
 	    fprintf(iconfig_file,"sys_func:%s\n", name);
 
+      } else if (strlen(name) > 4 && strcasecmp(".vpi", name+strlen(name)-4) == 0) {
+	    fprintf(iconfig_file,"module:%s\n", name);
+
       } else {
 	    fprintf(source_file, "%s\n", name);
 	    source_count += 1;
@@ -684,6 +762,9 @@ static int process_generation(const char*name)
       else if (strcmp(name,"assertions") == 0)
 	    gen_assertions = "assertions";
 
+      else if (strcmp(name,"supported-assertions") == 0)
+	    gen_assertions = "supported-assertions";
+
       else if (strcmp(name,"no-assertions") == 0)
 	    gen_assertions = "no-assertions";
 
@@ -717,6 +798,12 @@ static int process_generation(const char*name)
       else if (strcmp(name,"no-strict-expr-width") == 0)
 	    gen_strict_expr_width = "no-strict-expr-width";
 
+      else if (strcmp(name,"shared-loop-index") == 0)
+	    gen_shared_loop_index = "shared-loop-index";
+
+      else if (strcmp(name,"no-shared-loop-index") == 0)
+	    gen_shared_loop_index = "no-shared-loop-index";
+
       else if (strcmp(name,"verilog-ams") == 0)
 	    gen_verilog_ams = "verilog-ams";
 
@@ -734,6 +821,7 @@ static int process_generation(const char*name)
 		            "    2009    -- IEEE1800-2009\n"
 		            "    2012    -- IEEE1800-2012\n"
 		            "Other generation flags:\n"
+		            "    assertions | supported-assertions | no-assertions\n"
 		            "    specify | no-specify\n"
 		            "    verilog-ams | no-verilog-ams\n"
 		            "    std-include | no-std-include\n"
@@ -742,7 +830,8 @@ static int process_generation(const char*name)
 		            "    icarus-misc | no-icarus-misc\n"
 		            "    io-range-error | no-io-range-error\n"
 		            "    strict-ca-eval | no-strict-ca-eval\n"
-		            "    strict-expr-width | no-strict-expr-width\n");
+		            "    strict-expr-width | no-strict-expr-width\n"
+		            "    shared-loop-index | no-shared-loop-index\n");
 
 	    return 1;
       }
@@ -781,18 +870,224 @@ static int process_depfile(const char*name)
       return 0;
 }
 
-/*
- * If it exists add the SFT file for the given module.
- */
-static void add_sft_file(const char *module)
+static void add_env_vpi_module_path(const char*path)
 {
-      char *file;
+      env_vpi_path_list_size += 1;
+      env_vpi_path_list = (const char**)realloc(env_vpi_path_list,
+					  env_vpi_path_list_size*sizeof(char*));
+      env_vpi_path_list[env_vpi_path_list_size-1] = path;
+}
 
-      file = (char *) malloc(strlen(base)+1+strlen(module)+4+1);
-      sprintf(file, "%s%c%s.sft", base, sep, module);
-      if (access(file, R_OK) == 0)
-            fprintf(iconfig_file, "sys_func:%s\n", file);
-      free(file);
+static void get_env_vpi_module_paths(void)
+{
+      char *var = getenv("IVERILOG_VPI_MODULE_PATH");
+      char *ptr, *end;
+
+      if (!var)
+	    return;
+
+      var = strdup(var);
+#ifdef __MINGW32__
+      convert_to_MS_path(var);
+#endif
+      ptr = var;
+      end = var+strlen(var);
+      int len = 0;
+      while (ptr <= end) {
+	    if (*ptr == 0 || *ptr == path_sep) {
+		  *ptr = 0;
+		  if (len > 0) {
+		       add_env_vpi_module_path(var);
+		  }
+		  len = 0;
+		  var = ptr+1;
+	    } else {
+		  len++;
+	    }
+	    ptr++;
+      }
+}
+
+static void add_vpi_module_path(const char*path)
+{
+#ifdef __MINGW32__
+      char*tmp_path = strdup(path);
+      convert_to_MS_path(tmp_path);
+      path = tmp_path;
+#endif
+      vpi_path_list_size += 1;
+      vpi_path_list = (const char**)realloc(vpi_path_list,
+				      vpi_path_list_size*sizeof(char*));
+      vpi_path_list[vpi_path_list_size-1] = path;
+}
+
+static int probe_for_vpi_module(const char*base_path, const char*name,
+				char*path, unsigned path_size)
+{
+      snprintf(path, path_size, "%s%c%s.vpi", base_path, sep, name);
+      if (access(path, R_OK) == 0)
+	    return 1;
+
+      snprintf(path, path_size, "%s%c%s.vpl", base_path, sep, name);
+      if (access(path, R_OK) == 0)
+	    return 1;
+
+      return 0;
+}
+
+/*
+ * If it exists add the VPI file for the given module.
+ */
+static void add_vpi_file(const char *name)
+{
+      const char*base_dir = vpi_dir ? vpi_dir : base;
+
+      char path[4096];
+
+#ifdef __MINGW32__
+      char*tmp_name = strdup(name);
+      convert_to_MS_path(tmp_name);
+      name = tmp_name;
+#endif
+
+      int found = 0;
+      if (strchr(name, sep)) {
+	      /* If the name has at least one directory character in it
+		 then assume it is a complete name, maybe including any
+		 possible .vpi or .vpl suffix. */
+	    found = access(name, R_OK) == 0;
+	    if (!found) {
+		  snprintf(path, sizeof(path), "%s.vpi", name);
+		  found = access(path, R_OK) == 0;
+		  if (!found) {
+			snprintf(path, sizeof(path), "%s.vpl", name);
+			found = access(path, R_OK) == 0;
+		  }
+	    } else {
+		  strncpy(path, name, sizeof(path) - 1);
+	    }
+      } else {
+	    for (unsigned idx = 0; !found && (idx < vpi_path_list_size); idx += 1) {
+		  found = probe_for_vpi_module(vpi_path_list[idx], name,
+					       path, sizeof(path));
+	    }
+	    for (unsigned idx = 0; !found && (idx < env_vpi_path_list_size); idx += 1) {
+		  found = probe_for_vpi_module(env_vpi_path_list[idx], name,
+					       path, sizeof(path));
+	    }
+	    if (!found) {
+		  found = probe_for_vpi_module(base_dir, name,
+					       path, sizeof(path));
+	    }
+      }
+      if (found) {
+	    fprintf(iconfig_file, "module:%s\n", path);
+      } else {
+	    fprintf(stderr, "Unable to find VPI module '%s'\n", name);
+      }
+#ifdef __MINGW32__
+      free(tmp_name);
+#endif
+}
+
+static void find_ivl_root_failed(const char *reason)
+{
+      fprintf(stderr, "Cannot locate IVL modules : %s\n", reason);
+      exit(1);
+}
+
+static void find_ivl_root(void)
+{
+#ifdef __MINGW32__
+      const char *ivl_lib_prefix = "\\lib";
+      const char *ivl_lib_suffix = "\\ivl" IVL_SUFFIX;
+#else
+      const char *ivl_lib_prefix = IVL_LIB;
+      const char *ivl_lib_suffix = "/ivl" IVL_SUFFIX;
+#endif
+      ssize_t len = 0;
+      char *s;
+
+#ifndef __MINGW32__
+	/* First try the location specified in the build process. */
+      if (access(IVL_ROOT, F_OK) != -1) {
+	    assert(strlen(IVL_ROOT) < sizeof ivl_root);
+	    strcpy(ivl_root, IVL_ROOT);
+	    return;
+      }
+#endif
+	/* If that fails, calculate the ivl_root from the path to the
+	   command. This is always necessary on Windows because of the
+	   installation process, but may also be necessary on other OSs
+	   if the package has been relocated.
+
+	   On Windows we know the command path is formed like this:
+
+		$(prefix)\bin\iverilog.exe
+
+	   The module path in a Windows installation is the path:
+
+		$(prefix)\lib\ivl$(suffix)
+
+	   so we chop the file name and the last directory by
+	   turning the last two \ characters to null. Then we append
+	   the lib\ivl$(suffix) to finish.
+
+	   On other OSs, we expect the command path to be:
+
+		$(prefix)/bin/iverilog
+
+	   and the module path to be:
+
+		$(prefix)/$(lib)/ivl$(suffix)
+
+	   so we extract the $(prefix) from the command location as for
+	   Windows and the $(lib) from IVL_LIB. This will of course fail
+	   if the user has overridden $(bindir) or $(libdir), but there's
+	   not a lot we can do in that case.
+ */
+#if defined(__MINGW32__)
+      char tmppath[MAXSIZE];
+      len = GetModuleFileName(NULL, tmppath, sizeof tmppath);
+      if (len >= (ssize_t) sizeof ivl_root) {
+	    find_ivl_root_failed("command path exceeds size of string buffer.");
+      }
+	/* Convert to a short name to remove any embedded spaces. */
+      len = GetShortPathName(tmppath, ivl_root, sizeof ivl_root);
+#elif defined(__APPLE__)
+	  uint32_t size = sizeof ivl_root;
+	  len = _NSGetExecutablePath(ivl_root, &size) + 1;
+#else
+      len = readlink("/proc/self/exe", ivl_root, sizeof ivl_root);
+#endif
+      if (len >= (ssize_t) sizeof ivl_root) {
+	    find_ivl_root_failed("command path exceeds size of string buffer.");
+      }
+      if (len <= 0) {
+	      // We've failed, but we may yet find a -B option on the command line.
+	      // Use the built-in path so the user sees a sensible error message.
+	    assert(strlen(IVL_ROOT) < sizeof ivl_root);
+	    strcpy(ivl_root, IVL_ROOT);
+	    return;
+      }
+      s = strrchr(ivl_root, sep);
+      if (s == 0) {
+	    find_ivl_root_failed("missing first separator in command path.");
+      }
+      *s = 0;
+      s = strrchr(ivl_root, sep);
+      if (s == 0) {
+	    find_ivl_root_failed("missing second separator in command path.");
+      }
+      *s = 0;
+      len = s - ivl_root;
+      s = strrchr(ivl_lib_prefix, sep);
+      assert(s);
+      if (len + strlen(s) + strlen(ivl_lib_suffix) >= (ssize_t) sizeof ivl_root) {
+	    find_ivl_root_failed("module path exceeds size of string buffer.");
+      }
+      strcat(ivl_root, s);
+      strcat(ivl_root, ivl_lib_suffix);
 }
 
 int main(int argc, char **argv)
@@ -801,51 +1096,10 @@ int main(int argc, char **argv)
       int version_flag = 0;
       int opt;
 
-#ifdef __MINGW32__
-	/* Calculate the ivl_root from the path to the command. This
-	   is necessary because of the installation process on
-	   Windows. Mostly, it is those darn drive letters, but oh
-	   well. We know the command path is formed like this:
-
-		D:\iverilog\bin\iverilog.exe
-
-	   The module path in a Windows installation is the path:
-
-		D:\iverilog\lib\ivl$(suffix)
-
-	   so we chop the file name and the last directory by
-	   turning the last two \ characters to null. Then we append
-	   the lib\ivl$(suffix) to finish. */
-      char *s;
-      char tmppath[MAXSIZE];
-      GetModuleFileName(NULL, tmppath, sizeof tmppath);
-	/* Convert to a short name to remove any embedded spaces. */
-      GetShortPathName(tmppath, ivl_root, sizeof ivl_root);
-      s = strrchr(ivl_root, sep);
-      if (s) *s = 0;
-      else {
-	    fprintf(stderr, "%s: Missing first %c in exe path!\n",
-	                    argv[0], sep);
-	    exit(1);
-      }
-      s = strrchr(ivl_root, sep);
-      if (s) *s = 0;
-      else {
-	    fprintf(stderr, "%s: Missing second %c in exe path!\n",
-	                    argv[0], sep);
-	    exit(1);
-      }
-      strcat(ivl_root, "\\lib\\ivl" IVL_SUFFIX);
-
+      find_ivl_root();
       base = ivl_root;
 
-#else
-        /* In a UNIX environment, the IVL_ROOT from the Makefile is
-	   dependable. It points to the $prefix/lib/ivl directory,
-	   where the sub-parts are installed. */
-      strcpy(ivl_root, IVL_ROOT);
-      base = ivl_root;
-#endif
+      get_env_vpi_module_paths();
 
 	/* Create a temporary file for communicating input parameters
 	   to the preprocessor. */
@@ -869,8 +1123,6 @@ int main(int argc, char **argv)
       }
 
       fprintf(defines_file, "D:__ICARUS__=1\n");
-      if (strcmp(gen_verilog_ams,"verilog-ams") == 0)
-	    fprintf(defines_file, "D:__VAMS_ENABLE__=1\n");
 
 	/* Create another temporary file for passing configuration
 	   information to ivl. */
@@ -907,7 +1159,7 @@ int main(int argc, char **argv)
 	}
       }
 
-      while ((opt = getopt(argc, argv, "B:c:D:d:Ef:g:hI:M:m:N:o:P:p:Ss:T:t:vVW:y:Y:")) != EOF) {
+      while ((opt = getopt(argc, argv, "B:c:D:d:Ef:g:hl:I:iL:M:m:N:o:P:p:Ss:T:t:uvVW:y:Y:")) != EOF) {
 
 	    switch (opt) {
 		case 'B':
@@ -916,6 +1168,9 @@ int main(int argc, char **argv)
 		       character of the path indicates which path the
 		       user is specifying. */
 		  switch (optarg[0]) {
+		      case 'M': /* Path for the VPI modules */
+			vpi_dir = optarg+1;
+			break;
 		      case 'P': /* Path for the ivlpp preprocessor */
 			ivlpp_dir = optarg+1;
 			break;
@@ -962,14 +1217,25 @@ int main(int argc, char **argv)
 		  process_include_dir(optarg);
 		  break;
 
+		case 'i':
+		  ignore_missing_modules = 1;
+		  break;
+
+		case 'L':
+		  add_vpi_module_path(optarg);
+		  break;
+
+		case 'l':
+		  process_file_name(optarg, 1);
+		  break;
+
 		case 'M':
 		  if (process_depfile(optarg) != 0)
                         return -1;
 		  break;
 
 		case 'm':
-		  fprintf(iconfig_file, "module:%s\n", optarg);
-		  add_sft_file(optarg);
+		  add_vpi_file(optarg);
 		  break;
 
 		case 'N':
@@ -1002,6 +1268,9 @@ int main(int argc, char **argv)
 		case 't':
 		  targ = optarg;
 		  break;
+		case 'u':
+		  separate_compilation_flag = 1;
+		  break;
 		case 'v':
 		  verbose_flag = 1;
 		  break;
@@ -1037,6 +1306,13 @@ int main(int argc, char **argv)
 	    }
       }
 
+      if (strcmp(gen_verilog_ams,"verilog-ams") == 0)
+	    fprintf(defines_file, "D:__VAMS_ENABLE__=1\n");
+      if (synth_flag)
+	    fprintf(defines_file, "D:__ICARUS_SYNTH__=1\n");
+
+      if (vpi_dir == 0)
+	    vpi_dir = base;
       if (ivlpp_dir == 0)
 	    ivlpp_dir = base;
       if (vhdlpp_dir == 0)
@@ -1044,19 +1320,10 @@ int main(int argc, char **argv)
 
       if (version_flag || verbose_flag) {
 	    printf("Icarus Verilog version " VERSION " (" VERSION_TAG ")\n\n");
-	    printf("Copyright 1998-2013 Stephen Williams\n\n");
+	    printf("Copyright 1998-2020 Stephen Williams\n\n");
 	    puts(NOTICE);
       }
 
-      if (synth_flag) {
-	    fprintf(stderr, "Warning: Synthesis is not currently being "
-	                    "maintained and may not\n");
-	    fprintf(stderr, "         function correctly. V0.8 was the "
-	                    "last release branch to\n");
-	    fprintf(stderr, "         have active synthesis development "
-	                    "and support!\n");
-      }
-
 	/* Make a common conf file path to reflect the target. */
       snprintf(iconfig_common_path, sizeof iconfig_common_path, "%s%c%s%s.conf",
 	      base, sep, targ, synth_flag? "-s" : "");
@@ -1064,11 +1331,10 @@ int main(int argc, char **argv)
 	/* Write values to the iconfig file. */
       fprintf(iconfig_file, "basedir:%s\n", base);
 
-	/* Tell the core where to find the system.sft. This file
-	   describes the system functions so that elaboration knows
-	   how to handle them. */
-      fprintf(iconfig_file, "sys_func:%s%csystem.sft\n", base, sep);
-      fprintf(iconfig_file, "sys_func:%s%cvhdl_sys.sft\n", base, sep);
+	/* Tell the core where to find the system VPI modules. */
+      fprintf(iconfig_file, "module:%s%csystem.vpi\n", vpi_dir, sep);
+      fprintf(iconfig_file, "module:%s%cvhdl_sys.vpi\n", vpi_dir, sep);
+      fprintf(iconfig_file, "module:%s%cvhdl_textio.vpi\n", vpi_dir, sep);
 
 	/* If verilog-2005/09/12 is enabled or icarus-misc or verilog-ams,
 	 * then include the v2005_math library. */
@@ -1077,23 +1343,20 @@ int main(int argc, char **argv)
           strcmp(generation, "2012") == 0 ||
           strcmp(gen_icarus, "icarus-misc") == 0 ||
           strcmp(gen_verilog_ams, "verilog-ams") == 0) {
-	    fprintf(iconfig_file, "sys_func:%s%cv2005_math.sft\n", base, sep);
-	    fprintf(iconfig_file, "module:v2005_math\n");
+	    fprintf(iconfig_file, "module:%s%cv2005_math.vpi\n", vpi_dir, sep);
       }
 	/* If verilog-ams or icarus_misc is enabled, then include the
 	 * va_math module as well. */
       if (strcmp(gen_verilog_ams,"verilog-ams") == 0 ||
           strcmp(gen_icarus, "icarus-misc") == 0) {
-	    fprintf(iconfig_file, "sys_func:%s%cva_math.sft\n", base, sep);
-	    fprintf(iconfig_file, "module:va_math\n");
+	    fprintf(iconfig_file, "module:%s%cva_math.vpi\n", vpi_dir, sep);
       }
       /* If verilog-2009 (SystemVerilog) is enabled, then include the
          v2009 module. */
       if (strcmp(generation, "2005-sv") == 0 ||
           strcmp(generation, "2009") == 0 ||
           strcmp(generation, "2012") == 0) {
-	    fprintf(iconfig_file, "sys_func:%s%cv2009.sft\n", base, sep);
-	    fprintf(iconfig_file, "module:v2009\n");
+	    fprintf(iconfig_file, "module:%s%cv2009.vpi\n", vpi_dir, sep);
       }
 
       if (mtm != 0) fprintf(iconfig_file, "-T:%s\n", mtm);
@@ -1104,9 +1367,11 @@ int main(int argc, char **argv)
       fprintf(iconfig_file, "generation:%s\n", gen_io_range_error);
       fprintf(iconfig_file, "generation:%s\n", gen_strict_ca_eval);
       fprintf(iconfig_file, "generation:%s\n", gen_strict_expr_width);
+      fprintf(iconfig_file, "generation:%s\n", gen_shared_loop_index);
       fprintf(iconfig_file, "generation:%s\n", gen_verilog_ams);
       fprintf(iconfig_file, "generation:%s\n", gen_icarus);
       fprintf(iconfig_file, "warnings:%s\n", warning_flags);
+      fprintf(iconfig_file, "ignore_missing_modules:%s\n", ignore_missing_modules ? "true" : "false");
       fprintf(iconfig_file, "out:%s\n", opath);
       if (depfile) {
             fprintf(iconfig_file, "depfile:%s\n", depfile);
@@ -1183,8 +1448,12 @@ int main(int argc, char **argv)
 	   will append to the file, so this is necessary to make sure
 	   it starts out empty. */
       if (depfile) {
-	    FILE*fd = fopen(depfile, "w");
-	    fclose(fd);
+            FILE *fd = fopen(depfile, "w");
+            if (!fd) {
+                  fprintf(stderr, "%s: can't open %s file.\n\n%s\n", argv[0], depfile, HELP);
+                  return 1;
+            }
+            fclose(fd);
       }
 
       if (source_count == 0 && !version_flag) {
@@ -1199,8 +1468,12 @@ int main(int argc, char **argv)
 	/* Write the preprocessor command needed to preprocess a
 	   single file. This may be used to preprocess library
 	   files. */
-      fprintf(iconfig_file, "ivlpp:%s%civlpp -L -F\"%s\" -P\"%s\"\n",
-	      ivlpp_dir, sep, defines_path, compiled_defines_path);
+      fprintf(iconfig_file, "ivlpp:%s%civlpp %s -L -F\"%s\" -P\"%s\"\n",
+	      ivlpp_dir, sep,
+              strchr(warning_flags, 'r') ? "-Wredef-all" :
+              strchr(warning_flags, 'R') ? "-Wredef-chg" : "",
+              defines_path, compiled_defines_path
+      );
 
 	/* Done writing to the iconfig file. Close it now. */
       fclose(iconfig_file);

dup_expr.cc

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1999-2013 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 1999-2021 Stephen Williams (steve@icarus.com)
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -24,6 +24,8 @@
 # include  <cstdlib>
 # include  "ivl_assert.h"
 
+using namespace std;
+
 NetEAccess* NetEAccess::dup_expr() const
 {
       NetEAccess*tmp = new NetEAccess(branch_, nature_);
@@ -233,7 +235,7 @@ NetESelect* NetESelect::dup_expr() const
 
 NetESFunc* NetESFunc::dup_expr() const
 {
-      NetESFunc*tmp = new NetESFunc(name_, type_, expr_width(), nparms());
+      NetESFunc*tmp = new NetESFunc(name_, type_, expr_width(), nparms(), is_overridden_);
       ivl_assert(*this, tmp);
 
       tmp->cast_signed(has_sign());

elab_anet.cc

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2000-2003 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 2000-2021 Stephen Williams (steve@icarus.com)
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -29,6 +29,8 @@
 # include  "netmisc.h"
 # include  <iostream>
 
+using namespace std;
+
 NetNet* PExpr::elaborate_anet(Design*des, NetScope*scope) const
 {
       cerr << get_line() << ": error: Invalid expression on left side "
@@ -163,4 +165,3 @@ NetNet* PEIdent::elaborate_anet(Design*des, NetScope*scope) const
 
       return sig;
 }
-

elab_net.cc

@@ -32,6 +32,8 @@
 # include  <iostream>
 # include  "ivl_assert.h"
 
+using namespace std;
+
 /*
  * The concatenation is also OK an an l-value. This method elaborates
  * it as a structural l-value. The return values is the *input* net of
@@ -262,49 +264,87 @@ bool PEIdent::eval_part_select_(Design*des, NetScope*scope, NetNet*sig,
 		}
 
 		long midx_val = tmp->value().as_long();
-		midx = sig->sb_to_idx(prefix_indices, midx_val);
 		delete tmp_ex;
+		if (prefix_indices.size()+1 < sig->packed_dims().size()) {
+			// Here we are selecting one or more sub-arrays.
+			// Make this work by finding the indexed sub-arrays and
+			// creating a generated slice that spans the whole range.
+		      long loff, moff;
+		      unsigned long lwid, mwid;
+		      bool mrc, lrc;
+		      mrc = sig->sb_to_slice(prefix_indices, midx_val, moff, mwid);
+		      if (index_tail.sel == index_component_t::SEL_IDX_UP)
+			    lrc = sig->sb_to_slice(prefix_indices, midx_val+wid-1, loff, lwid);
+		      else
+			    lrc = sig->sb_to_slice(prefix_indices, midx_val-wid+1, loff, lwid);
+		      if (!mrc || !lrc) {
+			    cerr << get_fileline() << ": error: ";
+			    cerr << "Part-select [" << midx_val;
+			    if (index_tail.sel == index_component_t::SEL_IDX_UP) {
+				  cerr << "+:";
+			    } else {
+				  cerr << "-:";
+			    }
+			    cerr << wid << "] exceeds the declared bounds for ";
+			    cerr << sig->name();
+			    if (sig->unpacked_dimensions() > 0) cerr << "[]";
+			    cerr << "." << endl;
+			    des->errors += 1;
+			    return 0;
+		      }
+		      ivl_assert(*this, lwid == mwid);
 
-		if (index_tail.sel == index_component_t::SEL_IDX_UP)
-		      lidx = sig->sb_to_idx(prefix_indices, midx_val+wid-1);
-		else
-		      lidx = sig->sb_to_idx(prefix_indices, midx_val-wid+1);
-
-		if (midx < lidx) {
-		      long tmpx = midx;
-		      midx = lidx;
-		      lidx = tmpx;
-		}
-
-		  /* Warn about an indexed part select that is out of range. */
-		if (warn_ob_select && (lidx < 0)) {
-		      cerr << get_fileline() << ": warning: " << sig->name();
-		      if (sig->unpacked_dimensions() > 0) cerr << "[]";
-		      cerr << "[" << midx_val;
-		      if (index_tail.sel == index_component_t::SEL_IDX_UP) {
-			    cerr << "+:";
+		      if (moff > loff) {
+			    lidx = loff;
+			    midx = moff + mwid - 1;
 		      } else {
-			    cerr << "-:";
+			    lidx = moff;
+			    midx = loff + lwid - 1;
 		      }
-		      cerr << wid << "] is selecting before vector." << endl;
-		}
-		if (warn_ob_select && (midx >= (long)sig->vector_width())) {
-		      cerr << get_fileline() << ": warning: " << sig->name();
-		      if (sig->unpacked_dimensions() > 0) {
-			    cerr << "[]";
-		      }
-		      cerr << "[" << midx_val;
-		      if (index_tail.sel == index_component_t::SEL_IDX_UP) {
-			    cerr << "+:";
-		      } else {
-			    cerr << "-:";
-		      }
-		      cerr << wid << "] is selecting after vector." << endl;
-		}
+		} else {
+		      midx = sig->sb_to_idx(prefix_indices, midx_val);
 
-		  /* This is completely out side the signal so just skip it. */
-		if (lidx >= (long)sig->vector_width() || midx < 0) {
-		      return false;
+		      if (index_tail.sel == index_component_t::SEL_IDX_UP)
+			    lidx = sig->sb_to_idx(prefix_indices, midx_val+wid-1);
+		      else
+			    lidx = sig->sb_to_idx(prefix_indices, midx_val-wid+1);
+
+		      if (midx < lidx) {
+			    long tmpx = midx;
+			    midx = lidx;
+			    lidx = tmpx;
+		      }
+
+			/* Warn about an indexed part select that is out of range. */
+		      if (warn_ob_select && (lidx < 0)) {
+			    cerr << get_fileline() << ": warning: " << sig->name();
+			    if (sig->unpacked_dimensions() > 0) cerr << "[]";
+			    cerr << "[" << midx_val;
+			    if (index_tail.sel == index_component_t::SEL_IDX_UP) {
+				  cerr << "+:";
+			    } else {
+				  cerr << "-:";
+			    }
+			    cerr << wid << "] is selecting before vector." << endl;
+		      }
+		      if (warn_ob_select && (midx >= (long)sig->vector_width())) {
+			    cerr << get_fileline() << ": warning: " << sig->name();
+			    if (sig->unpacked_dimensions() > 0) {
+				  cerr << "[]";
+			    }
+			    cerr << "[" << midx_val;
+			    if (index_tail.sel == index_component_t::SEL_IDX_UP) {
+				  cerr << "+:";
+			    } else {
+				  cerr << "-:";
+			    }
+			    cerr << wid << "] is selecting after vector." << endl;
+		      }
+
+			/* This is completely out side the signal so just skip it. */
+		      if (lidx >= (long)sig->vector_width() || midx < 0) {
+			    return false;
+		      }
 		}
 
 		break;
@@ -328,39 +368,74 @@ bool PEIdent::eval_part_select_(Design*des, NetScope*scope, NetNet*sig,
 		      return false;
 		}
 
-		long lidx_tmp = sig->sb_to_idx(prefix_indices, lsb);
-		long midx_tmp = sig->sb_to_idx(prefix_indices, msb);
-		  /* Detect reversed indices of a part select. */
-		if (lidx_tmp > midx_tmp) {
-		      cerr << get_fileline() << ": error: Part select "
-			   << sig->name() << "[" << msb << ":"
-			   << lsb << "] indices reversed." << endl;
-		      cerr << get_fileline() << ":      : Did you mean "
-			   << sig->name() << "[" << lsb << ":"
-			   << msb << "]?" << endl;
-		      long tmp = midx_tmp;
-		      midx_tmp = lidx_tmp;
-		      lidx_tmp = tmp;
-		      des->errors += 1;
-		}
-
-		  /* Warn about a part select that is out of range. */
-		if (midx_tmp >= (long)sig->vector_width() || lidx_tmp < 0) {
-		      cerr << get_fileline() << ": warning: Part select "
-			   << sig->name();
-		      if (sig->unpacked_dimensions() > 0) {
-			    cerr << "[]";
+		if (prefix_indices.size()+1 < sig->packed_dims().size()) {
+		      // Here we have a slice that doesn't have enough indices
+		      // to get to a single slice. For example:
+		      //    wire [9:0][5:1] foo
+		      //      ... foo[4:3] ...
+		      // Make this work by finding the indexed slices and
+		      // creating a generated slice that spans the whole
+		      // range.
+		      long loff, moff;
+		      unsigned long lwid, mwid;
+		      bool lrc, mrc;
+		      lrc = sig->sb_to_slice(prefix_indices, lsb, loff, lwid);
+		      mrc = sig->sb_to_slice(prefix_indices, msb, moff, mwid);
+		      if (!mrc || !lrc) {
+			    cerr << get_fileline() << ": error: ";
+			    cerr << "Part-select [" << msb << ":" << lsb;
+			    cerr << "] exceeds the declared bounds for ";
+			    cerr << sig->name();
+			    if (sig->unpacked_dimensions() > 0) cerr << "[]";
+			    cerr << "." << endl;
+			    des->errors += 1;
+			    return 0;
 		      }
-		      cerr << "[" << msb << ":" << lsb
-			   << "] is out of range." << endl;
-		}
-		  /* This is completely out side the signal so just skip it. */
-		if (lidx_tmp >= (long)sig->vector_width() || midx_tmp < 0) {
-		      return false;
-		}
+		      ivl_assert(*this, lwid == mwid);
 
-		midx = midx_tmp;
-		lidx = lidx_tmp;
+		      if (moff > loff) {
+			    lidx = loff;
+			    midx = moff + mwid - 1;
+		      } else {
+			    lidx = moff;
+			    midx = loff + lwid - 1;
+		      }
+		} else {
+		      long lidx_tmp = sig->sb_to_idx(prefix_indices, lsb);
+		      long midx_tmp = sig->sb_to_idx(prefix_indices, msb);
+
+		        /* Detect reversed indices of a part select. */
+		      if (lidx_tmp > midx_tmp) {
+			    cerr << get_fileline() << ": error: Part select "
+			        << sig->name() << "[" << msb << ":"
+			        << lsb << "] indices reversed." << endl;
+			    cerr << get_fileline() << ":      : Did you mean "
+			        << sig->name() << "[" << lsb << ":"
+			        << msb << "]?" << endl;
+			    long tmp = midx_tmp;
+			    midx_tmp = lidx_tmp;
+			    lidx_tmp = tmp;
+			    des->errors += 1;
+		      }
+
+		        /* Warn about a part select that is out of range. */
+		      if (midx_tmp >= (long)sig->vector_width() || lidx_tmp < 0) {
+			    cerr << get_fileline() << ": warning: Part select "
+			         << sig->name();
+			    if (sig->unpacked_dimensions() > 0) {
+				cerr << "[]";
+			    }
+			    cerr << "[" << msb << ":" << lsb
+			         << "] is out of range." << endl;
+		}
+		        /* This is completely out side the signal so just skip it. */
+		      if (lidx_tmp >= (long)sig->vector_width() || midx_tmp < 0) {
+			    return false;
+		      }
+
+		      midx = midx_tmp;
+		      lidx = lidx_tmp;
+		}
 		break;
 	  }
 
@@ -630,7 +705,7 @@ NetNet* PEIdent::elaborate_lnet_common_(Design*des, NetScope*scope,
 	    indices_flags flags;
 	    indices_to_expressions(des, scope, this,
 				   path_tail.index, sig->unpacked_dimensions(),
-				   true, sig->unpacked_count(),
+				   true,
 				   flags,
 				   unpacked_indices,
 				   unpacked_indices_const);

elab_sig.cc

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2000-2014 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 2000-2020 Stephen Williams (steve@icarus.com)
  * Copyright CERN 2012 / Stephen Williams (steve@icarus.com)
  *
  *    This source code is free software; you can redistribute it
@@ -47,6 +47,8 @@
 
 using namespace std;
 
+#if 0
+/* These functions are not currently used. */
 static bool get_const_argument(NetExpr*exp, verinum&res)
 {
       switch (exp->expr_type()) {
@@ -73,8 +75,6 @@ static bool get_const_argument(NetExpr*exp, verinum&res)
       return true;
 }
 
-#if 0
-/* This function is not currently used. */
 static bool get_const_argument(NetExpr*exp, long&res)
 {
       verinum tmp;
@@ -198,7 +198,7 @@ static void elaborate_sig_classes(Design*des, NetScope*scope,
 {
       for (map<perm_string,PClass*>::const_iterator cur = classes.begin()
 		 ; cur != classes.end() ; ++ cur) {
-	    netclass_t*use_class = scope->find_class(cur->second->pscope_name());
+	    netclass_t*use_class = scope->find_class(des, cur->second->pscope_name());
 	    use_class->elaborate_sig(des, cur->second);
       }
 }
@@ -429,7 +429,7 @@ bool PGModule::elaborate_sig_udp_(Design*des, NetScope*scope, PUdp*udp) const
 
 bool PGenerate::elaborate_sig(Design*des,  NetScope*container) const
 {
-      if (direct_nested_)
+      if (directly_nested)
 	    return elaborate_sig_direct_(des, container);
 
       bool flag = true;
@@ -448,7 +448,7 @@ bool PGenerate::elaborate_sig(Design*des,  NetScope*container) const
 	    for (generate_it_t cur = generate_schemes.begin()
 		       ; cur != generate_schemes.end() ; ++ cur ) {
 		  PGenerate*item = *cur;
-		  if (item->direct_nested_ || !item->scope_list_.empty()) {
+		  if (item->directly_nested || !item->scope_list_.empty()) {
 			flag &= item->elaborate_sig(des, container);
 		  }
 	    }
@@ -496,12 +496,12 @@ bool PGenerate::elaborate_sig_direct_(Design*des, NetScope*container) const
 		  for (generate_it_t icur = item->generate_schemes.begin()
 			     ; icur != item->generate_schemes.end() ; ++ icur ) {
 			PGenerate*case_item = *icur;
-			if (case_item->direct_nested_ || !case_item->scope_list_.empty()) {
+			if (case_item->directly_nested || !case_item->scope_list_.empty()) {
 			      flag &= case_item->elaborate_sig(des, container);
 			}
 		  }
 	    } else {
-		  if (item->direct_nested_ || !item->scope_list_.empty()) {
+		  if (item->directly_nested || !item->scope_list_.empty()) {
 			  // Found the item, and it is direct nested.
 			flag &= item->elaborate_sig(des, container);
 		  }
@@ -715,16 +715,23 @@ void PTaskFunc::elaborate_sig_ports_(Design*des, NetScope*scope,
 		  continue;
 	    }
 
-	      // If the port has a default expression that can be used
-	      // as a value when the caller doesn't bind, then
-	      // elaborate that expression here. This expression
-	      // should evaluate down do a constant.
+	      // If the port has a default expression, elaborate
+	      // that expression here.
 	    if (ports_->at(idx).defe != 0) {
-		  tmp_def = elab_and_eval(des, scope, ports_->at(idx).defe, -1, true);
-		  if (tmp_def==0) {
-			cerr << get_fileline() << ": error: Unable to evaluate "
-			     << *ports_->at(idx).defe
-			     << " as a port default (constant) expression." << endl;
+		  if (tmp->port_type() == NetNet::PINPUT) {
+			tmp_def = elab_and_eval(des, scope, ports_->at(idx).defe,
+						-1, scope->need_const_func());
+			if (tmp_def == 0) {
+			      cerr << get_fileline()
+				   << ": error: Unable to evaluate "
+				   << *ports_->at(idx).defe
+				   << " as a port default expression." << endl;
+			      des->errors += 1;
+			}
+		  } else {
+			cerr << get_fileline() << ": sorry: Default arguments "
+			        "for subroutine output or inout ports are not "
+			        "yet supported." << endl;
 			des->errors += 1;
 		  }
 	    }
@@ -750,6 +757,11 @@ void PTaskFunc::elaborate_sig_ports_(Design*des, NetScope*scope,
 		       << "Function arguments must be input ports." << endl;
 		  des->errors += 1;
 	    }
+	    if (tmp->unpacked_dimensions() != 0) {
+		  cerr << get_fileline() << ": sorry: Subroutine ports with "
+			  "unpacked dimensions are not yet supported." << endl;
+		 des->errors += 1;
+	    }
       }
 }
 
@@ -864,13 +876,13 @@ static ivl_type_s*elaborate_type(Design*des, NetScope*scope,
       return 0;
 }
 
-static netparray_t* elaborate_parray_type(Design*des, NetScope*scope,
+static netparray_t* elaborate_parray_type(Design*des, NetScope*scope, const LineInfo*li,
 					  parray_type_t*data_type)
 {
 
       vector<netrange_t>packed_dimensions;
-      bool bad_range = evaluate_ranges(des, scope, packed_dimensions, * data_type->dims);
-      ivl_assert(*data_type, !bad_range);
+      bool dimensions_ok = evaluate_ranges(des, scope, li, packed_dimensions, * data_type->dims);
+      ivl_assert(*data_type, dimensions_ok);
 
       ivl_type_s*element_type = elaborate_type(des, scope, data_type->base_type);
 
@@ -909,62 +921,65 @@ bool test_ranges_eeq(const vector<netrange_t>&lef, const vector<netrange_t>&rig)
  */
 NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const
 {
+	// This sets the vector or array dimension size that will
+	// cause a warning. For now, these warnings are permanently
+	// enabled.
+      const long warn_dimension_size = 1 << 30;
+
       NetNet::Type wtype = type_;
       bool is_implicit_scalar = false;
       if (wtype == NetNet::IMPLICIT) {
 	    wtype = NetNet::WIRE;
 	    is_implicit_scalar = true;
       }
+	// Certain contexts, such as arguments to functions, presume
+	// "reg" instead of "wire". The parser reports these as
+	// IMPLICIT_REG. Also, certain cases, such as:
+	//   fun(string arg1) ...
+	// are implicitly NOT scalar, so detect that case here.
       if (wtype == NetNet::IMPLICIT_REG) {
 	    wtype = NetNet::REG;
-	    is_implicit_scalar = true;
+	    if (data_type_!=IVL_VT_STRING)
+		  is_implicit_scalar = true;
+      }
+
+      if (debug_elaborate) {
+	    cerr << get_fileline() << ": PWire::elaborate_sig: "
+		 << "Signal " << basename()
+		 << ", wtype=" << wtype
+		 << ", data_type_=" << data_type_
+		 << ", is_implicit_scalar=" << (is_implicit_scalar?"true":"false")
+		 << endl;
       }
 
       unsigned wid = 1;
       vector<netrange_t>packed_dimensions;
 
+      NetScope*base_type_scope = scope;
+      if (set_data_type_ && !set_data_type_->name.nil())
+            base_type_scope = scope->find_typedef_scope(des, set_data_type_);
+
       des->errors += error_cnt_;
 
-	// A signal can not have the same name as a scope object.
-      const NetScope *child = scope->child_byname(name_);
-      if (child) {
-	    cerr << get_fileline() << ": error: signal and ";
-	    child->print_type(cerr);
-	    cerr << " in '" << scope->fullname()
-	         << "' have the same name '" << name_ << "'." << endl;
-	    des->errors += 1;
-      }
-	// A signal can not have the same name as a genvar.
-      const LineInfo *genvar = scope->find_genvar(name_);
-      if (genvar) {
-	    cerr << get_fileline() << ": error: signal and genvar in '"
-	         << scope->fullname() << "' have the same name '" << name_
-	         << "'." << endl;
-	    des->errors += 1;
-      }
-	// A signal can not have the same name as a parameter. Note
-	// that we treat enumeration literals similar to parameters,
-	// so if the name matches an enumeration literal, it will be
-	// caught here.
-      const NetExpr *ex_msb, *ex_lsb;
-      const NetExpr *parm = scope->get_parameter(des, name_, ex_msb, ex_lsb);
-      if (parm) {
-	    cerr << get_fileline() << ": error: signal and parameter in '"
-	         << scope->fullname() << "' have the same name '" << name_
-	         << "'." << endl;
-	    des->errors += 1;
-      }
-	// A signal can not have the same name as a named event.
-      const NetEvent *event = scope->find_event(name_);
-      if (event) {
-	    cerr << get_fileline() << ": error: signal and named event in '"
-	         << scope->fullname() << "' have the same name '" << name_
-	         << "'." << endl;
-	    des->errors += 1;
-      }
-
       if (port_set_ || net_set_) {
-	    bool bad_range = false;
+
+	    if (warn_implicit_dimensions
+		&& port_set_ && net_set_
+		&& net_.empty() && !port_.empty()) {
+		  cerr << get_fileline() << ": warning: "
+		       << "var/net declaration of " << basename()
+		       << " inherits dimensions from port declaration." << endl;
+	    }
+
+	    if (warn_implicit_dimensions
+		&& port_set_ && net_set_
+		&& port_.empty() && !net_.empty()) {
+		  cerr << get_fileline() << ": warning: "
+		       << "Port declaration of " << basename()
+		       << " inherits dimensions from var/net." << endl;
+	    }
+
+	    bool dimensions_ok = true;
 	    vector<netrange_t> plist, nlist;
 	    /* If they exist get the port definition MSB and LSB */
 	    if (port_set_ && !port_.empty()) {
@@ -972,7 +987,7 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const
 			cerr << get_fileline() << ": PWire::elaborate_sig: "
 			     << "Evaluate ranges for port " << basename() << endl;
 		  }
-		  bad_range |= evaluate_ranges(des, scope, plist, port_);
+		  dimensions_ok &= evaluate_ranges(des, scope, this, plist, port_);
 		  nlist = plist;
 		    /* An implicit port can have a range so note that here. */
 		  is_implicit_scalar = false;
@@ -980,13 +995,13 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const
             assert(port_set_ || port_.empty());
 
 	    /* If they exist get the net/etc. definition MSB and LSB */
-	    if (net_set_ && !net_.empty() && !bad_range) {
+	    if (net_set_ && !net_.empty() && dimensions_ok) {
 		  nlist.clear();
 		  if (debug_elaborate) {
 			cerr << get_fileline() << ": PWire::elaborate_sig: "
 			     << "Evaluate ranges for net " << basename() << endl;
 		  }
-		  bad_range |= evaluate_ranges(des, scope, nlist, net_);
+		  dimensions_ok &= evaluate_ranges(des, base_type_scope, this, nlist, net_);
 	    }
             assert(net_set_ || net_.empty());
 
@@ -1042,7 +1057,11 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const
 
 	    packed_dimensions = nlist;
 	    wid = netrange_width(packed_dimensions);
-
+	    if (wid > warn_dimension_size) {
+		  cerr << get_fileline() << ": warning: Vector size "
+		          "is greater than " << warn_dimension_size
+		       << "." << endl;
+	    }
       }
 
       unsigned nattrib = 0;
@@ -1053,6 +1072,10 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const
       list<netrange_t>unpacked_dimensions;
       netdarray_t*netdarray = 0;
 
+      NetScope*array_type_scope = scope;
+      if (uarray_type_ && !uarray_type_->name.nil())
+            array_type_scope = scope->find_typedef_scope(des, uarray_type_);
+
       for (list<pform_range_t>::const_iterator cur = unpacked_.begin()
 		 ; cur != unpacked_.end() ; ++cur) {
 	    PExpr*use_lidx = cur->first;
@@ -1063,6 +1086,7 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const
 	      // put all the packed dimensions there.
 	    if (use_lidx==0 && use_ridx==0) {
 		  netvector_t*vec = new netvector_t(packed_dimensions, data_type_);
+		  vec->set_signed(get_signed());
 		  packed_dimensions.clear();
 		  ivl_assert(*this, netdarray==0);
 		  netdarray = new netdarray_t(vec);
@@ -1070,49 +1094,55 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const
 	    }
 
 	      // Special case: Detect the mark for a QUEUE
-	      // declaration, which is the dimensions [null:<nil>].
-	    if (use_ridx==0 && dynamic_cast<PENull*>(use_lidx)) {
+	      // declaration, which is the dimensions [null:max_idx].
+	    if (dynamic_cast<PENull*>(use_lidx)) {
 		  netvector_t*vec = new netvector_t(packed_dimensions, data_type_);
+		  vec->set_signed(get_signed());
 		  packed_dimensions.clear();
 		  ivl_assert(*this, netdarray==0);
-		  netdarray = new netqueue_t(vec);
+		  long max_idx;
+		  if (use_ridx) {
+			NetExpr*tmp = elab_and_eval(des, array_type_scope, use_ridx,
+			                            -1, true);
+			NetEConst*cv = dynamic_cast<NetEConst*>(tmp);
+			if (cv == 0) {
+			      cerr << get_fileline() << ": error: queue '" << name_
+			           << "' bound must be a constant!" << endl;
+			      des->errors += 1;
+			      max_idx = -1;
+			} else {
+			      verinum res = cv->value();
+			      if (res.is_defined()) {
+				    max_idx = res.as_long();
+				    if (max_idx < 0) {
+					  cerr << get_fileline() << ": error: queue '"
+					       << name_ << "' bound must be positive ("
+					       << max_idx << ")!" << endl;
+					  des->errors += 1;
+					  max_idx = -1;
+				    }
+			      } else {
+				    cerr << get_fileline() << ": error: queue '" << name_
+				         << "' bound is undefined!" << endl;
+				    des->errors += 1;
+				    max_idx = -1;
+			      }
+			}
+		  } else max_idx = -1;
+		  netdarray = new netqueue_t(vec, max_idx);
 		  continue;
 	    }
 
 	      // Cannot handle dynamic arrays of arrays yet.
 	    ivl_assert(*this, netdarray==0);
-	    ivl_assert(*this, use_lidx && use_ridx);
-
-	    NetExpr*lexp = elab_and_eval(des, scope, use_lidx, -1, true);
-	    NetExpr*rexp = elab_and_eval(des, scope, use_ridx, -1, true);
-
-	    if ((lexp == 0) || (rexp == 0)) {
-		  cerr << get_fileline() << ": internal error: There is "
-		       << "a problem evaluating indices for ``"
-		       << name_ << "''." << endl;
-		  des->errors += 1;
-		  return 0;
-	    }
-
-	    bool const_flag = true;
-	    verinum lval, rval;
-	    const_flag &= get_const_argument(lexp, lval);
-	    const_flag &= get_const_argument(rexp, rval);
-	    delete rexp;
-	    delete lexp;
 
 	    long index_l, index_r;
-	    if (! const_flag) {
-		  cerr << get_fileline() << ": error: The indices "
-		       << "are not constant for array ``"
-		       << name_ << "''." << endl;
-		  des->errors += 1;
-                    /* Attempt to recover from error, */
-	          index_l = 0;
-	          index_r = 0;
-	    } else {
-		  index_l = lval.as_long();
-		  index_r = rval.as_long();
+	    evaluate_range(des, array_type_scope, this, *cur, index_l, index_r);
+
+	    if (abs(index_r - index_l) > warn_dimension_size) {
+		  cerr << get_fileline() << ": warning: Array dimension "
+		          "is greater than " << warn_dimension_size
+		       << "." << endl;
 	    }
 
 	    unpacked_dimensions.push_back(netrange_t(index_l, index_r));
@@ -1145,6 +1175,14 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const
 
       NetLogic*pull = 0;
       if (wtype == NetNet::SUPPLY0 || wtype == NetNet::SUPPLY1) {
+	    if (debug_elaborate) {
+		  cerr << get_fileline() << ": debug: "
+		       << "Generate a SUPPLY pull for the ";
+		  if (wtype == NetNet::SUPPLY0) cerr << "supply0";
+		  else cerr << "supply1";
+		  cerr << " net." << endl;
+	    }
+
 	    NetLogic::TYPE pull_type = (wtype==NetNet::SUPPLY1)
 		  ? NetLogic::PULLUP
 		  : NetLogic::PULLDOWN;
@@ -1155,14 +1193,6 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const
 	    pull->pin(0).drive1(IVL_DR_SUPPLY);
 	    des->add_node(pull);
 	    wtype = NetNet::WIRE;
-
-	    if (debug_elaborate) {
-		  cerr << get_fileline() << ": debug: "
-		       << "Generate a SUPPLY pull for the ";
-		  if (wtype == NetNet::SUPPLY0) cerr << "supply0";
-		  else cerr << "supply1";
-		  cerr << " net." << endl;
-	    }
       }
 
 
@@ -1194,11 +1224,11 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const
 		  cerr << " in scope " << scope_path(scope) << endl;
 	    }
 
-	    sig = new NetNet(scope, name_, wtype, use_type);
+	    sig = new NetNet(scope, name_, wtype, unpacked_dimensions, use_type);
 
       } else if (enum_type_t*enum_type = dynamic_cast<enum_type_t*>(set_data_type_)) {
 	    list<named_pexpr_t>::const_iterator sample_name = enum_type->names->begin();
-	    const netenum_t*use_enum = scope->find_enumeration_for_name(sample_name->name);
+	    const netenum_t*use_enum = base_type_scope->find_enumeration_for_name(des, sample_name->name);
 
 	    if (debug_elaborate) {
 		  cerr << get_fileline() << ": debug: Create signal " << wtype
@@ -1231,7 +1261,7 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const
 
 	      // The trick here is that the parray type has an
 	      // arbitrary sub-type, and not just a scalar bit...
-	    netparray_t*use_type = elaborate_parray_type(des, scope, parray_type);
+	    netparray_t*use_type = elaborate_parray_type(des, scope, this, parray_type);
 	      // Should not be getting packed dimensions other than
 	      // through the parray type declaration.
 	    ivl_assert(*this, packed_dimensions.empty());
@@ -1293,27 +1323,3 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const
 
       return sig;
 }
-
-
-void Design::root_elaborate_sig(void)
-{
-      for (map<perm_string,netclass_t*>::const_iterator cur = classes_.begin()
-		 ; cur != classes_.end() ; ++ cur) {
-
-	    netclass_t*cur_class = cur->second;
-	    PClass*cur_pclass = class_to_pclass_[cur_class];
-
-	    cur_class->elaborate_sig(this, cur_pclass);
-      }
-
-      for (map<NetScope*,PTaskFunc*>::iterator cur = root_tasks_.begin()
-		 ; cur != root_tasks_.end() ; ++ cur) {
-
-	    if (debug_elaborate) {
-		  cerr << cur->second->get_fileline() << ": root_elaborate_sig: "
-		       << "Elaborate_sig for root task/func " << scope_path(cur->first) << endl;
-	    }
-
-	    cur->second->elaborate_sig(this, cur->first);
-      }
-}

elab_type.cc

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012-2014 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 2012-2020 Stephen Williams (steve@icarus.com)
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -17,11 +17,13 @@
  *    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
  */
 
+# include  "PExpr.h"
 # include  "pform_types.h"
 # include  "netlist.h"
 # include  "netclass.h"
 # include  "netdarray.h"
 # include  "netenum.h"
+# include  "netqueue.h"
 # include  "netparray.h"
 # include  "netscalar.h"
 # include  "netstruct.h"
@@ -32,19 +34,61 @@
 
 using namespace std;
 
+/*
+ * Some types have a list of ranges that need to be elaborated. This
+ * function elaborates the ranges referenced by "dims" into the vector
+ * "ranges".
+ */
+static void elaborate_array_ranges(Design*des, NetScope*scope,
+				   vector<netrange_t>&ranges,
+				   const list<pform_range_t>*dims)
+{
+      if (dims == 0)
+	    return;
+
+      for (list<pform_range_t>::const_iterator cur = dims->begin()
+		 ; cur != dims->end() ; ++ cur) {
+
+	    NetExpr*me = elab_and_eval(des, scope, cur->first, 0, true);
+
+	    NetExpr*le = elab_and_eval(des, scope, cur->second, 0, true);
+
+	      /* If elaboration failed for either expression, we
+		 should have already reported the error, so just
+		 skip the following evaluation to recover. */
+
+	    long mnum = 0, lnum = 0;
+	    if ( me && ! eval_as_long(mnum, me) ) {
+		  assert(0);
+		  des->errors += 1;
+	    }
+
+	    if ( le && ! eval_as_long(lnum, le) ) {
+		  assert(0);
+		  des->errors += 1;
+	    }
+
+	    ranges.push_back(netrange_t(mnum, lnum));
+      }
+}
+
 /*
  * Elaborations of types may vary depending on the scope that it is
  * done in, so keep a per-scope cache of the results.
  */
 ivl_type_s* data_type_t::elaborate_type(Design*des, NetScope*scope)
 {
+	// User-defined types must be elaborated in the context
+	// where they were defined.
+      if (!name.nil())
+	    scope = scope->find_typedef_scope(des, this);
+
+      ivl_assert(*this, scope);
       Definitions*use_definitions = scope;
-      if (use_definitions == 0)
-	    use_definitions = des;
 
       map<Definitions*,ivl_type_s*>::iterator pos = cache_type_elaborate_.lower_bound(use_definitions);
-      if (pos->first == use_definitions)
-	    return pos->second;
+	  if (pos != cache_type_elaborate_.end() && pos->first == use_definitions)
+	     return pos->second;
 
       ivl_type_s*tmp = elaborate_type_raw(des, scope);
       cache_type_elaborate_.insert(pos, pair<NetScope*,ivl_type_s*>(scope, tmp));
@@ -107,46 +151,20 @@ ivl_type_s* class_type_t::elaborate_type_raw(Design*, NetScope*) const
  * available at the right time. At that time, the netenum_t* object is
  * stashed in the scope so that I can retrieve it here.
  */
-ivl_type_s* enum_type_t::elaborate_type_raw(Design*des, NetScope*scope) const
+ivl_type_s* enum_type_t::elaborate_type_raw(Design*, NetScope*scope) const
 {
       ivl_assert(*this, scope);
       ivl_type_s*tmp = scope->enumeration_for_key(this);
-      if (tmp) return tmp;
-
-      tmp = des->enumeration_for_key(this);
+      if (tmp == 0 && scope->unit()) {
+	    tmp = scope->unit()->enumeration_for_key(this);
+}
       return tmp;
 }
 
 ivl_type_s* vector_type_t::elaborate_type_raw(Design*des, NetScope*scope) const
 {
       vector<netrange_t> packed;
-
-      if (pdims.get()) {
-	    for (list<pform_range_t>::const_iterator cur = pdims->begin()
-		       ; cur != pdims->end() ; ++ cur) {
-
-		  NetExpr*me = elab_and_eval(des, scope, cur->first, 0, true);
-
-		  NetExpr*le = elab_and_eval(des, scope, cur->second, 0, true);
-
-		    /* If elaboration failed for either expression, we
-		       should have already reported the error, so just
-		       skip the following evaluation to recover. */
-
-		  long mnum = 0, lnum = 0;
-		  if ( me && ! eval_as_long(mnum, me) ) {
-			assert(0);
-			des->errors += 1;
-		  }
-
-		  if ( le && ! eval_as_long(lnum, le) ) {
-			assert(0);
-			des->errors += 1;
-		  }
-
-		  packed.push_back(netrange_t(mnum, lnum));
-	    }
-      }
+      elaborate_array_ranges(des, scope, packed, pdims.get());
 
       netvector_t*tmp = new netvector_t(packed, base_type);
       tmp->set_signed(signed_flag);
@@ -171,13 +189,14 @@ ivl_type_s* string_type_t::elaborate_type_raw(Design*, NetScope*) const
       return &netstring_t::type_string;
 }
 
-ivl_type_s* parray_type_t::elaborate_type_raw(Design*des, NetScope*) const
+ivl_type_s* parray_type_t::elaborate_type_raw(Design*des, NetScope*scope) const
 {
-      cerr << get_fileline() << " : sorry: "
-           << "Packed arrays are not currently supported in this context."
-           << endl;
-      des->errors += 1;
-      return 0;
+      vector<netrange_t>packed;
+      elaborate_array_ranges(des, scope, packed, dims.get());
+
+      ivl_type_t etype = base_type->elaborate_type(des, scope);
+
+      return new netparray_t(packed, etype);
 }
 
 netstruct_t* struct_type_t::elaborate_type_raw(Design*des, NetScope*scope) const
@@ -201,9 +220,9 @@ netstruct_t* struct_type_t::elaborate_type_raw(Design*des, NetScope*scope) const
 	      // There may be several names that are the same type:
 	      //   <data_type> name1, name2, ...;
 	      // Process all the member, and give them a type.
-	    for (list<decl_assignment_t*>::iterator name = curp->names->begin()
-		       ; name != curp->names->end() ;  ++ name) {
-		  decl_assignment_t*namep = *name;
+	    for (list<decl_assignment_t*>::iterator cur_name = curp->names->begin()
+		       ; cur_name != curp->names->end() ;  ++ cur_name) {
+		  decl_assignment_t*namep = *cur_name;
 
 		  netstruct_t::member_t memb;
 		  memb.name = namep->name;
@@ -232,10 +251,21 @@ ivl_type_s* uarray_type_t::elaborate_type_raw(Design*des, NetScope*scope) const
 	    return res;
       }
 
-      vector<netrange_t> dimensions;
-      bool bad_range = evaluate_ranges(des, scope, dimensions, *dims);
+	// Special case: if the dimension is null:nil. this is a queue.
+      if (dynamic_cast<PENull*>(cur->first)) {
+	    cerr << get_fileline() << ": sorry: "
+		 << "SV queues inside classes are not yet supported." << endl;
+	    des->errors += 1;
 
-      if (bad_range) {
+	      // FIXME: Need to set the max size if cur->second is defined
+	    ivl_type_s*res = new netqueue_t(btype, -1);
+	    return res;
+      }
+
+      vector<netrange_t> dimensions;
+      bool dimensions_ok = evaluate_ranges(des, scope, this, dimensions, *dims);
+
+      if (!dimensions_ok) {
 	    cerr << get_fileline() << " : warning: "
 		 << "Bad dimensions for type here." << endl;
       }

elaborate_analog.cc

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2012 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 2008-2021 Stephen Williams (steve@icarus.com)
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -26,6 +26,8 @@
 
 # include  <typeinfo>
 
+using namespace std;
+
 NetProc* AContrib::elaborate(Design*des, NetScope*scope) const
 {
       NetExpr*lval = elab_and_eval(des, scope, lval_, -1);

emit.cc

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1998-2013 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 1998-2017 Stephen Williams (steve@icarus.com)
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -33,6 +33,8 @@
 # include  <cassert>
 # include  <cstring>
 
+using namespace std;
+
 bool NetNode::emit_node(struct target_t*) const
 {
       cerr << "EMIT: Gate type? " << typeid(*this).name() << endl;
@@ -123,6 +125,12 @@ bool NetFF::emit_node(struct target_t*tgt) const
       return true;
 }
 
+bool NetLatch::emit_node(struct target_t*tgt) const
+{
+      tgt->lpm_latch(this);
+      return true;
+}
+
 bool NetLiteral::emit_node(struct target_t*tgt) const
 {
       return tgt->net_literal(this);
@@ -504,26 +512,12 @@ int Design::emit(struct target_t*tgt) const
       if (tgt->start_design(this) == false)
 	    return -2;
 
-      for (map<NetScope*,PTaskFunc*>::const_iterator scope = root_tasks_.begin()
-		 ; scope != root_tasks_.end() ; ++ scope) {
-	    scope->first->emit_scope(tgt);
-	    scope->first->emit_defs(tgt);
-      }
-
 	// enumerate package scopes
       for (map<perm_string,NetScope*>::const_iterator scope = packages_.begin()
 		 ; scope != packages_.end() ; ++ scope) {
 	    scope->second->emit_scope(tgt);
       }
 
-      for (map<perm_string,netclass_t*>::const_iterator cur = classes_.begin()
-		 ; cur != classes_.end() ; ++cur) {
-	    const NetScope*use_scope = cur->second->class_scope();
-	    cur->second->emit_scope(tgt);
-	    tgt->class_type(use_scope, cur->second);
-	    cur->second->emit_defs(tgt);
-      }
-
 	// enumerate root scopes
       for (list<NetScope*>::const_iterator scope = root_scopes_.begin()
 		 ; scope != root_scopes_.end(); ++ scope ) {

eval.cc

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1998-2014 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 1998-2021 Stephen Williams (steve@icarus.com)
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -27,6 +27,8 @@
 # include  "netmisc.h"
 # include  "compiler.h"
 
+using namespace std;
+
 verinum* PExpr::eval_const(Design*, NetScope*) const
 {
       return 0;

eval_attrib.cc

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2002-2010 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 2002-2021 Stephen Williams (steve@icarus.com)
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -24,6 +24,8 @@
 # include  <iostream>
 # include  <cassert>
 
+using namespace std;
+
 /*
  * The evaluate_attributes function evaluates the attribute
  * expressions from the map, and returns a table in a form suitable

eval_tree.cc

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1999-2014 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 1999-2020 Stephen Williams (steve@icarus.com)
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -29,6 +29,8 @@
 # include  "ivl_assert.h"
 # include  "netmisc.h"
 
+using namespace std;
+
 NetExpr* NetExpr::eval_tree()
 {
       return 0;
@@ -404,7 +406,6 @@ NetEConst* NetEBComp::eval_leeq_(const NetExpr*le, const NetExpr*re) const
 {
       if (le->expr_type() == IVL_VT_REAL || re->expr_type() == IVL_VT_REAL)
 	    return eval_leeq_real_(le, re, true);
-//      assert(expr_type() == IVL_VT_LOGIC);
 
       const NetEConst*r = dynamic_cast<const NetEConst*>(re);
       if (r == 0) return 0;
@@ -416,12 +417,6 @@ NetEConst* NetEBComp::eval_leeq_(const NetExpr*le, const NetExpr*re) const
 	    return res;
       }
 
-      if (le->expr_width() == 0) {
-	    cerr << get_fileline() << ": internal error: Something wrong "
-		 << "with the left side width of <= ?" << endl;
-	    cerr << get_fileline() << ":               : " << *this << endl;
-      }
-
       if (NetEConst*tmp = must_be_leeq_(le, rv, true)) {
 	    return tmp;
       }
@@ -545,7 +540,7 @@ NetEConst* NetEBComp::eval_eqeq_real_(bool ne_flag, const NetExpr*le, const NetE
       bool flag = get_real_arguments(le, re, lval, rval);
       if (! flag) return 0;
 
-      verinum result(((lval == rval) ^ ne_flag) ?
+      verinum result(((lval == rval) != ne_flag) ?
                      verinum::V1 : verinum::V0, 1);
       NetEConst*res = new NetEConst(result);
       ivl_assert(*this, res);
@@ -570,11 +565,11 @@ NetEConst* NetEBComp::eval_eqeq_(bool ne_flag, const NetExpr*le, const NetExpr*r
       const verinum::V ne_res = ne_flag? verinum::V1 : verinum::V0;
 
       verinum::V res = eq_res;
-      unsigned top = lv.len();
-      if (rv.len() < top)
-	    top = rv.len();
 
-      for (unsigned idx = 0 ;  idx < top ;  idx += 1) {
+	// The two expressions should already be padded to the same size.
+      ivl_assert(*this, lv.len() == rv.len());
+
+      for (unsigned idx = 0 ;  idx < lv.len() ;  idx += 1) {
 
 	    bool x_bit_present = false;
 
@@ -611,60 +606,6 @@ NetEConst* NetEBComp::eval_eqeq_(bool ne_flag, const NetExpr*le, const NetExpr*r
 	    }
       }
 
-      if (res != verinum::Vx) {
-	    verinum::V lpad = verinum::V0;
-	    verinum::V rpad = verinum::V0;
-
-	    if (lv.has_sign() && lv.get(lv.len()-1) == verinum::V1)
-		  lpad = verinum::V1;
-	    if (rv.has_sign() && rv.get(rv.len()-1) == verinum::V1)
-		  rpad = verinum::V1;
-
-	    for (unsigned idx = top ;  idx < lv.len() ;  idx += 1)
-		  switch (lv.get(idx)) {
-
-		      case verinum::Vx:
-		      case verinum::Vz:
-			res = verinum::Vx;
-			break;
-
-		      case verinum::V0:
-			if (res != verinum::Vx && rpad != verinum::V0)
-			      res = ne_res;
-			break;
-
-		      case verinum::V1:
-			if (res != verinum::Vx && rpad != verinum::V1)
-			      res = ne_res;
-			break;
-
-		      default:
-			break;
-		  }
-
-	    for (unsigned idx = top ;  idx < rv.len() ;  idx += 1)
-		  switch (rv.get(idx)) {
-
-		      case verinum::Vx:
-		      case verinum::Vz:
-			res = verinum::Vx;
-			break;
-
-		      case verinum::V0:
-			if (res != verinum::Vx && lpad != verinum::V0)
-			      res = ne_res;
-			break;
-
-		      case verinum::V1:
-			if (res != verinum::Vx && lpad != verinum::V1)
-			      res = ne_res;
-			break;
-
-		      default:
-			break;
-		  }
-      }
-
       NetEConst*result = new NetEConst(verinum(res, 1));
       ivl_assert(*this, result);
       return result;
@@ -681,41 +622,15 @@ NetEConst* NetEBComp::eval_eqeqeq_(bool ne_flag, const NetExpr*le, const NetExpr
 
       verinum::V res = verinum::V1;
 
-	// Find the smallest argument length.
-      unsigned cnt = lv.len();
-      if (cnt > rv.len()) cnt = rv.len();
+	// The two expressions should already be padded to the same size.
+      ivl_assert(*this, lv.len() == rv.len());
 
-	// Check the common bits.
-      for (unsigned idx = 0 ;  idx < cnt ;  idx += 1)
+      for (unsigned idx = 0 ;  idx < lv.len() ;  idx += 1)
 	    if (lv.get(idx) != rv.get(idx)) {
 		  res = verinum::V0;
 		  break;
 	    }
 
-      bool is_signed = lv.has_sign() && rv.has_sign();
-
-	// If the left value is longer check it against the pad bit.
-      if (res == verinum::V1) {
-	    verinum::V pad = verinum::V0;
-	    if (is_signed) pad = rv.get(rv.len()-1);
-	    for (unsigned idx = cnt ;  idx < lv.len() ;  idx += 1)
-		  if (lv.get(idx) != pad) {
-			res = verinum::V0;
-			break;
-		  }
-      }
-
-	// If the right value is longer check it against the pad bit.
-      if (res == verinum::V1) {
-	    verinum::V pad = verinum::V0;
-	    if (is_signed) pad = lv.get(lv.len()-1);
-	    for (unsigned idx = cnt ;  idx < rv.len() ;  idx += 1) {
-		  if (rv.get(idx) != pad)
-			res = verinum::V0;
-			break;
-		  }
-      }
-
       if (ne_flag) {
 	    if (res == verinum::V0) res = verinum::V1;
 	    else res = verinum::V0;
@@ -726,6 +641,55 @@ NetEConst* NetEBComp::eval_eqeqeq_(bool ne_flag, const NetExpr*le, const NetExpr
       return result;
 }
 
+NetEConst* NetEBComp::eval_weqeq_(bool ne_flag, const NetExpr*le, const NetExpr*re) const
+{
+      const NetEConst*lc = dynamic_cast<const NetEConst*>(le);
+      const NetEConst*rc = dynamic_cast<const NetEConst*>(re);
+      if (lc == 0 || rc == 0) return 0;
+
+      const verinum&lv = lc->value();
+      const verinum&rv = rc->value();
+
+      const verinum::V eq_res = ne_flag ? verinum::V0 : verinum::V1;
+      const verinum::V ne_res = ne_flag ? verinum::V1 : verinum::V0;
+
+      verinum::V res = eq_res;
+
+	// The two expressions should already be padded to the same size.
+      ivl_assert(*this, lv.len() == rv.len());
+
+      for (unsigned idx = 0 ;  idx < lv.len() ;  idx += 1) {
+	      // An X or Z in the R-value matches any L-value.
+	    switch (rv.get(idx)) {
+		case verinum::Vx:
+		case verinum::Vz:
+		  continue;
+		default:
+		  break;
+	    }
+
+	      // An X or Z in the L-value that is not matches by an R-value X/Z returns undefined.
+	    switch (lv.get(idx)) {
+		case verinum::Vx:
+		case verinum::Vz:
+		  res = verinum::Vx;
+		  continue;
+		default:
+		  break;
+	    }
+
+	      // A hard (0/1) mismatch gives a not-equal result.
+	    if (rv.get(idx) != lv.get(idx)) {
+		  res = ne_res;
+		  break;
+	    }
+      }
+
+      NetEConst*result = new NetEConst(verinum(res, 1));
+      ivl_assert(*this, result);
+      return result;
+}
+
 NetEConst* NetEBComp::eval_arguments_(const NetExpr*l, const NetExpr*r) const
 {
       NetEConst*res = 0;
@@ -739,6 +703,10 @@ NetEConst* NetEBComp::eval_arguments_(const NetExpr*l, const NetExpr*r) const
 	    res = eval_eqeq_(false, l, r);
 	    break;
 
+	  case 'w': // Wild equality (==?)
+	    res = eval_weqeq_(false, l, r);
+	    break;
+
 	  case 'G': // >=
 	    res = eval_gteq_(l, r);
 	    break;
@@ -755,6 +723,10 @@ NetEConst* NetEBComp::eval_arguments_(const NetExpr*l, const NetExpr*r) const
 	    res = eval_eqeq_(true, l, r);
 	    break;
 
+	  case 'W': // Wild not-equal (!=?)
+	    res = eval_weqeq_(true, l, r);
+	    break;
+
 	  case '<': // Less than
 	    res = eval_less_(l, r);
 	    break;
@@ -831,48 +803,44 @@ NetExpr* NetEBDiv::eval_arguments_(const NetExpr*l, const NetExpr*r) const
       return tmp;
 }
 
-NetEConst* NetEBLogic::eval_tree_real_(const NetExpr*l, const NetExpr*r) const
-{
-      double lval;
-      double rval;
-
-      bool flag = get_real_arguments(l, r, lval, rval);
-      if (! flag) return 0;
-
-      verinum::V res;
-      switch (op_) {
-	  case 'a': // Logical AND (&&)
-	    if ((lval != 0.0) && (rval != 0.0))
-		  res = verinum::V1;
-	    else
-		  res = verinum::V0;
-	    break;
-
-	  case 'o': // Logical OR (||)
-	    if ((lval != 0.0) || (rval != 0.0))
-		  res = verinum::V1;
-	    else
-		  res = verinum::V0;
-	    break;
-
-	  default:
-	    return 0;
-      }
-
-      NetEConst*tmp = new NetEConst(verinum(res, 1));
-      ivl_assert(*this, tmp);
-      eval_debug(this, tmp, true);
-      return tmp;
-}
-
 NetEConst* NetEBLogic::eval_arguments_(const NetExpr*l, const NetExpr*r) const
 {
-      if (l->expr_type() == IVL_VT_REAL || r->expr_type() == IVL_VT_REAL)
-	    return eval_tree_real_(l,r);
+	// NetEBLogic arguments should have already been reduced so real is not possible.
+      ivl_assert(*this, (l->expr_type() != IVL_VT_REAL) && (r->expr_type() != IVL_VT_REAL));
       assert(expr_type() == IVL_VT_LOGIC);
 
       const NetEConst*lc = dynamic_cast<const NetEConst*>(l);
       const NetEConst*rc = dynamic_cast<const NetEConst*>(r);
+
+      // If the left side is constant and the right side is short circuited
+      // replace the expression with a constant
+      if (rc == 0 && lc != 0) {
+	    verinum v = lc->value();
+	    verinum::V res = verinum::Vx;
+	    switch (op_) {
+		case 'a': // Logical AND (&&)
+		  if (v.is_zero())
+			res = verinum::V0;
+		  break;
+		case 'o': // Logical OR (||)
+		  if (! v.is_zero() && v.is_defined())
+			res = verinum::V1;
+		  break;
+		case 'q': // Logical implication (->)
+		  if (v.is_zero())
+			res = verinum::V1;
+		  break;
+		default:
+		  break;
+	    }
+	    if (res != verinum::Vx) {
+		  NetEConst*tmp = new NetEConst(verinum(res, 1));
+		  ivl_assert(*this, tmp);
+		  eval_debug(this, tmp, false);
+		  return tmp;
+	    }
+      }
+
       if (lc == 0 || rc == 0) return 0;
 
       verinum::V lv = verinum::V0;
@@ -901,25 +869,39 @@ NetEConst* NetEBLogic::eval_arguments_(const NetExpr*l, const NetExpr*r) const
 	  case 'a': // Logical AND (&&)
 	    if ((lv == verinum::V0) || (rv == verinum::V0))
 		  res = verinum::V0;
-
 	    else if ((lv == verinum::V1) && (rv == verinum::V1))
 		  res = verinum::V1;
-
 	    else
 		  res = verinum::Vx;
-
 	    break;
 
 	  case 'o': // Logical OR (||)
 	    if ((lv == verinum::V1) || (rv == verinum::V1))
 		  res = verinum::V1;
-
 	    else if ((lv == verinum::V0) && (rv == verinum::V0))
 		  res = verinum::V0;
-
 	    else
 		  res = verinum::Vx;
+	    break;
 
+	  case 'q': // Logical implication (->)
+	    if ((lv == verinum::V0) || (rv == verinum::V1))
+		  res = verinum::V1;
+	    else if ((lv == verinum::V1) && (rv == verinum::V0))
+		  res = verinum::V0;
+	    else
+		  res = verinum::Vx;
+	    break;
+
+	  case 'Q': // Logical equivalence (<->)
+	    if (((lv == verinum::V0) && (rv == verinum::V0)) ||
+	        ((lv == verinum::V1) && (rv == verinum::V1)))
+		  res = verinum::V1;
+	    else if (((lv == verinum::V0) && (rv == verinum::V1)) ||
+	             ((lv == verinum::V1) && (rv == verinum::V0)))
+		  res = verinum::V0;
+	    else
+		  res = verinum::Vx;
 	    break;
 
 	  default:
@@ -1097,6 +1079,7 @@ NetEConst* NetEBShift::eval_arguments_(const NetExpr*l, const NetExpr*r) const
 		  break;
 		case 'r':
                   lv.has_sign(false);
+		  // fallthrough
 		case 'R':
 		  val = cast_to_width(lv >> shift, wid);
 		  break;
@@ -1548,6 +1531,7 @@ NetEConst* NetEUReduce::eval_arguments_(const NetExpr*ex) const
 
 	  case 'A':
 		invert = true;
+		// fallthrough
 	  case '&': {
 		res = verinum::V1;
 		for (unsigned idx = 0 ;  idx < val.len() ;  idx += 1)
@@ -1557,6 +1541,7 @@ NetEConst* NetEUReduce::eval_arguments_(const NetExpr*ex) const
 
 	  case 'N':
 		invert = true;
+		// fallthrough
 	  case '|': {
 		res = verinum::V0;
 		for (unsigned idx = 0 ;  idx < val.len() ;  idx += 1)
@@ -1566,6 +1551,7 @@ NetEConst* NetEUReduce::eval_arguments_(const NetExpr*ex) const
 
 	  case 'X':
 		invert = true;
+		// fallthrough
 	  case '^': {
 		  /* Reduction XOR. */
 		unsigned ones = 0, unknown = 0;
@@ -1617,6 +1603,7 @@ NetExpr* NetECast::eval_arguments_(const NetExpr*ex) const
 			res_val = cast_to_width(res_val, expr_width());
 		  res = new NetEConst(res_val);
 	    }
+	    // fallthrough
 	  case 'v':
 	    if (const NetECReal*val = dynamic_cast<const NetECReal*>(ex)) {
 		  verinum res_val(val->value().as_double(), false);
@@ -1931,15 +1918,111 @@ NetExpr* NetESFunc::evaluate_min_max_(ID id, const NetExpr*arg0_,
       return res;
 }
 
-NetEConst* NetESFunc::evaluate_countbits_(const NetExpr* /*arg0*/,
-                                          const NetExpr* /*arg1*/) const
+static void no_string_arg(const NetESFunc*info, unsigned arg_num)
 {
-      return 0;
+      cerr << info->get_fileline() << ": error: constant function "
+           << info->name() << "() does not support a string argument ("
+           << arg_num+1 << ")." << endl;
 }
 
-NetEConst* NetESFunc::evaluate_countones_(const NetExpr* /*arg*/) const
+NetEConst* NetESFunc::evaluate_countbits_() const
 {
-      return 0;
+      const NetEConst*tmpi = dynamic_cast<const NetEConst*>(parms_[0]);
+
+      NetEConst*res = 0;
+
+      if (tmpi) {
+	    verinum value = tmpi->value();
+
+	    if (value.is_string()) {
+		  no_string_arg(this, 0);
+		  return 0;
+	    }
+
+	      /* Find which values need to be counted. */
+	    bool count_0 = false;
+	    bool count_1 = false;
+	    bool count_z = false;
+	    bool count_x = false;
+	    for (unsigned arg=1; arg < parms_.size(); ++arg) {
+		  const NetEConst*argi = dynamic_cast<const NetEConst*>(parms_[arg]);
+		  if (! argi) return 0;
+		  verinum check_for = argi->value();
+		  if (check_for.is_string()) {
+			no_string_arg(this, arg);
+			return 0;
+		  }
+		  switch (check_for[0]) {
+		    case verinum::V0:
+			count_0 = true;
+			break;
+		    case verinum::V1:
+			count_1 = true;
+			break;
+		    case verinum::Vz:
+			count_z = true;
+			break;
+		    case verinum::Vx:
+			count_x = true;
+			break;
+		  }
+	    }
+
+	      /* Search each bit of the vector looking for the values to
+	       * be counted. */
+	    int count = 0;
+	    for (unsigned bit=0; bit < value.len(); ++bit) {
+		  switch (value[bit]) {
+		    case verinum::V0:
+			if (count_0) ++count;
+			break;
+		    case verinum::V1:
+			if (count_1) ++count;
+			break;
+		    case verinum::Vz:
+			if (count_z) ++count;
+			break;
+		    case verinum::Vx:
+			if (count_x) ++count;
+			break;
+		  }
+	    }
+
+	    verinum tmp (count, integer_width);
+	    tmp.has_sign(true);
+	    res = new NetEConst(tmp);
+	    ivl_assert(*this, res);
+      }
+
+      return res;
+}
+
+NetEConst* NetESFunc::evaluate_countones_(const NetExpr* arg) const
+{
+      const NetEConst*tmpi = dynamic_cast<const NetEConst*>(arg);
+
+      NetEConst*res = 0;
+
+      if (tmpi) {
+	    verinum value = tmpi->value();
+	    int count = 0;
+
+	    if (value.is_string()) {
+		  no_string_arg(this, 0);
+		  return 0;
+	    }
+
+	    for (unsigned bit=0; bit < value.len(); ++bit) {
+		  if (value[bit] == verinum::V1) ++count;
+	    }
+
+	    verinum tmp (count, integer_width);
+	    tmp.has_sign(true);
+	    res = new NetEConst(tmp);
+	    ivl_assert(*this, res);
+      }
+
+      return res;
 }
 
 /* Get the total number of dimensions for the given expression. */
@@ -1962,19 +2045,92 @@ NetEConst* NetESFunc::evaluate_dimensions_(const NetExpr*arg) const
       return new NetEConst(verinum(verinum(res), integer_width));
 }
 
-NetEConst* NetESFunc::evaluate_isunknown_(const NetExpr* /*arg*/) const
+NetEConst* NetESFunc::evaluate_isunknown_(const NetExpr* arg) const
 {
-      return 0;
+      const NetEConst*tmpi = dynamic_cast<const NetEConst*>(arg);
+
+      NetEConst*res = 0;
+
+      if (tmpi) {
+	    verinum value = tmpi->value();
+	    unsigned is_unknown = 1;
+
+	    if (value.is_string()) {
+		  no_string_arg(this, 0);
+		  return 0;
+	    }
+
+	    if (value.is_defined()) is_unknown = 0;
+
+	    verinum tmp (is_unknown, 1U);
+	    tmp.has_sign(false);
+	    res = new NetEConst(tmp);
+	    ivl_assert(*this, res);
+      }
+
+      return res;
 }
 
-NetEConst* NetESFunc::evaluate_onehot_(const NetExpr* /*arg*/) const
+static bool is_onehot(verinum&value, bool zero_is_okay)
 {
-      return 0;
+      bool found_a_one = false;
+
+      for (unsigned bit=0; bit < value.len(); ++bit) {
+	    if (value[bit] == verinum::V1) {
+		  if (found_a_one) return false;
+		  found_a_one = true;
+	    }
+      }
+
+	/* If no one bit was found return true if zero is okay. */
+      if (zero_is_okay) found_a_one = true;
+      return found_a_one;
 }
 
-NetEConst* NetESFunc::evaluate_onehot0_(const NetExpr* /*arg*/) const
+NetEConst* NetESFunc::evaluate_onehot_(const NetExpr* arg) const
 {
-      return 0;
+      const NetEConst*tmpi = dynamic_cast<const NetEConst*>(arg);
+
+      NetEConst*res = 0;
+
+      if (tmpi) {
+	    verinum value = tmpi->value();
+
+	    if (value.is_string()) {
+		  no_string_arg(this, 0);
+		  return 0;
+	    }
+
+	    verinum tmp (is_onehot(value, false), 1U);
+	    tmp.has_sign(false);
+	    res = new NetEConst(tmp);
+	    ivl_assert(*this, res);
+      }
+
+      return res;
+}
+
+NetEConst* NetESFunc::evaluate_onehot0_(const NetExpr* arg) const
+{
+      const NetEConst*tmpi = dynamic_cast<const NetEConst*>(arg);
+
+      NetEConst*res = 0;
+
+      if (tmpi) {
+	    verinum value = tmpi->value();
+
+	    if (value.is_string()) {
+		  no_string_arg(this, 0);
+		  return 0;
+	    }
+
+	    verinum tmp (is_onehot(value, true), 1U);
+	    tmp.has_sign(false);
+	    res = new NetEConst(tmp);
+	    ivl_assert(*this, res);
+      }
+
+      return res;
 }
 
 /* Get the number of unpacked dimensions for the given expression. */
@@ -2009,6 +2165,12 @@ static bool check_dimension(const NetExpr*dim_expr, long &dim)
 static bool get_array_info(const NetExpr*arg, long dim,
                            long &left, long &right, bool&defer)
 {
+      if (const NetEConstParam*param = dynamic_cast<const NetEConstParam*>(arg)) {
+	assert(dim == 1);
+	left = param->expr_width() - 1;
+	right = 0;
+	return false;
+      }
 	/* The argument must be a signal that has enough dimensions. */
       const NetESignal*esig = dynamic_cast<const NetESignal*>(arg);
       if (esig == 0) return true;
@@ -2140,7 +2302,7 @@ NetExpr* NetESFunc::evaluate_two_arg_(ID id, const NetExpr*arg0,
 {
       switch (id) {
 	  case CTBITS:
-	    return evaluate_countbits_(arg0, arg1);
+	    return evaluate_countbits_();
 	      /* The array functions are handled together. */
 	  case HIGH:
 	  case INCR:
@@ -2211,12 +2373,12 @@ NetESFunc::ID NetESFunc::built_in_id_() const
 	    built_in_func["$unpacked_dimensions" ] = UPDIMS;
       }
 
-	/* These are available in 1800-2009 and later. */
+	/* This is available in 1800-2009 and later. */
       if (funcs_need_init && (generation_flag >= GN_VER2009)) {
 	    built_in_func["$countones" ] = CTONES;
       }
 
-	/* These are available in 1800-2012 and later. */
+	/* This is available in 1800-2012 and later. */
       if (funcs_need_init && (generation_flag >= GN_VER2012)) {
 	    built_in_func["$countbits" ] = CTBITS;
       }
@@ -2243,7 +2405,11 @@ NetESFunc::ID NetESFunc::built_in_id_() const
 
 NetExpr* NetESFunc::eval_tree()
 {
-	/* Get the ID for this system function if it is can be used as a
+	/* We don't support evaluating overridden functions. */
+      if (is_overridden_)
+	    return 0;
+
+	/* Get the ID for this system function if it can be used as a
 	 * constant function. */
       ID id = built_in_id_();
       if (id == NOT_BUILT_IN) return 0;
@@ -2251,8 +2417,9 @@ NetExpr* NetESFunc::eval_tree()
       switch (parms_.size()) {
 	  case 1:
 	    if (! takes_nargs_(id, 1)) {
-		  cerr << get_fileline() << ": error: " << name_
-		       << "() does not support a single argument." << endl;
+		  cerr << get_fileline() << ": error: constant function "
+		       << name_ << "() does not support a single argument."
+		       << endl;
 		  return 0;
 	    }
 	    eval_expr(parms_[0]);
@@ -2260,8 +2427,9 @@ NetExpr* NetESFunc::eval_tree()
 
 	  case 2:
 	    if (! takes_nargs_(id, 2)) {
-		  cerr << get_fileline() << ": error: " << name_
-		       << "() does not support two arguments." << endl;
+		  cerr << get_fileline() << ": error: constant function "
+		       << name_ << "() does not support two arguments."
+		       << endl;
 		  return 0;
 	    }
 	    eval_expr(parms_[0]);
@@ -2271,15 +2439,21 @@ NetExpr* NetESFunc::eval_tree()
 	  default:
 	      /* Check to see if the function was called correctly. */
 	    if (! takes_nargs_(id, parms_.size())) {
-		  cerr << get_fileline() << ": error: " << name_
-		       << "() does not support " << parms_.size()
+		  cerr << get_fileline() << ": error: constant function "
+		       << name_ << "() does not support " << parms_.size()
 		       << " arguments." << endl;
 		  return 0;
 	    }
-// HERE: Need to add support for a multi argument $countbits().
-	    cerr << get_fileline() << ": sorry: functions with "
-	         << parms_.size() << " arguments are not supported: "
-	         << name_ << "()." << endl;
+	    if (id == CTBITS) {
+		  for (unsigned bit = 0; bit < parms_.size(); ++bit) {
+			eval_expr(parms_[bit]);
+		  }
+		  return evaluate_countbits_();
+	    } else {
+		  cerr << get_fileline() << ": sorry: constant functions with "
+		       << parms_.size() << " arguments are not supported: "
+		       << name_ << "()." << endl;
+	    }
 	    return 0;
       }
 }

exposenodes.cc

@@ -0,0 +1,129 @@
+/*
+ * Copyright (c) 2016-2021 Martin Whitaker (icarus@martin-whitaker.me.uk)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+
+# include "config.h"
+
+# include  <cstdlib>
+# include  <sstream>
+# include  "netlist.h"
+# include  "functor.h"
+# include  "compiler.h"
+# include  "ivl_assert.h"
+
+using namespace std;
+
+/*
+ * The exposenodes functor is primarily provided for use by the vlog95
+ * target. To implement some LPM objects, it needs to take a bit or part
+ * of one of the LPM inputs. If that input is not connected to a real
+ * net in the design, we need to create a net at that point so that
+ * there is something to which we can apply a bit or part select. This
+ * has the effect of splitting the synthesised structure at that point.
+ * Rather than creating a new net, we just look for a temporary net
+ * created by the synthesis process (there should be at least one) and
+ * reset its "local" flag. We also prepend another '_' to the synthetic
+ * name to avoid name collisions when we recompile the vlog95 output
+ * (because NetScope::local_symbol() doesn't actually check that the
+ * name it generates is unique).
+ */
+
+struct exposenodes_functor  : public functor_t {
+
+      unsigned count;
+
+      virtual void lpm_mux(Design*des, NetMux*obj);
+      virtual void lpm_part_select(Design*des, NetPartSelect*obj);
+      virtual void lpm_substitute(Design*des, NetSubstitute*obj);
+};
+
+static bool expose_nexus(Nexus*nex)
+{
+      NetNet*sig = 0;
+      for (Link*cur = nex->first_nlink() ; cur ; cur = cur->next_nlink()) {
+
+	      // Don't expose nodes that are attached to constants
+	    if (dynamic_cast<NetConst*> (cur->get_obj()))
+		  return false;
+	    if (dynamic_cast<NetLiteral*> (cur->get_obj()))
+		  return false;
+
+	    NetNet*cur_sig = dynamic_cast<NetNet*> (cur->get_obj());
+	    if (cur_sig == 0)
+		  continue;
+
+	    if (!cur_sig->local_flag())
+		  return false;
+
+	    sig = cur_sig;
+      }
+      assert(sig);
+      ostringstream res;
+      res << "_" << sig->name();
+      sig->rename(lex_strings.make(res.str()));
+      sig->local_flag(false);
+      return true;
+}
+
+/*
+ * The vlog95 target implements a wide mux as a hierarchy of 2:1 muxes,
+ * picking off one bit of the select input at each level of the hierarchy.
+ */
+void exposenodes_functor::lpm_mux(Design*, NetMux*obj)
+{
+      if (obj->sel_width() == 1)
+	    return;
+
+      if (expose_nexus(obj->pin_Sel().nexus()))
+	    count += 1;
+}
+
+/*
+ * A VP part select is going to select a part from its input.
+ */
+void exposenodes_functor::lpm_part_select(Design*, NetPartSelect*obj)
+{
+      if (obj->dir() != NetPartSelect::VP)
+	    return;
+
+      if (expose_nexus(obj->pin(1).nexus()))
+	    count += 1;
+}
+
+/*
+ * A substitute is going to select one or two parts from the wider input signal.
+ */
+void exposenodes_functor::lpm_substitute(Design*, NetSubstitute*obj)
+{
+      if (expose_nexus(obj->pin(1).nexus()))
+	    count += 1;
+}
+
+void exposenodes(Design*des)
+{
+      exposenodes_functor exposenodes;
+      exposenodes.count = 0;
+      if (verbose_flag) {
+	    cout << " ... Look for intermediate nodes" << endl << flush;
+      }
+      des->functor(&exposenodes);
+      if (verbose_flag) {
+	    cout << " ... Exposed " << exposenodes.count
+		 << " intermediate signals." << endl << flush;
+      }
+}

expr_synth.cc

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1999-2013 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 1999-2020 Stephen Williams (steve@icarus.com)
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -28,6 +28,8 @@
 # include  "netmisc.h"
 # include  "ivl_assert.h"
 
+using namespace std;
+
 static NetNet* convert_to_real_const(Design*des, NetScope*scope, NetEConst*expr)
 {
       verireal vrl(expr->value().as_double());
@@ -274,7 +276,18 @@ NetNet* NetEBComp::synthesize(Design*des, NetScope*scope, NetExpr*root)
 
       if (op_ == 'E' || op_ == 'N') {
 	    NetCaseCmp*gate = new NetCaseCmp(scope, scope->local_symbol(),
-					     width, op_=='E'?NetCaseCmp::EEQ:NetCaseCmp::NEQ);
+					     width, op_=='E' ? NetCaseCmp::EEQ : NetCaseCmp::NEQ);
+	    gate->set_line(*this);
+	    connect(gate->pin(0), osig->pin(0));
+	    connect(gate->pin(1), lsig->pin(0));
+	    connect(gate->pin(2), rsig->pin(0));
+	    des->add_node(gate);
+	    return osig;
+      }
+
+      if (op_ == 'w' || op_ == 'W') {
+	    NetCaseCmp*gate = new NetCaseCmp(scope, scope->local_symbol(),
+					     width, op_=='w' ? NetCaseCmp::WEQ : NetCaseCmp::WNE);
 	    gate->set_line(*this);
 	    connect(gate->pin(0), osig->pin(0));
 	    connect(gate->pin(1), lsig->pin(0));
@@ -335,6 +348,7 @@ NetNet* NetEBComp::synthesize(Design*des, NetScope*scope, NetExpr*root)
 		  des->errors += 1;
 		  return 0;
 	    }
+	    // fallthrough
 	  case 'e': // ==
 	    connect(dev->pin_AEB(), osig->pin(0));
 	    break;
@@ -353,6 +367,7 @@ NetNet* NetEBComp::synthesize(Design*des, NetScope*scope, NetExpr*root)
 		  des->errors += 1;
 		  return 0;
 	    }
+	    // fallthrough
 	  case 'n': // !=
 	    connect(dev->pin_ANEB(), osig->pin(0));
 	    break;
@@ -386,7 +401,8 @@ NetNet* NetEBPow::synthesize(Design*des, NetScope*scope, NetExpr*root)
       powr->set_line(*this);
       des->add_node(powr);
 
-      powr->set_signed( has_sign() );
+        // The lpm_pwr object only cares about the signedness of the exponent.
+      powr->set_signed( right_->has_sign() );
 
       connect(powr->pin_DataA(), lsig->pin(0));
       connect(powr->pin_DataB(), rsig->pin(0));
@@ -531,27 +547,40 @@ NetNet* NetEBLogic::synthesize(Design*des, NetScope*scope, NetExpr*root)
 	    return 0;
       }
 
-      netvector_t*osig_tmp = new netvector_t(expr_type());
-      NetNet*osig = new NetNet(scope, scope->local_symbol(),
-			       NetNet::IMPLICIT, osig_tmp);
-      osig->set_line(*this);
-      osig->local_flag(true);
-
       NetLogic*olog;
       perm_string oname = scope->local_symbol();
 
 	/* Create the logic OR/AND gate. This has a single bit output,
 	 * with single bit inputs for the two operands. */
-      if (op() == 'o') {
-	    olog = new NetLogic(scope, oname, 3, NetLogic::OR, 1, true);
-      } else {
-	    assert(op() == 'a');
+      switch (op()) {
+	case 'a':
 	    olog = new NetLogic(scope, oname, 3, NetLogic::AND, 1, true);
+	    break;
+	case 'o':
+	    olog = new NetLogic(scope, oname, 3, NetLogic::OR, 1, true);
+	    break;
+	case 'q':
+	    olog = new NetLogic(scope, oname, 3, NetLogic::IMPL, 1, true);
+	    break;
+	case 'Q':
+	    olog = new NetLogic(scope, oname, 3, NetLogic::EQUIV, 1, true);
+	    break;
+	default:
+	    cerr << get_fileline() << ": sorry: "
+	         << human_readable_op(op_)
+	         << " is not currently supported." << endl;
+	    des->errors += 1;
+	    return 0;
       }
-
       olog->set_line(*this);
       des->add_node(olog);
 
+      netvector_t*osig_tmp = new netvector_t(expr_type());
+      NetNet*osig = new NetNet(scope, scope->local_symbol(),
+			       NetNet::IMPLICIT, osig_tmp);
+      osig->set_line(*this);
+      osig->local_flag(true);
+
       connect(osig->pin(0), olog->pin(0));
 
 	/* The left and right operands have already been reduced to a
@@ -733,12 +762,18 @@ NetNet* NetEConcat::synthesize(Design*des, NetScope*scope, NetExpr*root)
 	    }
       }
 
-      if (flag == false) return 0;
+      if (flag == false) {
+	    delete[]tmp;
+	    return 0;
+      }
 
       ivl_assert(*this, data_type != IVL_VT_NO_TYPE);
 
 	/* If this is a replication of zero just return 0. */
-      if (expr_width() == 0) return 0;
+      if (expr_width() == 0) {
+	    delete[]tmp;
+	    return 0;
+      }
 
 	/* Make a NetNet object to carry the output vector. */
       perm_string path = scope->local_symbol();
@@ -1138,18 +1173,29 @@ NetNet* NetESelect::synthesize(Design *des, NetScope*scope, NetExpr*root)
       if (sub->vector_width() == expr_width())
 	    return sub;
 
-	// The vector_width is not exactly right, so the source is
-	// probably asking for padding. Create nodes to do sign
-	// extension or 0 extension, depending on the has_sign() mode
-	// of the expression.
-
       netvector_t*net_vec = new netvector_t(expr_type(), expr_width()-1, 0);
       net_vec->set_signed(has_sign());
       NetNet*net = new NetNet(scope, scope->local_symbol(),
 			      NetNet::IMPLICIT, net_vec);
       net->set_line(*this);
       net->local_flag(true);
-      if (has_sign()) {
+
+	// It may still happen that the expression is wider than the selection,
+	// and there was no part select created earlier (size casting).
+      if(expr_width() < sub->vector_width()) {
+	    NetPartSelect*sel = new NetPartSelect(sub, 0, expr_width(),
+                                                  NetPartSelect::VP, has_sign());
+	    sel->set_line(*this);
+	    des->add_node(sel);
+
+	    connect(net->pin(0), sel->pin(0));
+
+	// The vector_width is not exactly right, so the source is
+	// probably asking for padding. Create nodes to do sign
+	// extension or 0 extension, depending on the has_sign() mode
+	// of the expression.
+
+      } else if (has_sign()) {
 	    NetSignExtend*pad = new NetSignExtend(scope,
 						  scope->local_symbol(),
 						  expr_width());
@@ -1166,7 +1212,6 @@ NetNet* NetESelect::synthesize(Design *des, NetScope*scope, NetExpr*root)
 	    cat->set_line(*this);
 	    des->add_node(cat);
 
-	    assert(expr_width() > sub->vector_width());
 	    unsigned pad_width = expr_width() - sub->vector_width();
 	    verinum pad((uint64_t)0, pad_width);
 	    NetConst*con = new NetConst(scope, scope->local_symbol(),
@@ -1278,6 +1323,8 @@ NetNet* NetESignal::synthesize(Design*des, NetScope*scope, NetExpr*root)
 						  net_->vector_width()-1, 0);
 	    NetNet*tmp = new NetNet(scope, scope->local_symbol(),
 				    NetNet::IMPLICIT, tmp_vec);
+	    tmp->set_line(*this);
+	    tmp->local_flag(true);
 	    verinum tmp_val ((uint64_t)scope->genvar_tmp_val, net_->vector_width());
 	    NetConst*tmp_const = new NetConst(scope, scope->local_symbol(), tmp_val);
 	    tmp_const->set_line(*this);
@@ -1329,6 +1376,7 @@ static NetEvWait* make_func_trigger(Design*des, NetScope*scope, NetExpr*root)
       if (nset && (nset->size() > 0)) {
             NetEvent*ev = new NetEvent(scope->local_symbol());
             ev->set_line(*root);
+            ev->local_flag(true);
 
             NetEvProbe*pr = new NetEvProbe(scope, scope->local_symbol(),
                                            ev, NetEvProbe::ANYEDGE,

functor.cc

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1999-2012 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 1999-2016 Stephen Williams (steve@icarus.com)
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -78,6 +78,10 @@ void functor_t::lpm_ff(Design*, NetFF*)
 {
 }
 
+void functor_t::lpm_latch(Design*, NetLatch*)
+{
+}
+
 void functor_t::lpm_logic(Design*, NetLogic*)
 {
 }
@@ -102,6 +106,10 @@ void functor_t::sign_extend(Design*, NetSignExtend*)
 {
 }
 
+void functor_t::lpm_substitute(Design*, NetSubstitute*)
+{
+}
+
 void functor_t::lpm_ureduce(Design*, NetUReduce*)
 {
 }
@@ -215,6 +223,11 @@ void NetFF::functor_node(Design*des, functor_t*fun)
       fun->lpm_ff(des, this);
 }
 
+void NetLatch::functor_node(Design*des, functor_t*fun)
+{
+      fun->lpm_latch(des, this);
+}
+
 void NetLiteral::functor_node(Design*des, functor_t*fun)
 {
       fun->lpm_literal(des, this);
@@ -255,6 +268,11 @@ void NetSignExtend::functor_node(Design*des, functor_t*fun)
       fun->sign_extend(des, this);
 }
 
+void NetSubstitute::functor_node(Design*des, functor_t*fun)
+{
+      fun->lpm_substitute(des, this);
+}
+
 void NetUReduce::functor_node(Design*des, functor_t*fun)
 {
       fun->lpm_ureduce(des, this);

functor.h

@@ -1,7 +1,7 @@
 #ifndef IVL_functor_H
 #define IVL_functor_H
 /*
- * Copyright (c) 1999-2014 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 1999-2016 Stephen Williams (steve@icarus.com)
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -75,6 +75,9 @@ struct functor_t {
 	/* This method is called for each FF in the design. */
       virtual void lpm_ff(class Design*des, class NetFF*);
 
+	/* This method is called for each LATCH in the design. */
+      virtual void lpm_latch(class Design*des, class NetLatch*);
+
 	/* Handle LPM combinational logic devices. */
       virtual void lpm_logic(class Design*des, class NetLogic*);
 
@@ -89,6 +92,9 @@ struct functor_t {
 	/* This method is called for each power. */
       virtual void lpm_pow(class Design*des, class NetPow*);
 
+	/* This method is called for each part substitute. */
+      virtual void lpm_substitute(class Design*des, class NetSubstitute*);
+
 	/* This method is called for each unary reduction gate. */
       virtual void lpm_ureduce(class Design*des, class NetUReduce*);
 

iverilog-vpi.man.in

@@ -1,10 +1,10 @@
-.TH iverilog-vpi 1 "April 17th, 2009" "" "Version %M.%m.%n %E"
+.TH iverilog-vpi 1 "Jan 29th, 2017" "" "Version %M.%n%E"
 .SH NAME
 iverilog-vpi - Compile front end for VPI modules
 
 .SH SYNOPSIS
 .B iverilog-vpi
-[\-\-name=\fIname\fP]
+[options]
 \fIsourcefile\fP...
 
 .SH DESCRIPTION
@@ -15,9 +15,9 @@ list of C or C++ source files, and generates as output a linked VPI
 module. See the \fBvvp\fP(1) man page for a description of how the
 linked module is loaded by a simulation.
 
-The output is named after the first source file. For example, if the
-first source file is named \fIfoo.c\fP, the output becomes
-\fIfoo.vpi\fP.
+By default the output is named after the first source file. For
+example, if the first source file is named \fIfoo.c\fP, the output
+becomes \fIfoo.vpi\fP.
 
 .SH OPTIONS
 \fIiverilog\-vpi\fP accepts the following options:
@@ -26,10 +26,15 @@ first source file is named \fIfoo.c\fP, the output becomes
 Include the named library in the link of the VPI module. This allows
 VPI modules to further reference external libraries.
 
+.TP 8
+.B -L\fIdirectory\fP
+Add \fIdirectory\fP to the list of directories that will be searched
+for library files.
+
 .TP 8
 .B -I\fIdirectory\fP
-Add \fIdirectory\fP to the list of directories that will be search for
-header files.
+Add \fIdirectory\fP to the list of directories that will be searched
+for header files.
 
 .TP 8
 .B -D\fIdefine\fP
@@ -41,46 +46,38 @@ Normally, the output VPI module will be named after the first source
 file passed to the command. This flag sets the name (without the .vpi
 suffix) of the output vpi module.
 
-.TP 8
-.B --install-dir
-This flag causes the program to print the install directory for VPI
-modules, then exit. It is a convenience for makefiles or automated
-plug-in installers.
-
-.TP 8
-.B --cflags, --ldflags and --ldlibs
-These flags provide compile time information.
-
 .SH "PC-ONLY OPTIONS"
 
-The PC port of \fIiverilog\-vpi\fP includes two special flags needed to
-support the more intractable development environment. These flags help
-the program locate parts that it needs.
+When built as a native Windows program (using the MinGW toolchain),
+by default \fIiverilog\-vpi\fP will attempt to locate the MinGW tools
+needed to compile a VPI module on the system path (as set by the PATH
+environment variable). As an alternative, the user may specify the
+location of the MinGW tools via the following option.
 
 .TP 8
 .B -mingw=\fIpath\fP
-Tell the program the root of the Mingw compiler tool suite. The
+Tell the program the root of the MinGW compiler tool suite. The
 \fBvvp\fP runtime is compiled with this compiler, and this is the
-compiler that \fIiverilog\-vpi\fP expects to use to compile your source
-code. This is normally not needed, and if you do use it, it is only
-needed once. The compiler will save the \fIpath\fP in the registry for
-use later.
+compiler that \fIiverilog\-vpi\fP expects to use to compile your
+source code. If this option accompanies a list of files, it will
+apply to the current build only. If this option is provided on its
+own, \fIiverilog\-vpi\fP will save the \fIpath\fP in the registry
+and use that path in preference to the system path for subsequent
+operations, avoiding the need to specify it on the command line
+every time.
+
+.SH "INFORMATIONAL OPTIONS"
+
+\fIiverilog\-vpi\fP includes additional flags to let Makefile gurus
+peek at the configuration of the \fIiverilog\fP installation.  This way,
+Makefiles can be written that handle complex VPI builds natively, and
+without hard-coding values that depend on the system and installation.
+If used at all, these options must be used one at a time, and without
+any other options or directives.
 
 .TP 8
-.B -ivl=\fIpath\fP
-Set for the use during compilation the root if the Icarus Verilog
-install. This is the place where you installed Icarus Verilog when you
-ran the installer. This flag is also only needed once, and the path is
-stored in the registry for future use.
-
-.SH "UNIX-ONLY OPTIONS"
-
-The UNIX version of \fIiverilog\-vpi\fP includes additional flags to
-let Makefile gurus peek at the configuration of the \fIiverilog\fP
-installation.  This way, Makefiles can be written that handle complex VPI
-builds natively, and without hard-coding values that depend on the
-system and installation.  If used at all, these options must be
-used one at a time, and without any other options or directives.
+.B --install-dir
+Print the install directory for VPI modules.
 
 .TP 8
 .B --cflags
@@ -95,11 +92,6 @@ Print the linker flags (LDFLAGS) needed to link a VPI module.
 .B --ldlibs
 Print the libraries (LDLIBS) needed to link a VPI module.
 
-.TP 8
-.B -m32
-On 64bit systems that support it (and support vvp32) this flag
-requests a 32bit vpi binary instead of the default 64bit binary.
-
 .P
 Example GNU makefile that takes advantage of these flags:
 .IP "" 4
@@ -123,12 +115,12 @@ Steve Williams ([email protected])
 
 .SH SEE ALSO
 iverilog(1), vvp(1),
-.BR "<http://www.icarus.com/eda/verilog/>",
-.BR "<http://www.mingw.org>",
+.BR "<http://iverilog.icarus.com/>",
+.BR "<http://mingw-w64.yaxm.org/>",
 
 .SH COPYRIGHT
 .nf
-Copyright \(co  2002\-2009 Stephen Williams
+Copyright \(co  2002\-2017 Stephen Williams
 
 This document can be freely redistributed according to the terms of the
 GNU General Public License version 2.0

iverilog-vpi.sh

@@ -35,6 +35,7 @@ CCSRC=
 CXSRC=
 OBJ=
 LIB=
+LIBDIR=
 OUT=
 INCOPT=
 DEFS=
@@ -81,6 +82,9 @@ do
     -l*) LIB="$LIB $parm"
 	 ;;
 
+    -L*) LIBDIR="$LIBDIR $parm"
+	 ;;
+
     -I*) INCOPT="$INCOPT $parm"
 	 ;;
 
@@ -92,6 +96,11 @@ do
 	 exit;
 	 ;;
 
+    --ccflags)
+	 echo "$CXXFLAGS"
+	 exit;
+	 ;;
+
     --ldflags)
 	 echo "$LDFLAGS"
 	 exit;
@@ -148,4 +157,4 @@ then
 fi
 
 echo "Making $OUT from $OBJ..."
-exec $LD -o $OUT $LDFLAGS $OBJ $LIB $LDLIBS
+exec $LD -o $OUT $LDFLAGS $LIBDIR $OBJ $LIB $LDLIBS

ivl.def

@@ -125,6 +125,7 @@ ivl_lpm_enable
 ivl_lpm_file
 ivl_lpm_lineno
 ivl_lpm_name
+ivl_lpm_negedge
 ivl_lpm_q
 ivl_lpm_scope
 ivl_lpm_select
@@ -180,6 +181,7 @@ ivl_parameter_width
 ivl_path_condit
 ivl_path_delay
 ivl_path_is_condit
+ivl_path_is_parallel
 ivl_path_scope
 ivl_path_source
 ivl_path_source_negedge
@@ -210,6 +212,9 @@ ivl_scope_enumerates
 ivl_scope_event
 ivl_scope_events
 ivl_scope_file
+ivl_scope_func_type
+ivl_scope_func_signed
+ivl_scope_func_width
 ivl_scope_is_auto
 ivl_scope_is_cell
 ivl_scope_lineno
@@ -276,6 +281,7 @@ ivl_stmt_block_stmt
 ivl_stmt_call
 ivl_stmt_case_count
 ivl_stmt_case_expr
+ivl_stmt_case_quality
 ivl_stmt_case_stmt
 ivl_stmt_cond_expr
 ivl_stmt_cond_false
@@ -290,6 +296,7 @@ ivl_stmt_lval
 ivl_stmt_lvals
 ivl_stmt_lwidth
 ivl_stmt_name
+ivl_stmt_needs_t0_trigger
 ivl_stmt_nevent
 ivl_stmt_opcode
 ivl_stmt_parm

ivl_alloc.h

@@ -26,6 +26,7 @@
 #  include <stdio.h>
 #endif
 
+#if defined(__GNUC__)
 /*
  * Define a safer version of malloc().
  */
@@ -82,5 +83,6 @@
       } \
       __ivl_rtn; \
 })
+#endif
 
 #endif /* IVL_ivl_alloc_H */

ivl_assert.h

@@ -1,7 +1,7 @@
 #ifndef IVL_ivl_assert_H
 #define IVL_ivl_assert_H
 /*
- * Copyright (c) 2007-2014 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 2007-2021 Stephen Williams (steve@icarus.com)
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -24,9 +24,9 @@
 #define ivl_assert(tok, expression)  \
       do { \
 	    if (! (expression)) { \
-		  cerr << (tok).get_fileline() << ": assert: " \
-		       << __FILE__ << ":" << __LINE__ \
-		       << ": failed assertion " << #expression << endl; \
+		  std::cerr << (tok).get_fileline() << ": assert: " \
+			    << __FILE__ << ":" << __LINE__ \
+			    << ": failed assertion " << #expression << std::endl; \
 		  abort(); \
 	    } \
       } while (0)

ivl_target.h

@@ -1,7 +1,7 @@
 #ifndef IVL_ivl_target_H
 #define IVL_ivl_target_H
 /*
- * Copyright (c) 2000-2014 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 2000-2020 Stephen Williams (steve@icarus.com)
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -41,6 +41,12 @@
 # define __attribute__(x)
 #endif
 
+#if defined(__cplusplus) && defined(_MSC_VER)
+# define ENUM_UNSIGNED_INT : unsigned int
+#else
+# define ENUM_UNSIGNED_INT
+#endif
+
 _BEGIN_DECL
 
 /*
@@ -201,7 +207,7 @@ typedef enum ivl_dis_domain_e {
       IVL_DIS_CONTINUOUS = 2
 } ivl_dis_domain_t;
 
-typedef enum ivl_drive_e {
+typedef enum ivl_drive_e ENUM_UNSIGNED_INT {
       IVL_DR_HiZ    = 0,
       IVL_DR_SMALL  = 1,
       IVL_DR_MEDIUM = 2,
@@ -243,7 +249,7 @@ typedef enum ivl_expr_type_e {
       IVL_EX_UNARY = 14
 } ivl_expr_type_t;
 
-typedef enum ivl_select_type_e {
+typedef enum ivl_select_type_e ENUM_UNSIGNED_INT {
       IVL_SEL_OTHER = 0,
       IVL_SEL_IDX_UP = 1,
       IVL_SEL_IDX_DOWN = 2
@@ -259,6 +265,8 @@ typedef enum ivl_logic_e {
       IVL_LO_BUFT   = 24, /* transparent bufz. (NOT "tri-state") */
       IVL_LO_BUFZ   =  5,
       IVL_LO_CMOS   = 22,
+      IVL_LO_EQUIV  = 25,
+      IVL_LO_IMPL   = 26,
       IVL_LO_NAND   =  6,
       IVL_LO_NMOS   =  7,
       IVL_LO_NOR    =  8,
@@ -274,7 +282,6 @@ typedef enum ivl_logic_e {
       IVL_LO_RPMOS  = 16,
       IVL_LO_XNOR   = 18,
       IVL_LO_XOR    = 19,
-
       IVL_LO_UDP    = 21
 } ivl_logic_t;
 
@@ -300,8 +307,10 @@ typedef enum ivl_lpm_type_e {
       IVL_LPM_CONCAT = 16,
       IVL_LPM_CONCATZ = 36, /* Transparent concat */
       IVL_LPM_CMP_EEQ= 18, /* Case EQ (===) */
-      IVL_LPM_CMP_EQX= 37, /* Windcard EQ (==?) */
+      IVL_LPM_CMP_EQX= 37, /* Wildcard EQ (casex) */
       IVL_LPM_CMP_EQZ= 38, /* casez EQ */
+      IVL_LPM_CMP_WEQ= 41,
+      IVL_LPM_CMP_WNE= 42,
       IVL_LPM_CMP_EQ = 10,
       IVL_LPM_CMP_GE =  1,
       IVL_LPM_CMP_GT =  2,
@@ -309,6 +318,7 @@ typedef enum ivl_lpm_type_e {
       IVL_LPM_CMP_NEE= 19, /* Case NE (!==) */
       IVL_LPM_DIVIDE = 12,
       IVL_LPM_FF     =  3,
+      IVL_LPM_LATCH  = 40,
       IVL_LPM_MOD    = 13,
       IVL_LPM_MULT   =  4,
       IVL_LPM_MUX    =  5,
@@ -345,10 +355,13 @@ typedef enum ivl_path_edge_e {
 
 /* Processes are initial, always, or final blocks with a statement. This is
    the type of the ivl_process_t object. */
-typedef enum ivl_process_type_e {
-      IVL_PR_INITIAL = 0,
-      IVL_PR_ALWAYS  = 1,
-      IVL_PR_FINAL   = 2
+typedef enum ivl_process_type_e ENUM_UNSIGNED_INT {
+      IVL_PR_INITIAL      = 0,
+      IVL_PR_ALWAYS       = 1,
+      IVL_PR_ALWAYS_COMB  = 3,
+      IVL_PR_ALWAYS_FF    = 4,
+      IVL_PR_ALWAYS_LATCH = 5,
+      IVL_PR_FINAL        = 2
 } ivl_process_type_t;
 
 /* These are the sorts of reasons a scope may come to be. These types
@@ -422,6 +435,14 @@ typedef enum ivl_statement_type_e {
       IVL_ST_WHILE   = 23
 } ivl_statement_type_t;
 
+/* Case statements can be tagged as unique/unique0/priority. */
+typedef enum ivl_case_quality_t {
+      IVL_CASE_QUALITY_BASIC    = 0,  /* no quality flags */
+      IVL_CASE_QUALITY_UNIQUE   = 1,
+      IVL_CASE_QUALITY_UNIQUE0  = 2,
+      IVL_CASE_QUALITY_PRIORITY = 3
+} ivl_case_quality_t;
+
 /* SystemVerilog allows a system function to be called as a task. */
 typedef enum ivl_sfunc_as_task_e {
       IVL_SFUNC_AS_TASK_ERROR   = 0,
@@ -431,7 +452,7 @@ typedef enum ivl_sfunc_as_task_e {
 
 /* This is the type of a variable, and also used as the type for an
    expression. */
-typedef enum ivl_variable_type_e {
+typedef enum ivl_variable_type_e ENUM_UNSIGNED_INT {
       IVL_VT_VOID    = 0,  /* Not used */
       IVL_VT_NO_TYPE = 1,  /* Place holder for missing/unknown type. */
       IVL_VT_REAL    = 2,
@@ -504,6 +525,10 @@ extern ivl_island_t ivl_branch_island(ivl_branch_t obj);
  * ivl_path_is_condit
  *    Is this a conditional structure? Needed for ifnone.
  *
+ * ivl_path_is_parallel
+ *    This returns true if the path is a parallel connection and
+ *    false if the path is a full connection.
+ *
  * ivl_path_source_posedge
  * ivl_path_source_negedge
  *    These functions return true if the source is edge sensitive.
@@ -514,6 +539,8 @@ extern uint64_t ivl_path_delay(ivl_delaypath_t obj, ivl_path_edge_t pt);
 extern ivl_nexus_t ivl_path_condit(ivl_delaypath_t obj);
 extern int ivl_path_is_condit(ivl_delaypath_t obj);
 
+extern int ivl_path_is_parallel(ivl_delaypath_t obj);
+
 extern int ivl_path_source_posedge(ivl_delaypath_t obj);
 extern int ivl_path_source_negedge(ivl_delaypath_t obj);
 
@@ -1239,8 +1266,10 @@ extern unsigned    ivl_lpm_lineno(ivl_lpm_t net);
  * width of a general power is the XXXX of the widths of the
  * inputs.
  *
- * Power may be signed. If so, the output should be sign extended
- * to fill in its result.
+ * Power may be signed. This indicates the type of the exponent. The
+ * base will always be treated as unsigned. The compiler must ensure
+ * the width of the base is equal to the width of the output to
+ * obtain the correct result when the base is really a signed value.
  *
  * - Part Select (IVL_LPM_PART_VP and IVL_LPM_PART_PV)
  * There are two part select devices, one that extracts a part from a
@@ -1285,8 +1314,8 @@ extern unsigned    ivl_lpm_lineno(ivl_lpm_t net);
  * magnitude compare, the signedness does matter. In any case, the
  * result of the compare is always unsigned.
  *
- * The EQX and EQZ nodes are windcard compares, where xz bits (EQX) or
- * z bits (EQZ) in the data(1) operand are treated as windcards. no
+ * The EQX and EQZ nodes are wildcard compares, where xz bits (EQX) or
+ * z bits (EQZ) in the data(1) operand are treated as wildcards. no
  * bits in the data(0) operand are wild. This matches the
  * SystemVerilog convention for the ==? operator.
  *
@@ -1303,8 +1332,13 @@ extern unsigned    ivl_lpm_lineno(ivl_lpm_t net);
  * inputs and the Q. All the types must be exactly the same.
  *
  * - D-FlipFlop (IVL_LPM_FF)
- * This data is an edge sensitive register. The ivl_lpm_q output and
- * single ivl_lpm_data input are the same with, ivl_lpm_width. This
+ * This device is an edge sensitive register. The ivl_lpm_q output and
+ * single ivl_lpm_data input are the same width, ivl_lpm_width. This
+ * device carries a vector like other LPM devices.
+ *
+ * - Latch (IVL_LPM_LATCH)
+ * This device is an asynchronous latch. The ivl_lpm_q output and
+ * single ivl_lpm_data input are the same width, ivl_lpm_width. This
  * device carries a vector like other LPM devices.
  *
  * - Memory port (IVL_LPM_RAM) (deprecated in favor of IVL_LPM_ARRAY)
@@ -1418,21 +1452,22 @@ extern ivl_signal_t ivl_lpm_array(ivl_lpm_t net);
   /* IVL_LPM_PART IVL_LPM_SUBSTITUTE */
 extern unsigned ivl_lpm_base(ivl_lpm_t net);
   /* IVL_LPM_FF */
+extern unsigned    ivl_lpm_negedge(ivl_lpm_t net);
 extern ivl_nexus_t ivl_lpm_clk(ivl_lpm_t net);
   /* IVL_LPM_UFUNC */
 extern ivl_scope_t  ivl_lpm_define(ivl_lpm_t net);
-  /* IVL_LPM_FF */
+  /* IVL_LPM_FF IVL_LPM_LATCH*/
 extern ivl_nexus_t ivl_lpm_enable(ivl_lpm_t net);
   /* IVL_LPM_ADD IVL_LPM_CONCAT IVL_LPM_FF IVL_LPM_PART IVL_LPM_MULT
      IVL_LPM_MUX IVL_LPM_POW IVL_LPM_SHIFTL IVL_LPM_SHIFTR IVL_LPM_SUB
-     IVL_LPM_UFUNC IVL_LPM_SUBSTITUTE */
+     IVL_LPM_UFUNC IVL_LPM_SUBSTITUTE IVL_LPM_LATCH */
 extern ivl_nexus_t ivl_lpm_data(ivl_lpm_t net, unsigned idx);
   /* IVL_LPM_ADD IVL_LPM_MULT IVL_LPM_POW IVL_LPM_SUB IVL_LPM_CMP_EQ
      IVL_LPM_CMP_EEQ IVL_LPM_CMP_EQX IVL_LPM_CMP_EQZ IVL_LPM_CMP_NEE */
 extern ivl_nexus_t ivl_lpm_datab(ivl_lpm_t net, unsigned idx);
   /* IVL_LPM_ADD IVL_LPM_FF IVL_LPM_MULT IVL_LPM_PART IVL_LPM_POW
      IVL_LPM_SUB IVL_LPM_UFUNC IVL_LPM_CMP_EEQ IVL_LPM_CMP_EQX
-     IVL_LPM_CMP_EQZ IVL_LPM_CMP_NEE IVL_LPM_SUBSTITUTE */
+     IVL_LPM_CMP_EQZ IVL_LPM_CMP_NEE IVL_LPM_SUBSTITUTE IVL_LPM_LATCH */
 extern ivl_nexus_t ivl_lpm_q(ivl_lpm_t net);
 extern ivl_drive_t ivl_lpm_drive0(ivl_lpm_t net);
 extern ivl_drive_t ivl_lpm_drive1(ivl_lpm_t net);
@@ -1738,6 +1773,13 @@ extern unsigned    ivl_parameter_lineno(ivl_parameter_t net);
  * ivl_scope_lineno
  *    Returns the instantiation file and line for this scope.
  *
+ * ivl_scope_func_type
+ * ivl_scope_func_signed
+ * ivl_scope_func_width
+ *
+ *    If the scope is a function, these function can be used to get
+ *    the type of the return value.
+ *
  * ivl_scope_is_auto
  *    Is the task or function declared to be automatic?
  *
@@ -1856,6 +1898,9 @@ extern const char*  ivl_scope_tname(ivl_scope_t net);
 extern int          ivl_scope_time_precision(ivl_scope_t net);
 extern int          ivl_scope_time_units(ivl_scope_t net);
 
+extern ivl_variable_type_t ivl_scope_func_type(ivl_scope_t net);
+extern int ivl_scope_func_signed(ivl_scope_t net);
+extern unsigned ivl_scope_func_width(ivl_scope_t net);
 
 /* SIGNALS
  * Signals are named things in the Verilog source, like wires and
@@ -2077,6 +2122,7 @@ extern unsigned ivl_stmt_lineno(ivl_statement_t net);
  *    handle disable statements.
  *
  * ivl_stmt_events
+ * ivl_stmt_needs_t0_trigger
  * ivl_stmt_nevent
  *    Statements that have event arguments (TRIGGER and WAIT) make
  *    those event objects available through these methods.
@@ -2191,6 +2237,8 @@ extern ivl_scope_t ivl_stmt_call(ivl_statement_t net);
 extern unsigned ivl_stmt_case_count(ivl_statement_t net);
   /* IVL_ST_CASE,IVL_ST_CASER,IVL_ST_CASEX,IVL_ST_CASEZ */
 extern ivl_expr_t ivl_stmt_case_expr(ivl_statement_t net, unsigned i);
+  /* IVL+ST_CASE,IVL_ST_CASER,IVL_ST_CASEX,IVL_ST_CASEZ */
+extern ivl_case_quality_t ivl_stmt_case_quality(ivl_statement_t net);
   /* IVL_ST_CASE,IVL_ST_CASER,IVL_ST_CASEX,IVL_ST_CASEZ */
 extern ivl_statement_t ivl_stmt_case_stmt(ivl_statement_t net, unsigned i);
   /* IVL_ST_CONDIT IVL_ST_CASE IVL_ST_REPEAT IVL_ST_WHILE */
@@ -2204,6 +2252,7 @@ extern ivl_expr_t ivl_stmt_delay_expr(ivl_statement_t net);
   /* IVL_ST_DELAY */
 extern uint64_t ivl_stmt_delay_val(ivl_statement_t net);
   /* IVL_ST_WAIT IVL_ST_TRIGGER */
+extern unsigned    ivl_stmt_needs_t0_trigger(ivl_statement_t net);
 extern unsigned    ivl_stmt_nevent(ivl_statement_t net);
 extern ivl_event_t ivl_stmt_events(ivl_statement_t net, unsigned idx);
   /* IVL_ST_CONTRIB */
@@ -2312,7 +2361,7 @@ extern const char* ivl_type_prop_name(ivl_type_t net, int idx);
 extern ivl_type_t  ivl_type_prop_type(ivl_type_t net, int idx);
 
 
-#if defined(__MINGW32__) || defined (__CYGWIN32__)
+#if defined(__MINGW32__) || defined (__CYGWIN__)
 #  define DLLEXPORT __declspec(dllexport)
 #else
 #  define DLLEXPORT
@@ -2342,4 +2391,6 @@ typedef const char* (*target_query_f) (const char*key);
 
 _END_DECL
 
+#undef ENUM_UNSIGNED_INT
+
 #endif /* IVL_ivl_target_H */

ivl_target_priv.h

@@ -1,7 +1,7 @@
 #ifndef IVL_ivl_target_priv_H
 #define IVL_ivl_target_priv_H
 /*
- * Copyright (c) 2008-2014 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 2008-2019 Stephen Williams (steve@icarus.com)
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -51,8 +51,6 @@ struct ivl_design_s {
       ivl_process_t threads_;
 
 	// Keep arrays of root scopes.
-      std::map<const NetScope*,ivl_scope_t> classes;
-      std::map<const NetScope*,ivl_scope_t> root_tasks;
       std::vector<ivl_scope_t> packages;
       std::vector<ivl_scope_t> roots;
 

ivlpp/Makefile.in

@@ -60,7 +60,7 @@ distclean: clean
 	rm -f Makefile config.log
 
 cppcheck: $(O:.o=.c)
-	cppcheck --enable=all -f $(INCLUDE_PATH) $^
+	cppcheck --enable=all --std=posix --std=c99 --std=c++03 -f $(INCLUDE_PATH) $^
 
 Makefile: $(srcdir)/Makefile.in ../config.status
 	cd ..; ./config.status --file=ivlpp/$@
@@ -71,9 +71,11 @@ ivlpp@EXEEXT@: $O
 lexor.c: $(srcdir)/lexor.lex
 	$(LEX) -t $< > $@
 
-install: all installdirs $(libdir)/ivl$(suffix)/ivlpp@EXEEXT@
+install: all installdirs installfiles
 
-$(libdir)/ivl$(suffix)/ivlpp@EXEEXT@: ivlpp@EXEEXT@
+F = ivlpp@EXEEXT@
+
+installfiles: $(F) | installdirs
 	$(INSTALL_PROGRAM) ./ivlpp@EXEEXT@ "$(DESTDIR)$(libdir)/ivl$(suffix)/ivlpp@EXEEXT@"
 
 installdirs: $(srcdir)/../mkinstalldirs

ivlpp/globals.h

@@ -1,7 +1,7 @@
 #ifndef IVL_globals_H
 #define IVL_globals_H
 /*
- * Copyright (c) 1999-2014 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 1999-2017 Stephen Williams (steve@icarus.com)
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -53,6 +53,9 @@ extern char dep_mode;
 
 extern int verbose_flag;
 
+extern int warn_redef;
+extern int warn_redef_all;
+
 /* This is the entry to the lexer. */
 extern int yylex(void);
 

ivlpp/ivlpp.txt

@@ -95,7 +95,7 @@ keys, with their corresponding values, are:
       This is exactly the same as the "-Dname=<value>" described above.
 
    I:<dir>
-      This is exctly the same as "-I<dir>".
+      This is exactly the same as "-I<dir>".
 
    relative include:<flag>
       The <flag> can be "true" or "false". This enables "relative

ivlpp/main.c

@@ -1,5 +1,5 @@
 const char COPYRIGHT[] =
-          "Copyright (c) 1999-2011 Stephen Williams ([email protected])";
+          "Copyright (c) 1999-2020 Stephen Williams ([email protected])";
 /*
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -98,6 +98,10 @@ int line_direct_flag = 0;
 unsigned error_count = 0;
 FILE *depend_file = NULL;
 
+/* Should we warn about macro redefinitions? */
+int warn_redef = 0;
+int warn_redef_all = 0;
+
 static int flist_read_flags(const char*path)
 {
       char line_buf[2048];
@@ -282,7 +286,7 @@ int main(int argc, char*argv[])
       include_dir[0] = 0;  /* 0 is reserved for the current files path. */
       include_dir[1] = strdup(".");
 
-      while ((opt=getopt(argc, argv, "F:f:K:Lo:p:P:vV")) != EOF) switch (opt) {
+      while ((opt=getopt(argc, argv, "F:f:K:Lo:p:P:vVW:")) != EOF) switch (opt) {
 
 	  case 'F':
 	    flist_read_flags(optarg);
@@ -336,6 +340,15 @@ int main(int argc, char*argv[])
 		break;
 	  }
 
+	  case 'W':
+	    if (strcmp(optarg, "redef-all") == 0) {
+		  warn_redef_all = 1;
+		  warn_redef = 1;
+	    } else if (strcmp(optarg, "redef-chg") == 0) {
+		  warn_redef = 1;
+	    }
+	    break;
+
 	  case 'v':
 	    fprintf(stderr, "Icarus Verilog Preprocessor version "
 		    VERSION " (" VERSION_TAG ")\n\n");
@@ -366,7 +379,10 @@ int main(int argc, char*argv[])
 		    "    -p<fil> - Write precompiled defines to <fil>\n"
 		    "    -P<fil> - Read precompiled defines from <fil>\n"
 		    "    -v      - Verbose\n"
-		    "    -V      - Print version information and quit\n",
+		    "    -V      - Print version information and quit\n"
+		    "    -W<cat> - Enable extra ivlpp warning category:\n"
+		    "               o redef-all - all macro redefinitions\n"
+		    "               o redef-chg - macro definition changes\n",
 		    argv[0]);
 	    return flag_errors;
       }

ivtest/.gitattributes

@@ -0,0 +1,5 @@
+# This test is sensitive to the number of bytes in the text file.
+ivltests/pr1819452.txt text eol=lf
+
+# MSY2 expected results require LF line endings.
+regression_report-msys2.txt text eol=lf

ivtest/.gitignore

@@ -0,0 +1,33 @@
+# Lines that start with '#' are comments.
+#
+# This file is for the development branch of Icarus Verilog.
+#
+# The following files will be ignored by git.
+
+# The log and work directories
+ivl_vhdl_work/
+log/
+work/
+vpi_log/
+vhdl/
+
+# The normal regression output files.
+
+regression_report.txt
+vhdl_regression_report.txt
+
+# These should be cleaned up, but ignore them as well.
+*~
+*.o
+*.vpi
+*.tmp
+src/vcddiff
+vsim
+vlog95.v
+tmp_blif.blif
+tmp_blif.v
+tmp_blif.vvp
+
+# Some tests do not work out of the work directory, so
+# ignore these files that they leave in the home directory.
+dump.vcd

ivtest/COPYING

@@ -0,0 +1,339 @@
+		    GNU GENERAL PUBLIC LICENSE
+		       Version 2, June 1991
+
+ Copyright (C) 1989, 1991 Free Software Foundation, Inc.
+ 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+			    Preamble
+
+  The licenses for most software are designed to take away your
+freedom to share and change it.  By contrast, the GNU General Public
+License is intended to guarantee your freedom to share and change free
+software--to make sure the software is free for all its users.  This
+General Public License applies to most of the Free Software
+Foundation's software and to any other program whose authors commit to
+using it.  (Some other Free Software Foundation software is covered by
+the GNU Library General Public License instead.)  You can apply it to
+your programs, too.
+
+  When we speak of free software, we are referring to freedom, not
+price.  Our General Public Licenses are designed to make sure that you
+have the freedom to distribute copies of free software (and charge for
+this service if you wish), that you receive source code or can get it
+if you want it, that you can change the software or use pieces of it
+in new free programs; and that you know you can do these things.
+
+  To protect your rights, we need to make restrictions that forbid
+anyone to deny you these rights or to ask you to surrender the rights.
+These restrictions translate to certain responsibilities for you if you
+distribute copies of the software, or if you modify it.
+
+  For example, if you distribute copies of such a program, whether
+gratis or for a fee, you must give the recipients all the rights that
+you have.  You must make sure that they, too, receive or can get the
+source code.  And you must show them these terms so they know their
+rights.
+
+  We protect your rights with two steps: (1) copyright the software, and
+(2) offer you this license which gives you legal permission to copy,
+distribute and/or modify the software.
+
+  Also, for each author's protection and ours, we want to make certain
+that everyone understands that there is no warranty for this free
+software.  If the software is modified by someone else and passed on, we
+want its recipients to know that what they have is not the original, so
+that any problems introduced by others will not reflect on the original
+authors' reputations.
+
+  Finally, any free program is threatened constantly by software
+patents.  We wish to avoid the danger that redistributors of a free
+program will individually obtain patent licenses, in effect making the
+program proprietary.  To prevent this, we have made it clear that any
+patent must be licensed for everyone's free use or not licensed at all.
+
+  The precise terms and conditions for copying, distribution and
+modification follow.
+
+		    GNU GENERAL PUBLIC LICENSE
+   TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
+
+  0. This License applies to any program or other work which contains
+a notice placed by the copyright holder saying it may be distributed
+under the terms of this General Public License.  The "Program", below,
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+
+Activities other than copying, distribution and modification are not
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+running the Program is not restricted, and the output from the Program
+is covered only if its contents constitute a work based on the
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+Whether that is true depends on what the Program does.
+
+  1. You may copy and distribute verbatim copies of the Program's
+source code as you receive it, in any medium, provided that you
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+copyright notice and disclaimer of warranty; keep intact all the
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+along with the Program.
+
+You may charge a fee for the physical act of transferring a copy, and
+you may at your option offer warranty protection in exchange for a fee.
+
+  2. You may modify your copy or copies of the Program or any portion
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+distribute such modifications or work under the terms of Section 1
+above, provided that you also meet all of these conditions:
+
+    a) You must cause the modified files to carry prominent notices
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+
+    b) You must cause any work that you distribute or publish, that in
+    whole or in part contains or is derived from the Program or any
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+
+    c) If the modified program normally reads commands interactively
+    when run, you must cause it, when started running for such
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+    notice that there is no warranty (or else, saying that you provide
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+    the Program is not required to print an announcement.)
+
+These requirements apply to the modified work as a whole.  If
+identifiable sections of that work are not derived from the Program,
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+
+  3. You may copy and distribute the Program (or a work based on it,
+under Section 2) in object code or executable form under the terms of
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+    a) Accompany it with the complete corresponding machine-readable
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+    allowed only for noncommercial distribution and only if you
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+The source code for a work means the preferred form of the work for
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+distribution of the source code, even though third parties are not
+compelled to copy the source along with the object code.
+
+  4. You may not copy, modify, sublicense, or distribute the Program
+except as expressly provided under this License.  Any attempt
+otherwise to copy, modify, sublicense or distribute the Program is
+void, and will automatically terminate your rights under this License.
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+this License will not have their licenses terminated so long as such
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+
+  5. You are not required to accept this License, since you have not
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+prohibited by law if you do not accept this License.  Therefore, by
+modifying or distributing the Program (or any work based on the
+Program), you indicate your acceptance of this License to do so, and
+all its terms and conditions for copying, distributing or modifying
+the Program or works based on it.
+
+  6. Each time you redistribute the Program (or any work based on the
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+infringement or for any other reason (not limited to patent issues),
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+license would not permit royalty-free redistribution of the Program by
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+the only way you could satisfy both it and this License would be to
+refrain entirely from distribution of the Program.
+
+If any portion of this section is held invalid or unenforceable under
+any particular circumstance, the balance of the section is intended to
+apply and the section as a whole is intended to apply in other
+circumstances.
+
+It is not the purpose of this section to induce you to infringe any
+patents or other property right claims or to contest validity of any
+such claims; this section has the sole purpose of protecting the
+integrity of the free software distribution system, which is
+implemented by public license practices.  Many people have made
+generous contributions to the wide range of software distributed
+through that system in reliance on consistent application of that
+system; it is up to the author/donor to decide if he or she is willing
+to distribute software through any other system and a licensee cannot
+impose that choice.
+
+This section is intended to make thoroughly clear what is believed to
+be a consequence of the rest of this License.
+
+  8. If the distribution and/or use of the Program is restricted in
+certain countries either by patents or by copyrighted interfaces, the
+original copyright holder who places the Program under this License
+may add an explicit geographical distribution limitation excluding
+those countries, so that distribution is permitted only in or among
+countries not thus excluded.  In such case, this License incorporates
+the limitation as if written in the body of this License.
+
+  9. The Free Software Foundation may publish revised and/or new versions
+of the General Public License from time to time.  Such new versions will
+be similar in spirit to the present version, but may differ in detail to
+address new problems or concerns.
+
+Each version is given a distinguishing version number.  If the Program
+specifies a version number of this License which applies to it and "any
+later version", you have the option of following the terms and conditions
+either of that version or of any later version published by the Free
+Software Foundation.  If the Program does not specify a version number of
+this License, you may choose any version ever published by the Free Software
+Foundation.
+
+  10. If you wish to incorporate parts of the Program into other free
+programs whose distribution conditions are different, write to the author
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+
+			    NO WARRANTY
+
+  11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
+FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW.  EXCEPT WHEN
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+YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER
+PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGES.
+
+		     END OF TERMS AND CONDITIONS
+
+	Appendix: How to Apply These Terms to Your New Programs
+
+  If you develop a new program, and you want it to be of the greatest
+possible use to the public, the best way to achieve this is to make it
+free software which everyone can redistribute and change under these terms.
+
+  To do so, attach the following notices to the program.  It is safest
+to attach them to the start of each source file to most effectively
+convey the exclusion of warranty; and each file should have at least
+the "copyright" line and a pointer to where the full notice is found.
+
+    <one line to give the program's name and a brief idea of what it does.>
+    Copyright (C) 19yy  <name of author>
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+
+Also add information on how to contact you by electronic and paper mail.
+
+If the program is interactive, make it output a short notice like this
+when it starts in an interactive mode:
+
+    Gnomovision version 69, Copyright (C) 19yy name of author
+    Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+    This is free software, and you are welcome to redistribute it
+    under certain conditions; type `show c' for details.
+
+The hypothetical commands `show w' and `show c' should show the appropriate
+parts of the General Public License.  Of course, the commands you use may
+be called something other than `show w' and `show c'; they could even be
+mouse-clicks or menu items--whatever suits your program.
+
+You should also get your employer (if you work as a programmer) or your
+school, if any, to sign a "copyright disclaimer" for the program, if
+necessary.  Here is a sample; alter the names:
+
+  Yoyodyne, Inc., hereby disclaims all copyright interest in the program
+  `Gnomovision' (which makes passes at compilers) written by James Hacker.
+
+  <signature of Ty Coon>, 1 April 1989
+  Ty Coon, President of Vice
+
+This General Public License does not permit incorporating your program into
+proprietary programs.  If your program is a subroutine library, you may
+consider it more useful to permit linking proprietary applications with the
+library.  If this is what you want to do, use the GNU Library General
+Public License instead of this License.

ivtest/README

@@ -0,0 +1,120 @@
+####################
+#
+# Main test script
+#
+####################
+
+There are a group of tests that are meant to exercise the compiler
+and the run time. To run them just type:
+
+./regress
+
+or
+
+perl vvp_reg.pl
+
+or if perl is located in /usr/bin
+
+./vvp_reg.pl
+
+The output from these tests are displayed on the screen
+and are also placed in the regression_report.txt file.
+The expected output for the current development release
+is located in the regression_report-devel.txt file. The
+expected output for stable (released) versions can be
+found in files named regression_report-v<version>.txt.
+
+The results from individual tests can be found in the
+log directory and gold files, when needed, are in the
+gold directory. The source files can be found in the
+ivltests and contrib directories. The list of tests
+and how they are run are in the regress-*.list files.
+
+To check a specific suffixed version of Icarus Verilog
+use the --suffix=<suffix> flag to tell the script which
+version to run e.g.(--suffix=-10 will test iverilog-10,
+etc.). You can also run the test with valgrind (very very
+slow) by giving the script the --with-valgrind flag.
+
+
+####################
+#
+# VPI test script
+#
+####################
+
+To test the VPI interface type:
+
+perl vpi_reg.pl
+
+or if perl is located in /usr/bin
+
+./vpi_reg.pl
+
+All these tests should pass for V11.devel. There are
+some expected failures for V10, which are flagged as
+Not Implemented
+
+The individual test results are found in the vpi_log
+directory and the gold files are in the vpi_gold
+directory. The source files are in the vpi directory.
+The vpi_regress.list file has the tests to perform.
+
+This script also takes the --suffix=<suffix> and the
+--with-valgrind flags described above.
+
+
+####################
+#
+# VHDL test script
+#
+####################
+
+** Note this is no longer maintained **
+
+This test script require that ghdl be installed in your
+path and is used to test the Verilog to VHDL translation.
+
+perl vhdl_reg.pl
+
+or if perl is located in /usr/bin
+
+./vhdl_reg.pl
+
+The expected output for V0.10.devel and V0.9 is located
+in the vhdl_regression_report-devel.txt file. V0.8 does
+not support converting Verilog to VHDL.
+
+This script also takes the --suffix=<suffix> and the
+--with-valgrind flags described above.
+
+
+####################
+#
+# BLIF test script
+#
+####################
+
+This test script require that abc be installed in your
+path and is used to test the Verilog to VHDL translation.
+
+python blif_reg.py
+
+There is no expected output as of yet so to check for
+regressions simply run with and without your patches.
+
+
+####################
+#
+# Windows (MinGW) test issues
+#
+####################
+
+When running under Windows using a MinGW build in a MSYS2
+shell, the expected output from vvp_reg.pl can be found in
+regression_report-msys2.txt. The MinGW/MSYS2 specific test
+exceptions can be found in regress-msys2.list. Exceptions
+for the VPI tests can be found in the vpi_regress.list file.
+
+With Windows 10 and MSYS2, there are now very few differences
+between the Windows and Linux builds.

ivtest/blif.list

@@ -0,0 +1,21 @@
+blif01a
+blif01b
+blif01c
+blif01d
+blif01e
+blif01f
+blif01g
+blif01h
+blif01i
+blif02a
+blif02b
+blif02c
+blif02d
+blif02e
+blif02f
+blif02g
+blif02h
+blif02i
+blif02j
+blif02k
+blif_shift

ivtest/blif/blif01a.v

@@ -0,0 +1,66 @@
+
+/*
+ * Generate a combinational adder of any width. The width parameter can
+ * be any integer value >0. The A and B inputs have WID bits, and the Q
+ * output has WID+1 bits to include the overflow.
+ */
+module addN
+  #(parameter WID = 4)
+   (input wire [WID-1:0] A,
+    input wire [WID-1:0] B,
+    output wire [WID:0]  Q
+    /* */);
+
+   wire [WID-1:0]	Cout;
+
+   /* The least significant slice has no Cin */
+   add1 U0 (.A(A[0]), .B(B[0]), .Cin(1'b0), .Q(Q[0]), .Cout(Cout[0]));
+
+   /* Generate all the remaining slices */
+   genvar i;
+   for (i = 1 ; i < WID ; i = i+1) begin : U
+      add1 Un (.A(A[i]), .B(B[i]), .Cin(Cout[i-1]), .Q(Q[i]), .Cout(Cout[i]));
+   end
+
+   assign Q[WID] = Cout[WID-1];
+
+endmodule // add
+
+/*
+ * This is a single-bit combinational adder used by the addH module
+ * above.
+ */
+module add1(input A, input B, input Cin, output Q, output Cout);
+
+   assign Q = A ^ B ^ Cin;
+   assign Cout = A&B | A&Cin | B&Cin;
+
+endmodule // hadd
+
+`ifdef TEST_BENCH
+module main;
+
+   parameter WID = 4;
+   reg [WID-1:0] A, B;
+   wire [WID:0]  Q;
+
+   addN #(.WID(WID)) usum (.A(A), .B(B), .Q(Q));
+
+   int		 adx;
+   int		 bdx;
+   initial begin
+      for (bdx = 0 ; bdx[WID]==0 ; bdx = bdx+1) begin
+	 for (adx = 0 ; adx[WID]==0 ; adx = adx+1) begin
+	    A <= adx[WID-1:0];
+	    B <= bdx[WID-1:0];
+	    #1 if (Q !== (adx+bdx)) begin
+	       $display("FAILED -- A=%b, B=%b, Q=%b", A, B, Q);
+	       $finish;
+	    end
+	 end
+      end
+      $display("PASSED");
+   end
+
+endmodule // main
+`endif

ivtest/blif/blif01a_tb.v

@@ -0,0 +1,40 @@
+
+/*
+ * This is a post-wynthesis test for the blif01a.v test. Run this
+ * simulation in these steps:
+ *
+ *   $ iverilog -tblif -o foo.blif blif01a.v
+ *   $ abc
+ *   abc 01> read_blif foo.blif
+ *   abc 02> write_verilog foo.v
+ *   abc 03> quit
+ *   $ iverilog -g2009 -o foo.vvp blif02a_tb.v foo.v
+ *   $ vvp foo.vvp
+ */
+module main;
+
+   parameter WID = 4;
+   reg [WID-1:0] A, B;
+   wire [WID:0]  Q;
+
+   addN usum(.\A[3] (A[3]), .\A[2] (A[2]), .\A[1] (A[1]), .\A[0] (A[0]),
+	     .\B[3] (B[3]), .\B[2] (B[2]), .\B[1] (B[1]), .\B[0] (B[0]),
+	     .\Q[4] (Q[4]), .\Q[3] (Q[3]), .\Q[2] (Q[2]), .\Q[1] (Q[1]), .\Q[0] (Q[0]));
+
+   int		 adx;
+   int		 bdx;
+   initial begin
+      for (bdx = 0 ; bdx[WID]==0 ; bdx = bdx+1) begin
+	 for (adx = 0 ; adx[WID]==0 ; adx = adx+1) begin
+	    A <= adx[WID-1:0];
+	    B <= bdx[WID-1:0];
+	    #1 if (Q !== (adx+bdx)) begin
+	       $display("FAILED -- A=%b, B=%b, Q=%b", A, B, Q);
+	       $finish;
+	    end
+	 end
+      end
+      $display("PASSED");
+   end
+
+endmodule // main

ivtest/blif/blif01b.v

@@ -0,0 +1,9 @@
+
+module test_logic(input A, B, output q_nand, q_nor, q_xnor, q_not);
+
+   assign q_nand = A ~& B;
+   assign q_nor  = A ~| B;
+   assign q_xnor = A ~^ B;
+   assign q_not  = ~A;
+
+endmodule // test_logic

ivtest/blif/blif01b_tb.v

@@ -0,0 +1,34 @@
+
+module main;
+
+   reg [2:0] X;
+   wire      q_nand, q_nor, q_xnor, q_not;
+
+   test_logic DUT(.A(X[0]), .B(X[1]), .q_nand(q_nand), .q_nor(q_nor),
+		  .q_xnor(q_xnor), .q_not(q_not));
+
+   initial begin
+      for (X = 0 ; X < 4 ; X = X+1) begin
+	 #1 /* Let gates settle. */;
+	 if (q_nand !== (X[0] ~& X[1])) begin
+	    $display("FAILED -- q_nand=%b, X=%b", q_nand, X[1:0]);
+	    $finish;
+	 end
+	 if (q_nor !== (X[0] ~| X[1])) begin
+	    $display("FAILED -- q_nor=%b, X=%b", q_nor, X[1:0]);
+	    $finish;
+	 end
+	 if (q_xnor !== (X[0] ~^ X[1])) begin
+	    $display("FAILED -- q_xnor=%b, X=%b", q_xnor, X[1:0]);
+	    $finish;
+	 end
+	 if (q_not !== (~X[0])) begin
+	    $display("FAILED -- q_not=%b, X=%b", q_not, X[0]);
+	    $finish;
+	 end
+
+      end
+      $display("PASSED");
+   end
+
+endmodule // main

ivtest/blif/blif01c.v

@@ -0,0 +1,11 @@
+
+module addN
+  #(parameter WID = 4)
+   (input wire [WID-1:0] A,
+    input wire [WID-1:0] B,
+    output wire [WID:0]  Q
+    /* */);
+
+   assign Q = A + B;
+
+endmodule // add

ivtest/blif/blif01c_tb.v

@@ -0,0 +1,40 @@
+
+/*
+ * This is a post-wynthesis test for the blif01a.v test. Run this
+ * simulation in these steps:
+ *
+ *   $ iverilog -tblif -o foo.blif blif01a.v
+ *   $ abc
+ *   abc 01> read_blif foo.blif
+ *   abc 02> write_verilog foo.v
+ *   abc 03> quit
+ *   $ iverilog -g2009 -o foo.vvp blif02a_tb.v foo.v
+ *   $ vvp foo.vvp
+ */
+module main;
+
+   parameter WID = 4;
+   reg [WID-1:0] A, B;
+   wire [WID:0]  Q;
+
+   addN usum(.\A[3] (A[3]), .\A[2] (A[2]), .\A[1] (A[1]), .\A[0] (A[0]),
+	     .\B[3] (B[3]), .\B[2] (B[2]), .\B[1] (B[1]), .\B[0] (B[0]),
+	     .\Q[4] (Q[4]), .\Q[3] (Q[3]), .\Q[2] (Q[2]), .\Q[1] (Q[1]), .\Q[0] (Q[0]));
+
+   int		 adx;
+   int		 bdx;
+   initial begin
+      for (bdx = 0 ; bdx[WID]==0 ; bdx = bdx+1) begin
+	 for (adx = 0 ; adx[WID]==0 ; adx = adx+1) begin
+	    A <= adx[WID-1:0];
+	    B <= bdx[WID-1:0];
+	    #1 if (Q !== (adx+bdx)) begin
+	       $display("FAILED -- A=%b, B=%b, Q=%b", A, B, Q);
+	       $finish;
+	    end
+	 end
+      end
+      $display("PASSED");
+   end
+
+endmodule // main

ivtest/blif/blif01d.v

@@ -0,0 +1,11 @@
+
+module subN
+  #(parameter WID = 4)
+   (input wire [WID-1:0] A,
+    input wire [WID-1:0] B,
+    output wire [WID:0]  Q
+    /* */);
+
+   assign Q = A - B;
+
+endmodule // add