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OpenRAM
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3672 Commits

Author SHA1 Message Date
Jacob Walker 0b056dca54 fixed rom bank test name 2023-03-30 18:44:55 -07:00
Jacob Walker 52791a2719 a space 2023-03-30 11:30:50 -07:00
Jacob Walker c1fb3cab6c 1kb rom DRC clean 2023-03-30 11:30:50 -07:00
Jacob Walker 7805fcb21e more top level routing cleanup 2023-03-30 11:30:50 -07:00
Jacob Walker fef9902c45 rom base passing tests with top level routing 2023-03-30 11:30:50 -07:00
mrg 7c453e80be Simplify ROM test. 2023-03-30 11:30:50 -07:00
mrg af0a6d32fb Remove old skip tests 2023-03-30 11:30:50 -07:00
mrg 2075d244cb Change ROM test permissions to include x 2023-03-30 11:30:50 -07:00
Jacob Walker 4c34a54d32 top level boundary fixes 2023-03-30 11:30:50 -07:00
Jacob Walker 7fe5ed5c41 edge routing 2023-03-30 11:30:50 -07:00
Jacob Walker 09f9c4cc20 some rom bank cleanup 2023-03-30 11:30:50 -07:00
mrg 56e14113aa Change rom_base_bank name and top pin names 2023-03-30 11:30:50 -07:00
mrg d2b5be0130 Add exclude tests for ROMs 2023-03-30 11:30:50 -07:00
mrg fe65a20431 Rename ROM unit tests. 2023-03-30 11:30:50 -07:00
Jacob Walker eec0f02bb8 skip test file 2023-03-30 11:30:50 -07:00
Jacob Walker b50ec272da updated top level rom unit tests 2023-03-30 11:30:50 -07:00
Jacob Walker 41f0b9a412 rom compiler top level 2023-03-30 11:30:50 -07:00
Jacob Walker 2d5199961d revert changes to pinvbuf 2023-03-30 11:30:50 -07:00
Jacob Walker 382c91f342 precharge array test passing sky130 2023-03-30 11:30:50 -07:00
Jacob Walker 92251fe61e more code cleaning 2023-03-30 11:30:50 -07:00
Jacob Walker 90cf382a43 removed hardcoded DRC rule 2023-03-30 11:30:50 -07:00
Jacob Walker 0cb4459b4b changed ROM test data path 2023-03-30 11:30:50 -07:00
Jacob Walker af0209ec96 passing code style 2023-03-30 11:30:50 -07:00
Jacob Walker 79efff9ca6 code cleanup and updated copyright 2023-03-30 11:30:50 -07:00
Jacob Walker bbf2cd2913 Changes for test generation and simulation 2023-03-30 11:30:50 -07:00
Jacob Walker 89c7d50bd1 added row of nmos to end of array for precharge 2023-03-30 11:30:50 -07:00
SWalker f847721500 changes to control logic, invert polarity of precharge 2023-03-30 11:30:50 -07:00
SWalker 9cefe5da7c added unrouted output buffers 2023-03-30 11:30:50 -07:00
SWalker 764601a721 added binning to precharge pmos 2023-03-30 11:30:50 -07:00
Jesse Cirimelli-Low 6981cfa58b add example of writing out simulation netlist 2023-03-30 11:30:50 -07:00
Jacob Walker 736bd51fe1 add top level pins for sim 2023-03-30 11:30:50 -07:00
Jacob Walker 81bf2d7ae7 fixed decode lvs 2023-03-30 11:30:50 -07:00
Jacob Walker 16df8e0e43 fixing decoder lvs 2023-03-30 11:30:50 -07:00
Jacob Walker 559300e5cc taps in main array and decoder 2023-03-30 11:30:50 -07:00
Jacob Walker f7aed247fd column control and address precharge 2023-03-30 11:30:50 -07:00
Jacob Walker ce8197d206 pitch match decoder and array 2023-03-30 11:30:50 -07:00
Jacob Walker e697efa5f6 fixed base array lvs 2023-03-30 11:30:50 -07:00
Jacob Walker b2631b60ff updated imports to match upstream dev openram 2023-03-30 11:30:50 -07:00
Jacob Walker 63925bd48e Decoder array and start of rom bank 2023-03-30 11:30:50 -07:00
Jacob Walker bc8d564dbf array with poly straps passing drc/lvs 2023-03-30 11:30:50 -07:00
Jacob Walker aea3c0ad01 passing drc/lvs on 4x4 rom array 2023-03-30 11:30:50 -07:00
Jacob Walker a3e271f6fb reoriented cell and added tap cell 2023-03-30 11:30:50 -07:00
Jacob Walker 7309af7e29 base and dummy array alignment in sky130 2023-03-30 11:30:50 -07:00
Jacob Walker d7ac26a053 array generation and bitline routing with array module 2023-03-30 11:30:50 -07:00
Jacob Walker 4db5c3be26 basic nmos array, for nand rom 2023-03-30 11:30:50 -07:00
Sam Crow 299512eba2 standardize array tests 2023-03-22 18:56:52 -07:00
Eren Dogan 6eebef8c72 Fix typo in Makefile 2023-03-16 14:40:24 -07:00
mrg 8ea100b52e Split pbitcell tests to fix factory.reset() bug. 2023-03-14 08:50:00 -07:00
Eren Dogan 16490e9928 Merge branch 'conda' into dev 2023-03-13 16:10:35 -07:00
Eren Dogan 650b6e513c Remove the hack used for unit tests running on docker 2023-03-10 16:35:22 -08:00
mrg c9bf3c1261 Remove factory.reset from all unit tests as we no longer use regress.py. 2023-03-10 10:44:54 -08:00
Sam Crow e20f28580f support no rbls in local array 2023-03-09 14:44:05 -08:00
Sam Crow 710f0fbae5 update local/global tests for no rbls 2023-03-09 14:37:07 -08:00
Sam Crow 41344a980b change array modules to allow rbl=[0, 0] 2023-03-09 10:23:28 -08:00
Sam Crow 7abaf0463e create no rbl no dummy tests 2023-03-09 10:05:17 -08:00
mrg 5c173551ec Remove regress.py and skip_tests for Makefile option instead. 2023-03-02 12:44:52 -08:00
mrg 1f3bdd598a Add scn4m_subm global array test to skip test until issue is fixed. 2023-03-01 14:23:31 -08:00
mrg 49dbbb33bc Add skip tests until inverters added to sense amps. 2023-03-01 14:15:07 -08:00
mrg 58f1b55e08 Over-ride build_graph in row/col caps to remove incorrect graph error. 2023-03-01 09:25:56 -08:00
samuelkcrow e90964fbda update copyright 2023-02-21 14:04:31 -08:00
samuelkcrow ad4b4f66dc use capped array to create banks 2023-02-21 09:58:46 -08:00
samuelkcrow 3a8e29ce77 Merge remote-tracking branch 'origin/dev' into no_rbl 2023-02-20 22:11:02 -08:00
samuelkcrow 52dcd81a08 use left_rbl instead of rbl to calculate replica column mirroring (column offset) 2023-02-20 17:28:24 -08:00
Eren Dogan b37711e643 Merge branch 'dev' into deploy_pip 2023-02-20 14:08:20 -08:00
mrg c07268d297 Disable power routing on some freepdk45 tests for issue 36 2023-02-17 17:00:04 -08:00
Eren Dogan d8a169e79f Reenable tests 2023-02-17 14:56:52 -08:00
Eren Dogan d3da632dc1 Fix typo in model delay test 2023-02-17 13:34:02 -08:00
Eren Dogan a7582c05dc Disable failing tests 2023-02-17 10:42:31 -08:00
samuelkcrow 51a7161cd7 fix mirroring of cap cells in cap rows 2023-02-14 10:59:00 -08:00
samuelkcrow 2565305158 fix positional getters 2023-02-13 18:45:21 -08:00
samuelkcrow 8d6d8f2f8c revert variable names to those inherited from bitcell base array 2023-02-13 18:45:21 -08:00
Eren Dogan 78e84ee8df Add version file 2023-02-07 10:30:48 -08:00
samuelkcrow 2948b08e66 copy rbl default values logic from lower array modules 2023-02-06 20:04:54 -08:00
samuelkcrow 796b1913cf fix typo in wordline var 2023-02-06 20:01:49 -08:00
samuelkcrow c256a5eb44 fix coppied functions from replica array to work correctly in capped array 2023-02-06 19:57:42 -08:00
samuelkcrow 4a22c5c56f add instance offset to capped array offset getters 2023-02-06 19:40:37 -08:00
samuelkcrow 92a9a1729e untested update to get_cell_name function used by characterizer 2023-02-06 19:19:02 -08:00
samuelkcrow 3dac89d041 fixing named variables passed between array modules 2023-02-04 21:06:41 -08:00
Eren Dogan dce324fc94 Fix newline for scripts 2023-01-28 22:59:08 -08:00
Eren Dogan e5fc25da6f Update copyright year 2023-01-28 22:56:27 -08:00
samuelkcrow 2f795f8068 fix height calculation bug for replica array 2023-01-26 17:38:24 -08:00
samuelkcrow cc408447b1 standardize names and content of tests in the 14_* group 2023-01-26 14:14:25 -08:00
samuelkcrow 03adf94b6a fix offsets to match original replica array, and make array translation statically sized 2023-01-26 12:31:14 -08:00
samuelkcrow 8fc93bc91a point local array to new capped array module 2023-01-24 11:09:57 -08:00
samuelkcrow ebe163c57e fix placement bug for cap cells including wrong height from replica array 2023-01-24 11:07:52 -08:00
Eren Dogan c613693399 Don't use Docker for unit tests 2023-01-22 18:19:56 -08:00
Eren Dogan efba4d785e Fix other commands to use conda as well 2023-01-22 18:15:38 -08:00
Eren Dogan 0c08d5da5f Search for tools in conda first 2023-01-22 18:14:48 -08:00
Eren Dogan ca03da8d95 Use conda to install the tools needed 2023-01-20 15:34:45 -08:00
samuelkcrow 5573c6b241 fix pin shape issue 2023-01-18 22:44:32 -08:00
samuelkcrow d460eacfcc standardize rbl arguments interface 2023-01-18 22:43:37 -08:00
samuelkcrow 78c4ba5fc0 clean up comments 2023-01-18 21:01:30 -08:00
samuelkcrow 7021b80506 remove unused side argument from side routing functions 2023-01-18 20:36:36 -08:00
samuelkcrow 8522f32e43 radically simplify unused wordline routing code... bit of a facepalm tbh 2023-01-18 20:32:40 -08:00
samuelkcrow 78cabf9ca3 make capped array name more descriptive and add x mode to tests 2023-01-17 10:20:16 -08:00
samuelkcrow b5cddb9394 fix remaining lvs issues by adding an offset to pins gotten from subinstances and appropriately grounding wls in cap cells 2023-01-16 17:54:17 -08:00
samuelkcrow 29c79abaf8 move layout pins when copying them 2023-01-15 20:33:38 -08:00
samuelkcrow d8e0f4275d fix capped array after merge with dev 2022-12-14 14:20:54 -08:00
samuelkcrow f651b484c5 fix capped array tests after dev merge 2022-12-14 08:48:12 -08:00
samuelkcrow 6a8a76dd23 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into no_rbl 2022-12-14 08:13:08 -08:00