38de6ebf3a
Compress support function definitions a bit
2008-07-19 21:04:52 +01:00
af3ee49f57
Refactor support function code a bit
2008-07-19 20:49:55 +01:00
0cb6ea34d7
Move type conversion code into a separate file
2008-07-19 15:23:47 +01:00
b6df73d3b9
Support functions for converting (un)signed -> boolean
2008-07-19 15:15:16 +01:00
2d79e1a2e0
Store the currently active entity
2008-07-19 14:45:00 +01:00
7b311b6adb
Translate internal delays in assignments
2008-07-18 14:47:35 +01:00
df4a380e42
Fix implementation of IVL_LPM_UFUNC
...
Function name was not correct.
2008-07-18 14:31:12 +01:00
6ff80e80a4
Catch case where (un)signed is converted to boolean
2008-07-18 12:30:24 +01:00
8b6b111541
Add IVL_LPM_CMP_EQ
2008-07-18 11:58:26 +01:00
fd8f01e317
Add IVL_LPM_CMP_GE
2008-07-18 11:56:00 +01:00
00317dd47f
Dummy implementation of $time
2008-07-18 11:50:05 +01:00
e9637f6d11
Generate synthesisable code for sequential processes
...
Whilst adding `wait until ...' at the end of every
process is a valid translation of the input, it is not
actually synthesisable in at least one commercial
synthesiser (XST). According to the XST manual the
correct template is to use `wait until ...' at the
start of sequential processes and `wait on ...'
(equivalent to `wait until ...' with 'Event on all
the signals) at the end of combinatorial processes.
This patch implements that.
2008-07-17 17:36:42 +01:00
1f9ed2c5ec
VHDL AST element for `wait on' statement
2008-07-17 17:23:21 +01:00
7677b59650
Make sure offset of IVL_LPM_ARRAY is integer
2008-07-17 16:41:34 +01:00
9cf4792d53
Translate array references in expressions
2008-07-17 14:47:10 +01:00
4d9f029000
Generate correct array bounds
2008-07-17 14:38:07 +01:00
9916686c24
Convert constant bits to integers
2008-07-17 14:29:56 +01:00
c86377790f
Automatically convert constant bit strings to integers
2008-07-17 14:26:35 +01:00
2a791bfb38
Assignment to arrays
2008-07-17 13:41:44 +01:00
1d3ac6bc1f
Generate VHDL array type declarations of Verilog arrays
2008-07-17 13:08:55 +01:00
3fa5a04947
Merge branch 'vhdl' into array
2008-07-17 12:01:09 +01:00
7c5b0f737c
Class for VHDL type declarations
2008-07-17 11:59:02 +01:00
c116808fdb
Remove duplicated code
2008-07-17 11:46:36 +01:00
553f3d77a9
Code for VHDL array type
2008-07-17 11:43:59 +01:00
642fbe9fc5
Correct check for arrays
2008-07-17 11:31:06 +01:00
395a2248d8
Make sure 1-bit constants are std_logic not (un)signed
2008-07-16 16:52:15 +01:00
be67cae29f
Add translation for IVL_ST_CASEX
2008-07-16 16:42:44 +01:00
f62a00bedb
Fix LPM binop with different signedness
...
Need to explicitly cast between signed/unsigned to
make sure both arguments have the same type or the
VHDL won't compile.
2008-07-16 16:20:08 +01:00
646a6056a2
Add IVL_LPM_CMP_EEQ support
2008-07-16 12:50:55 +01:00
4504c2bceb
Fix initialisation order bug with `if' statements
...
If an assignment appears inside an if statement branch
it could be incorrectly used as the signal's initial
value.
2008-07-16 12:11:00 +01:00
d343db34fd
Fix initialisation order
...
Initial processes set a magic flag in the code generator
which allows it to push constant assignments into the
VHDL signal initialisation and omit the assignment.
However, it should only do this if the signal has not
already been read (otherwise the previous read would
not get the undefined value as expected)
2008-07-16 12:00:11 +01:00
b5e12077b2
Fix assignment to lval slice
...
It was broken in yeserday's refactoring
2008-07-15 18:40:30 +01:00
f3753ea9ad
Add warning that arrays are not yet implemented
2008-07-15 18:09:18 +01:00
45e289d32d
Implement IVL_LPM_SHIFTL/R
2008-07-15 18:01:37 +01:00
40cabff44f
Leave blank line at end of function
2008-07-15 16:30:50 +01:00
a9c98ad5f2
Handle `if' with empty cond_true part
...
Fixes assertion failure with following statement:
if (foo)
begin
end
else
...
2008-07-15 14:26:19 +01:00
b8e758edf0
Refactor LPM code
2008-07-15 14:09:24 +01:00
0b48f69b4e
Tidy up blocking assignment code
2008-07-15 10:44:48 +01:00
d1e7e325b7
Remove redundant edge_detector function
2008-07-14 21:34:48 +01:00
75b1db0add
Fix assignment with ternary RHS
...
This was also broken in the last commit
2008-07-14 21:27:21 +01:00
6e965523a1
Fix PV assignment (was broken in last commit)
2008-07-14 21:09:19 +01:00
8589c0691b
Refactor assignment code
2008-07-14 21:04:09 +01:00
99ef8ec4f1
Simplify edge detector code
...
Now generates a `wait until' statement rather than a
sensitivity list.
2008-07-14 20:29:49 +01:00
d22c9a8b05
Simplify blocking assignment
...
Now generates 'wait for 0 ns' after non-blocking assignment
2008-07-14 19:54:45 +01:00
f84f50842c
Support bufif for tri1 nets
2008-07-14 19:13:11 +01:00
65720f49fe
Simple bufif cases
2008-07-14 19:00:58 +01:00
6243736481
Pull-up/pull-down logic devices
2008-07-14 12:04:20 +01:00
e331e4831b
Fix nexus_to_expr where nexus has IVL_LPM_SELECT_PV
2008-07-14 11:53:38 +01:00
78ee61558d
Remove redundant test
...
Signal is guaranteed to appear in arch_scope or its parent
by the surrounding `if' statement.
2008-07-13 15:27:07 +01:00
07c4ff7ea7
Add assertion about result of lpm_to_expr
2008-07-13 15:26:03 +01:00
e5422dddd2
Remove useless `ignore' param to nexus_to_expr
2008-07-13 15:24:35 +01:00
6af201ea03
Refactor nexus expansion functions.
...
Now a single function nexus_to_expr
2008-07-13 15:17:14 +01:00
27a40cfdcd
Constant assignments to outputs
...
If the Verilog source contained a continuous assignment
of a constant to an output, it would not be present in
the VHDL output. This patch generates a VHDL continous
assignment in these cases.
2008-07-13 13:02:17 +01:00
3bd480a375
Allow ouput to be read if connected to child output
...
If output P of A is connected to output Q of B (and A is
instantiated inside B) then VHDL does not allow B to read
the value of Q (also P), but Verilog does. To get around
this the output Q is mapped to P_Sig which is then connected
to P, this allows B to read the value of P/Q via P_Sig.
2008-07-13 12:41:02 +01:00
aa951af2b7
Change 'signdness' to 'signdness'
2008-07-10 19:27:17 +01:00
55747bf79d
Refactor signdness changing code into a single function
...
This is the code that generated calls to signed/unsigned in
the VHDL output.
2008-07-08 13:07:11 +01:00
1cd7689d03
Fix casting with signed/unsigned expressions
...
Previously the code generator tried to infer the VHDL types. Now it
takes a much more dumb approach and forces the VHDL type to be
the same as the ivl type (derived from ivl_expr_signed and
ivl_expr_width) in the expression tree. This works much better :-)
2008-07-08 12:58:50 +01:00
bd5cc96956
Correct vector sizes for bit select
2008-07-08 00:20:31 +01:00
a0dbb1aa5d
Fix more bugs in part selects
2008-07-07 21:45:27 +01:00
4777966b4c
Bit select bug fixes
2008-07-07 21:19:59 +01:00
860a74ddd8
Allow LPMs in port maps
2008-07-07 20:41:29 +01:00
2bb645e0bc
Refactor LPM code to allow lpm->expr function
2008-07-07 19:46:18 +01:00
47db80315c
Add sign extension LPM
2008-07-07 19:27:52 +01:00
0348664512
Correctly determine VHDL type of LHS of part select
2008-07-07 16:35:39 +01:00
3987e0753d
Fix case where booleans are compared against vectors
2008-07-07 16:31:27 +01:00
6b73cc39a5
Add Active_High support func and fix LPM part select
2008-07-07 16:17:54 +01:00
b0de1a8d7e
Implement part select for LHS of assignment
2008-07-07 16:11:45 +01:00
37fe6e4219
Dummy implementation of IVL_LO_BUF*
2008-07-07 15:49:51 +01:00
89cdbf63be
Reduction LPM types
2008-07-07 15:45:20 +01:00
7f955cc070
Move the VHDL support package
2008-07-07 15:36:13 +01:00
4db5b9d7ed
Add unary OR/NOR
...
These are currently implemented with reference to an external
Reduce_OR function
2008-07-07 15:23:57 +01:00
dadd145d09
Add message for unsupported LPM nexus pointer
2008-07-07 15:04:28 +01:00
bdf5ee7ab7
Concat LPM
2008-07-07 14:48:57 +01:00
ebaa4c7d5d
Implement assignment to part select properly
...
Previously the base of the lval was ignored, this ensures
the correct assignment is generated.
2008-07-07 11:00:27 +01:00
c33600bcc3
Add concatenation operator
2008-07-06 18:21:34 +01:00
85d2cc78d6
Finish ternary operator expansion
2008-07-06 17:56:48 +01:00
18071562ba
Partially implement ternary expressions
...
This handles the case where the expression appears as the
right hand side of an assignment. The expression is converted
into a regular if statement.
2008-07-04 21:55:51 +01:00
5aeff6d47d
Merge blocking and non-blocking assignment code
2008-07-04 20:07:38 +01:00
a298b03735
Add bitwise OR
2008-07-04 12:05:49 +01:00
3d0a2b55ce
Avoid declaring same function multiple times
...
If it appears in multiple places in the hierarchy
2008-07-04 12:03:37 +01:00
19871efd5a
Fix bug where sensitivity might reference undefined signals
2008-07-04 11:58:33 +01:00
1410c339de
Make sure any calls to numeric_std Resize have correct type
...
The signed/unsigned-ness of an expression needs to be
preserved over any call to Resize. Also add a sanity
check to make sure non-vector types are not resized.
2008-07-04 11:36:11 +01:00
96d32b29c9
Translate logical expressions correctly.
...
For logical AND/OR in VHDL both operands must be of the
same type (Boolean)
2008-07-04 11:23:32 +01:00
88816e150a
Properly parenthesise unary operators
2008-07-04 11:17:24 +01:00
409fc4dc19
Check if case expression variable is already defined
...
Verilog_Case_Ex is used as a temporary to store the result of
any non-static case expression. This fixes a bug where it would
be declared multiple times if there were multiple case statements
in a block.
2008-07-04 11:15:34 +01:00
c54b36c902
Add logical AND operator
2008-07-04 11:10:20 +01:00
19cbab78b2
Tidy up code to generate default branch of case
2008-07-03 20:04:47 +01:00
1736cd9bc8
Fix uneccessarily complicated generated case statement
...
No need to generate separate case test variable if the
test in the VL source is a simple variable reference.
2008-07-03 16:27:36 +01:00
a5264e9995
Make sure all choices are covered in case statement
2008-07-03 16:17:56 +01:00
6868127ba3
Make sure case expression has the correct type
2008-07-03 16:14:17 +01:00
dbbadbc309
Make sure the renamed signal is used in the sensitivity list
2008-07-03 16:13:02 +01:00
fb08164cbc
List some more illegal VHDL names
2008-07-03 15:20:43 +01:00
7e999c5496
Fix continuous assignment of constants
...
E.g. in assign p = 1 the RHS signal in the generated LPM now
has a correct intial value (and it will never be written to
elsewhere)
2008-07-03 15:13:12 +01:00
4fac825457
Add PV part select type
2008-07-03 14:45:54 +01:00
35c66744db
Cleanup and remove debug output
2008-07-01 11:31:00 +01:00
930e04f6c7
Ensure port map expressions are globally static
2008-07-01 11:28:02 +01:00
37756b8d06
Avoid mapping a signal to itself
2008-07-01 11:13:02 +01:00
596c93ce7e
Rename instance if it has the same name as the type
2008-07-01 11:05:24 +01:00
edfae1abfb
PV LPM part select type
2008-07-01 11:02:49 +01:00
624943b3ca
Simplify port map generation code
2008-07-01 10:59:31 +01:00
ef89a760d6
Add vhdl_element::print method for debugging
2008-07-01 10:44:20 +01:00
050aa277ae
Make vhdl_element::emit a little more generic
2008-07-01 10:37:22 +01:00
f03dfb50ad
Refactor nexus_to_var_ref
2008-07-01 10:33:46 +01:00
6e8474f584
Fix bug where func had to be declared before use
2008-06-30 17:58:15 +01:00
4e73b1b133
Fix bug when resolving nexus to VHDL signal
2008-06-30 17:47:45 +01:00
e08e29c8b4
Add UFUNC LPM type
2008-06-30 16:35:29 +01:00
b82ca28190
Add XOR logic type and fix part select
2008-06-30 16:18:55 +01:00
081f397460
Implement LPM part select
2008-06-27 14:58:03 +01:00
f800298d01
Fix memory leak
2008-06-27 12:29:50 +01:00
301a25303f
Remove useless assertion
2008-06-27 12:21:53 +01:00
b24eb6ce88
Handle local variables in functions
2008-06-27 12:21:27 +01:00
fd60bfd3d2
Rewrite function parameter finding code
2008-06-27 12:18:39 +01:00
500442e5c5
Working function calls
2008-06-25 22:15:57 +01:00
2baf31dff8
Fix bug with $display and integer literals
2008-06-25 21:54:11 +01:00
d997397c38
Generate function calls with parameters
2008-06-25 21:49:22 +01:00
7773000c36
Generate function declarations
2008-06-25 21:40:35 +01:00
042f7ccbcd
Generate a return type for functions
2008-06-25 18:43:50 +01:00
44aa8a6b91
Associate signals with scopes rather than entities
2008-06-25 18:12:57 +01:00
43c671cb5c
Emit VHDL for function declarations
2008-06-25 18:00:48 +01:00
a3df37b851
Initial code to generate function calls
...
Also catch a few null-pointer issues
2008-06-25 17:29:09 +01:00
c01c2bd742
Dummy code for handling function scopes
2008-06-25 12:48:46 +01:00
899a70908e
Fix small bug with initialisation and ammend comments
2008-06-24 20:13:18 +01:00
bf95d77562
Finish replacing vhdl_process with vhdl_procedural
2008-06-24 20:01:06 +01:00
db992e808f
Start using vhdl_procedural instead of vhdl_process
2008-06-24 19:54:22 +01:00
f2aca68b82
Add new vhdl_procedural superclass for process/task/func
2008-06-24 19:50:57 +01:00
12b448ef01
Merge branch 'vhdl' of git@github.com:nickg/iverilog into vhdl
...
Conflicts:
tgt-vhdl/vhdl_syntax.cc
2008-06-24 19:42:35 +01:00
e77bb0157e
Remove redundant methods from vhdl_arch
2008-06-24 19:39:05 +01:00
75631bd8f1
Move is_inital code out of vhdl_process into vhdl_scope
...
Part of tidy up before implementing functions
2008-06-24 19:06:06 +01:00
63b1887ff2
Refactor code to use the new vhdl_scope class
2008-06-24 18:52:25 +01:00
ba36e47575
Add new vhdl_scope class and refactor
2008-06-24 18:12:00 +01:00
3866c4526e
Simplify code to emit operators
2008-06-24 14:58:58 +01:00
cb08f02de1
Resize signed/unsigned bit vectors correctly
2008-06-24 10:58:21 +01:00
4188fbecee
Add XOR operator and catch default case branch
2008-06-24 10:55:45 +01:00
f261bf7e97
Fix bug where variables could be declared twice
2008-06-23 15:13:10 +01:00
88dc9b6b63
Remove debugging information from the output
2008-06-23 15:02:26 +01:00
632a265e14
Fix casting/resizing order bug
2008-06-23 15:00:55 +01:00
449cd0a76e
Correctly generate signed/unsigned types
2008-06-23 14:28:27 +01:00
44958409f5
A slightly smarter $display
2008-06-23 13:45:24 +01:00
f81129aa68
Fix some bugs with blocking assignment
2008-06-23 13:36:28 +01:00
e5ef0d97bd
Fix signed/unsigned resizing
2008-06-23 13:04:28 +01:00
469036990a
Output blocking assignments in the right place
2008-06-23 12:30:48 +01:00
d06f5c7c54
Emit loop statements with the correct indent
2008-06-23 12:27:30 +01:00
9911939576
Simplify casting code
2008-06-23 12:21:10 +01:00
c9ace14c40
Shift operators working correctly
2008-06-23 12:14:12 +01:00
d5cdb91d55
Handle complex expressions in case statement
2008-06-23 11:36:12 +01:00
75f7c9ae0c
Only move constant assignments into initialisation
2008-06-21 16:40:18 +01:00
c926454a41
Statements might be emitted in wrong order
2008-06-21 16:33:05 +01:00
5cfe7ea0aa
Tidy up output
2008-06-21 16:28:07 +01:00
c70fb4ba08
Simple implementation of IVL_EX_SELECT
2008-06-21 16:17:44 +01:00
7cba9f3cb2
Shift left/right
2008-06-21 15:19:33 +01:00
d6acb8d059
Less than / greater than
2008-06-21 15:16:22 +01:00
ec23b70bb7
While loops
2008-06-21 15:13:44 +01:00
58f2f5007d
Bitwise AND
2008-06-21 15:05:48 +01:00
0caf4fd9d0
Add case statement
2008-06-21 15:03:36 +01:00
037ce08f72
Fix tiny bug in $display code
2008-06-21 14:42:54 +01:00
204862ac3c
Implement $write
2008-06-20 19:00:07 +01:00
0f50849fbb
Add call to To_Integer when printing signed/unsigned
2008-06-20 18:26:39 +01:00
404c22ac86
Improved implementation of $display
2008-06-20 11:51:13 +01:00
08d80b35cb
Rename signals that would be illegal VHDL names
2008-06-19 16:15:47 +01:00
6622b5fe3a
Compare logic values for === and !==
2008-06-19 16:08:33 +01:00
d7bb5658f2
Translate IVL_ST_DELAYX statements
2008-06-19 12:16:19 +01:00
be12f56856
Document blocking assignment behaviour
2008-06-18 14:04:16 +01:00
e0f41198d6
Blocking assignment working correctly
2008-06-18 13:49:03 +01:00
fb31a88c51
Blocking assignment nearly working
2008-06-18 13:30:19 +01:00
254ccb9ccb
First passing at blocking assignment
2008-06-18 13:06:27 +01:00
d2bebee9d9
Refactor before adding blocking assignment
2008-06-18 12:51:11 +01:00
af8c08e6a7
Allow optional VHPI $finish implementation
2008-06-17 20:16:16 +01:00
01249000c3
Temporarily treat blocking assignment as non-blocking
2008-06-17 14:07:36 +01:00
1debbc3100
Simplify edge_detector() a bit
2008-06-16 20:06:06 +01:00
ae0b09dd3a
Don't bother emitting else part if it's empty
2008-06-16 19:53:42 +01:00
8d0afa632d
Subtraction and multiplication LPM devices
2008-06-16 19:49:24 +01:00
561953e494
Minial LPM to support continuous assignments
2008-06-16 19:41:01 +01:00
83a7796b74
Make sure signal names conform to VHDL rules
2008-06-16 17:37:17 +01:00
ce72eb4eb4
Fix Valgrind warnings
2008-06-16 14:26:38 +01:00
7cde5f247e
Add translation for not-equals operator
2008-06-16 12:47:41 +01:00
849e7cb4d5
Add equality operator
2008-06-16 12:20:28 +01:00
92c823680a
Fix crash when `if' statement had no `else'
2008-06-16 12:13:01 +01:00
8a9486eb49
Eliminate useless Resize() call
2008-06-14 18:11:10 +01:00
2fb57805ea
Use signed rather than std_logic_vector
...
Arithmetic operators now working correctly
2008-06-14 18:03:25 +01:00
919c1d695c
Adding binary +
2008-06-14 17:09:31 +01:00
0ea64ad8ab
Correct misleading comment
2008-06-13 14:47:06 +01:00
9fbb449e06
Optimise away empty (VHDL) processes
2008-06-13 14:17:24 +01:00
be3c4cf268
Generate signal initial values from `initial' processes
2008-06-13 14:10:28 +01:00
0a8fd50c4a
Find assignments that could be initializers
2008-06-13 13:59:48 +01:00
70db096b6d
Clean up the edge detector code a bit
2008-06-13 12:52:20 +01:00
005df31a0d
Use renamed signal in expressions, if there is one
2008-06-13 12:39:18 +01:00
d6193c1622
Add _Reg internal signal if output is registered
2008-06-13 12:34:27 +01:00
b8c1f9ab67
A system for linking ivl_signal_t to entities
2008-06-12 20:26:23 +01:00
0df3eabe26
Convert `if (foo) ..' to `if foo = '1' then ..'
2008-06-12 11:36:21 +01:00
8fe2211e2b
Generate `after' modifier instead of `wait' statements
2008-06-12 11:24:43 +01:00
645ee2003f
Translation for unary not
2008-06-12 10:56:28 +01:00
d6f1162547
Generate correct VHDL signal values
2008-06-12 10:50:46 +01:00
46991aa65c
Generate process bodies in the right place
2008-06-12 10:47:52 +01:00
7eb41304e6
Generate rising/falling edge detectors
2008-06-12 10:36:38 +01:00
19e60b698f
Translate if statements
2008-06-11 14:20:05 +01:00
a7cfdc3a87
Add VHDL if statement to AST types
2008-06-11 14:11:37 +01:00
b010b8e3ca
Use `assert false' as initial translation of $finish
2008-06-11 13:37:21 +01:00
26a2c69c2e
Change architecture name to `FromVerilog'
2008-06-11 11:31:43 +01:00
5a7cfd8c02
Clean up vhdl_comp_inst
2008-06-10 14:00:15 +01:00
babe694366
Generate port mappings
2008-06-10 13:58:41 +01:00
Nick Gasson