Branches - iverilog - Gitea: Git with a cup of tea

master

aad14df3d7 · Switch to std::round() and a common routine for real to uint64_t · Updated 2025-12-17 04:52:36 +01:00

gh-pages 6dea3b9b8f · Deploy to GitHub pages · Updated 2025-12-17 04:55:50 +01:00	10253 1		ZIP TAR.GZ
steveicarus/rework-regression-tests-20250119 bf97480fc6 · ivtest: Reformat more tests to the now format · Updated 2025-01-20 04:32:45 +01:00 luke	101 1		ZIP TAR.GZ
v12-branch 4fd5291632 · ci: Windows: Add gperf to dependency list · Updated 2022-12-27 03:23:55 +01:00 luke	719 4		ZIP TAR.GZ
v11-branch b2f2414f48 · Add regression test for issue #756. · Updated 2022-08-27 17:23:46 +02:00 luke	1528 134		ZIP TAR.GZ
array-copy 3c2fb6a601 · Fix dynamic array assignment to make a copy of the rvalue. · Updated 2020-11-26 21:52:06 +01:00 luke	1511 0	Included	ZIP TAR.GZ
v10-branch b988543096 · Use GNU make pattern rules to handle multiple file output from bison. · Updated 2020-08-17 18:03:57 +02:00 luke	2391 233		ZIP TAR.GZ
v0_8-branch 0e4dfa6732 · Fix some compile warnings when using more modern compilers · Updated 2015-08-19 20:20:57 +02:00 luke	7268 272		ZIP TAR.GZ
v0_9-branch dacd613f94 · Backported fix for br991 from devel branch. · Updated 2015-08-19 09:49:28 +02:00 luke	5062 519		ZIP TAR.GZ
vec4-stack 105521b547 · Merge branch 'master' into vec4-stack · Updated 2014-12-06 17:24:46 +01:00 luke	2719 0	Included	ZIP TAR.GZ
s20120501-branch 303710fa32 · Repair handling of attributes attached to variables. · Updated 2012-05-09 20:17:06 +02:00 luke	3806 1		ZIP TAR.GZ
s20111127-branch bb4f074bde · Prepare for snapshot 2011-11-27 · Updated 2011-11-27 20:42:02 +01:00 luke	3937 0	Included	ZIP TAR.GZ
pei-branch 4818db887e · Fix for LXT/LXT2 output using MinGW. · Updated 2010-02-09 06:07:45 +01:00 luke	4653 0	Included	ZIP TAR.GZ
vvp-net-out-rework 0b2ce7a5ec · Merge branch 'master' into vvp-net-out-rework · Updated 2009-09-23 06:47:10 +02:00 luke	4821 0	Included	ZIP TAR.GZ
verilog-ams dbe45159ab · Merge branch 'master' into verilog-ams · Updated 2008-12-11 04:45:35 +01:00 luke	5204 0	Included	ZIP TAR.GZ
embedded-vvp 4ee9cc6247 · Additions and changes for using VVP as DLL with an analog simulator. · Updated 2008-11-17 03:29:02 +01:00 luke	5279 1		ZIP TAR.GZ
elaborate-net-rework 6411e96193 · Generate delay devices for sign-extend devices. · Updated 2008-09-07 03:05:18 +02:00 luke	5453 0	Included	ZIP TAR.GZ
performance afa2478801 · Merge branch 'master' of ssh://steve-icarus@icarus.com/home/u/icarus/steve/git/verilog · Updated 2008-06-10 01:58:21 +02:00 luke	6039 7		ZIP TAR.GZ
var-array-rework d1daf6733f · Allow VPI callbacks to var array words. · Updated 2008-05-21 03:30:56 +02:00 luke	6136 0	Included	ZIP TAR.GZ
v0_8-devel c92b37b1bd · Error message for inconnected primitive ports. · Updated 2007-09-05 01:26:43 +02:00 luke	7268 164		ZIP TAR.GZ
cvshead 87e813766a · Detect and ignore specify edge expressions · Updated 2007-06-14 05:50:00 +02:00 luke	6664 0	Included	ZIP TAR.GZ

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