This patch optimises away straight line sequences like:
wait for 0 ns;
wait for X ns;
to:
wait for X ns;
This tidies up the output a bit.
It also has the effect of removing all code from initial
processes where the assignments have been extracted as
VHDL signal intialisers. (c.f. pr2391337)
This prints out an error message rather than crashing out with
an assertion failure when a function assigns to a non-local
variable, which cannot be done in VHDL.
This changes the assignment statement generator so that
each VHDL declaration "knows" which type of assignment
statement can/should be used on (i.e. signals must be
assigned with <=). This will help us catch cases when
we try to use, for example, := with signals. This occurs
in pr2362211 where we try to assign to a signal within
a function (where only := can be used).
If a module's input was connected to a nexus that contained
a constant driver. That constant would be incorrectly generated
as an assignment to the input *inside* the child module (instead
of an assignment inside the instantiating module).
With this small patch, building succeeds with Debian's current gcc-snapshot,
gcc (Debian 20081130-1) 4.4.0 20081130 (experimental) [trunk revision 142292]
That gcc also warns about the remaining #idents in
vvp/concat.cc
vvp/dff.h
The resulting build shows some regressions in the test suite, that
I am still investigating. The patch does not break building, or show
test suite regressions, with gcc-4.3.
Signals of width 1 are declared in VHDL as std_logic, as this
is the usual way to represent them. Unfortunately, we cannot
distinguish between
reg [0:0] a;
and
reg a;
This patch avoids trying to slice a std_logic so a[0] is equivalent to a.
This patch removes the CVS ident information from the Makefile.in
files it also puts in the current version 0.9.devel for the default
VERSION definition. This is normally passed down, but a local make
will use the value from the local Makefile. This will eventually be
replaced with a file based version to give us just one place to
reliably modify the version.
This patch updates the GNU address in the -V output, adds the
VERSION_TAG info to the tgt-vvp back end and adds the whole -V
hook to the tgt-vhdl back end.
Fix for pr2224949
The compiler generates a concatenation LPM to zero-pad ports when the
signal widths don't match up. However, when the VHDL generator generated
the input signals to this LPM it incorrectly sized them to be the width
of the result.
The VHDL converter erroneously treated a casez and casex exactly
the same. In reality a casez compares a 'x' value (it is not a
don't care). It also adds support for a full don't care case by
just returning True for the condition.
This configure option causes the installed commands to have
a suffix string that makes them distinct from other versions
that also have a suffix string. This allows for multiple
installed versions of Icarus Verilog.
Also, move installed C/C++ header files into a subdirectory of
their own under the target include directory, to make clearer
the purpose and source of those files.
VHDL can't select bits from arbitrary expression so sometimes
translating IVL_EX_SELECT would fail. This is easily fixed by
replacing the select with a shift in this instance (and the
resizing)
make_safe_name now makes sure a VHDL signal is never given a
name that conflicts with any reserved words. If it does, we
just prepend VL_.
(This code was already present, but the full list of reserved
words wasn't.)
Continue cleaning up shadowed variables, flagged by turning on -Wshadow.
No intended change in functionality. This patch set covers the tgt-vhdl
directory, and was tested by Nick.
A casex statement cannot be directly translated to a VHDL case
statement as VHDL does not treat the don't-care bit as special.
The solution here is to generate an if statement from the casex
which compares only the non-don't-care bit positions.
Emitting a VHDL expression like Resize("01", 32) is ambiguous
between interpreting "01" as a Signed or an Unsigned. There's
no point actually outputting this as we can sign-extend the
constant value in the code generator, which is what this
patch does.
The exponentiation operator in VHDL is not defined for numeric_std
types. We can get around this by converting the operands to integers,
performing the operation, then converting the result back to the
original type. This will work OK in simulation but certainly will not
synthesise unless the operands are constant.
However, even this does not work quite correctly. The Integer type in
VHDL is signed and usually only 32 bits, therefore any result larger
than this will overflow and raise an exception. I can't see a way
around this at the moment.
Target selection is done by the DLL target code generator, so there
is no value having a layer of target selection ahead of it. Remove
all that redundant code and simplify the target config files to reflect
this.
Generate scopes were previously ignored, and this would cause a segfault
later on. This patch gives an error whenever it encounters a generate
scope. This should be removed once generate statements are implemented.
Previously only signedness was only corrected for the
result. This patch ensures the VHDL operands have the
same signedness as their Verilog counterparts.
This fixes a few of the signedX tests.
This splits up the monolithic and confusing vhdl_expr::cast function into
several smaller to_XXX functions which each generate code to cast an
expression to type XXX. This makes it much easier to understand and maintain.
Mostly this ensures that a recursive call to a function
is made with the correct types (this may involve generating
code to cast expressions to the correct type).
Nick Gasson
Larry Doolittle
Cary R
Stephen Williams