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OpenRAM
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1601 Commits

Author SHA1 Message Date
Hunter Nichols d08181455c Added multiport bitcell support for storage node checks 2019-05-20 22:50:03 -07:00
Hunter Nichols 099bc4e258 Added bitcell check to storage nodes. 2019-05-20 18:35:52 -07:00
Hunter Nichols 412f9bb463 Added additional check to bitline to reduce false positives. 2019-05-17 01:56:22 -07:00
Hunter Nichols 03a762d311 Replaced constant string comparisons with enums 2019-05-16 14:18:33 -07:00
Hunter Nichols d8617acff2 Merged with dev 2019-05-15 18:48:00 -07:00
Hunter Nichols a80698918b Fixed test issues, removed all bitcells not relevant for timing graph. 2019-05-15 17:17:26 -07:00
Hunter Nichols 178d3df5f5 Added graph to characterizer to get net names and perform s_en checks. Graph not working with column mux. 2019-05-14 14:44:49 -07:00
Hunter Nichols b30c20ffb5 Added graph creation to characterizer, re-arranged pin creation. 2019-05-14 01:15:50 -07:00
Hunter Nichols b4cce65889 Added incorrect read checking in characterizer. 2019-05-13 19:38:46 -07:00
mrg 3fa8c5543a Merge branch 'dev' into scn3me_subm 2019-05-08 17:52:38 -07:00
mrg a5ed9b56cd Optional m4 in design class 2019-05-08 17:51:38 -07:00
Matt Guthaus c24879162a Add back scn3me_subm tech files 2019-05-08 16:06:21 -07:00
Hunter Nichols d54074d68e Made timing graph more gate-level. Changed edges to be defined by inputs/ouputs and name based. 2019-05-07 00:52:27 -07:00
Matt Guthaus 0f03553689 Update copyright to correct years. 2019-05-06 06:50:15 -07:00
Hunter Nichols 5bfc42fdbb Added quality improvements to graph: improved naming, auto vdd/gnd removal 2019-04-29 23:57:25 -07:00
Matt Guthaus 534c6b36df Use correct back end config file. 2019-04-29 10:20:27 -07:00
Matt Guthaus 8d8565bd9c Add inline_drclvs option for improved coverage 2019-04-29 09:15:46 -07:00
Matt Guthaus 978ba9d2f2 Refactor run scripts. 
Run DRC, LVS, and PEX share a run_*.sh script.
 2019-04-26 15:43:46 -07:00
Matt Guthaus 946a0aca86 Simplify DRC and LVS run scripts. 
Modified run scripts to work on local only files in the temp
directory. This assumes the files and subckts are named the
same as the clel name. Script now copies library files
to the temp directory as well.
 2019-04-26 15:17:39 -07:00
Matt Guthaus 51a97979b9 Add front and back-end test 30. 2019-04-26 15:17:19 -07:00
Matt Guthaus d23aa9a1bd Use local setup.tcl and flatten bitcell arrays. 2019-04-26 14:12:51 -07:00
Matt Guthaus 9cead23f22 Add hierarchy to netgen LVS command. 2019-04-26 13:46:34 -07:00
Matt Guthaus 3f9a987e51 Update copyright. Add header to all OpenRAM files. 2019-04-26 12:33:53 -07:00
Matt Guthaus 0439b129bb Some pgates are designs since not a fixed height 2019-04-26 12:33:53 -07:00
Matt Guthaus 05ad4285af Cleanup pgate code. 
Moved create_netlist and create_layout to the pgate class
from which everything is derived. Modified all pgates
to have consistent debug output and order of init function.
 2019-04-26 12:30:42 -07:00
Jesse Cirimelli-Low e507fbd5e9 Merge branch 'datasheet_gen' into dev 2019-04-26 12:29:37 -07:00
Matt Guthaus 3ffcad0db8 Add port makeall for removing symmetry problems in netgen 2019-04-26 09:17:52 -07:00
Hunter Nichols f35385f42a Cleaned up names, added exclusions to narrow paths for analysis. 2019-04-24 23:51:09 -07:00
Hunter Nichols e292767166 Added graph creation and functions in base class and lower level modules. 2019-04-24 14:23:22 -07:00
Matt Guthaus 59d2e45744 Move characterization on/off feedback to report_status. 2019-04-24 11:30:38 -07:00
Matt Guthaus 7f5e6dd6f8 Fix unconnected supply pin bug in supply router. 
Simplified some of the supply router pin groups so that it assumes
each group is fully connected. When computing enclosures of the
pins on the routing grid, it will remove disconnected enclosure
shapes to keep things connected.
 2019-04-24 10:54:22 -07:00
Matt Guthaus 66c703d932 Simplify router code to clean it up a bit. 2019-04-22 15:30:35 -07:00
Matt Guthaus 5b828f32cb Create auxiliary run_drc.sh and run_lvs.sh with arguments for calibre 2019-04-22 15:12:59 -07:00
Hunter Nichols 4f28295e20 Added initial graph for correct naming 2019-04-19 01:27:06 -07:00
Jesse Cirimelli-Low 49e5f97eb4 fixed bug where log would fail to generate if output folder did not exist 2019-04-17 15:02:10 -07:00
Matt Guthaus 25bc3a66ed Add far left option for contact placement in pgates. 2019-04-17 13:41:35 -07:00
Matt Guthaus a35bf29bdd Improve print output for debugging layout objects. 2019-04-17 13:41:17 -07:00
Matt Guthaus be20408fb2 Rewrite add_contact to use layer directions. 2019-04-15 18:00:36 -07:00
Hunter Nichols c1411f4227 Applied quick corner estimation to analytical delay. 2019-04-09 12:26:54 -07:00
Hunter Nichols a500d7ee3d Adjusted bitcell analytical delays for multiport cells. 2019-04-09 02:49:52 -07:00
Hunter Nichols 25c034f85d Added more accurate bitline delay capacitance estimations 2019-04-09 01:56:32 -07:00
Hunter Nichols 1438519495 Added check to pdriver for 0 fanout which can break compute_sizes. 2019-04-03 17:53:28 -07:00
Hunter Nichols edac60d2a8 Merged with dev and fixed conflicts. 2019-04-03 16:45:01 -07:00
Hunter Nichols cc5b347f42 Added analyical model test which compares measured delay to model delay. 2019-04-03 16:26:20 -07:00
Hunter Nichols f6eefc1728 Added updated analytical characterization with combined models 2019-04-02 01:09:31 -07:00
Matt Guthaus df4e2fead8 Return empty set instead of a list. 2019-04-01 15:59:57 -07:00
Matt Guthaus 07ecf52b9f Add giant example for front-end mode 2019-04-01 15:49:01 -07:00
Matt Guthaus 5f37677225 Convert pin map to a set for faster membership. 2019-04-01 15:45:44 -07:00
Matt Guthaus 74f904a509 Cleanup options for front-end. Improve info output. 2019-04-01 10:35:17 -07:00
Matt Guthaus c3e074c069 Add option for routing supplies. Off by default, but enabled in unit test config files. 2019-04-01 09:58:59 -07:00
Hunter Nichols 97777475b4 Added additions to account for custom delay chains. 2019-03-28 17:16:23 -07:00
Hunter Nichols 50d3b4cb8d Added some bitline measures to the model_checker 2019-03-19 15:03:57 -07:00
Matt Guthaus 95d96bd45d Add OPENRAM_TMP environment check 2019-03-08 11:12:30 -08:00
Matt Guthaus 0354e2dfb7 Rename config_20 to config since it is used in all tests 2019-03-08 10:47:41 -08:00
Matt Guthaus 196710ec3e Remove factory from lef and verilog tests 2019-03-08 09:22:48 -08:00
Matt Guthaus bd256d33d6 Remove syntax error 2019-03-08 08:35:18 -08:00
Matt Guthaus 7129f79dc4 Merge remote-tracking branch 'origin' into tech_reorg 2019-03-08 08:33:46 -08:00
Matt Guthaus d8f64500e6 Remove factory create from lib tests so that we can give required name 2019-03-08 08:31:26 -08:00
Hunter Nichols e39f9ee481 Merge branch 'dev' into multiport_characterization 2019-03-07 12:31:14 -08:00
Hunter Nichols 910878ed30 Removed bitline measures until hardcoded signal names are made dynamic 2019-03-07 12:30:27 -08:00
Jesse Cirimelli-Low e6311dd44a Merge branch 'datasheet_gen' into dev 2019-03-06 23:47:19 -08:00
Jesse Cirimelli-Low 4754e6851d add_db takes commline line argv for path 2019-03-06 22:21:05 -08:00
Jesse Cirimelli-Low c1770036ac made the add_db code much simpler 2019-03-06 22:20:34 -08:00
Jesse Cirimelli-Low 83e810f8b8 added sorting to deliverables output 2019-03-06 21:12:21 -08:00
Jesse Cirimelli-Low fac9ff9be6 changed add_db.py to uncommenting method 2019-03-06 20:59:52 -08:00
Matt Guthaus 95137a2c26 Wrap debug line 2019-03-06 14:24:24 -08:00
Matt Guthaus 77229d5121 Reduce verbosity 2019-03-06 14:24:18 -08:00
Matt Guthaus c4c844a8a2 Remove duplicate module name checking since we use the factory 2019-03-06 14:14:46 -08:00
Matt Guthaus 09a429aef7 Update unit tests to all use the sram_factory 2019-03-06 14:12:24 -08:00
Matt Guthaus acf2798a18 Add link to presentation in README 2019-03-06 08:29:43 -08:00
Matt Guthaus cfc14f327e Factor default corner out of import_tech 2019-03-06 07:46:30 -08:00
Matt Guthaus d178801882 Simplify tech organization and import 2019-03-06 07:41:38 -08:00
Hunter Nichols 80a325fe32 Added corner information for analytical power estimation. 2019-03-04 19:27:53 -08:00
Hunter Nichols ddeb40c9bf Added lib test which generates multiple corner models. Only does process currently. 2019-03-04 16:27:10 -08:00
Hunter Nichols 7e67b741f6 Merge branch 'dev' into multiport_characterization 2019-03-04 00:43:03 -08:00
Hunter Nichols 0e96648211 Added linear corner factors in analytical delay model. 2019-03-04 00:42:18 -08:00
Matt Guthaus 22deab959c Fix setup_bitcell to allow user to force override the bitcell. 2019-03-03 11:58:41 -08:00
Matt Guthaus abcb1cfa2c Correct elsif to elif 2019-02-28 09:17:24 -08:00
Matt Guthaus da6aa161de Don't autodetect the bitcell if the user overrides it 2019-02-28 09:12:32 -08:00
Matt Guthaus fb7264bae2 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2019-02-28 08:44:18 -08:00
Jesse Cirimelli-Low 3802c537e5 added add_db.py to add .db files to datasheets 2019-02-27 22:20:06 -08:00
Hunter Nichols 816669b9ca Merge branch 'dev' into multiport_characterization 2019-02-26 22:48:39 -08:00
Hunter Nichols ea51cfdbb4 Removed data collection script 2019-02-26 22:46:38 -08:00
Hunter Nichols 42bc6efb21 Added additional graphing and data collection to script 2019-02-26 20:06:35 -08:00
Matt Guthaus f865e66181 Remove git_id file 2019-02-25 16:47:38 -08:00
Matt Guthaus de977732db Only warn if not unit tests 2019-02-25 16:13:54 -08:00
Matt Guthaus 1f1426b97c Add auto-detect of custom bitcells 2019-02-25 16:10:34 -08:00
Matt Guthaus c79b97eb51 Merge remote-tracking branch 'origin/dev' into multiport 2019-02-25 15:46:39 -08:00
Matt Guthaus a4b5368302 Add total size in warning for output size. 2019-02-25 14:57:18 -08:00
Matt Guthaus 638afaeb31 Remove duplicate profile stats script 2019-02-25 10:14:02 -08:00
Matt Guthaus a18071a4ff Add warning for large memory sizes 2019-02-25 10:07:05 -08:00
Jesse Cirimelli-Low 34294443d4 updated logos and css for official colors 2019-02-25 07:46:34 -08:00
Jesse Cirimelli-Low 677588290d merging with dev now that it is passing 2019-02-25 07:05:06 -08:00
Matt Guthaus a210fdda0f Fix arguments for none verification 2019-02-24 10:49:35 -08:00
Matt Guthaus 9b785cd535 Fix error in cell width. Fix escape warning. 2019-02-24 10:48:54 -08:00
Matt Guthaus 4577d380f9 Add example 1w/1r 2019-02-24 09:57:34 -08:00
Matt Guthaus 6cdc870091 Copy 1rw/1r cell to 1w/1r. 2019-02-24 09:54:45 -08:00
Matt Guthaus 6c9ae1c659 Remove temp names in DRC/LVS. Extract unique doesn't actually extract. 2019-02-24 07:26:21 -08:00
Jesse Cirimelli-Low b9525e0f9e Merge branch 'dev' into datasheet_gen 2019-02-23 15:45:51 -08:00
Matt Guthaus 4da56098e7 Merge branch 'magic_lvs_ports' into dev 2019-02-22 19:02:43 -08:00
Matt Guthaus 599e5457a0 Fix all libs to have pin indices 2019-02-22 17:40:49 -08:00
Matt Guthaus 583dc4410b Revert bus bits back into pins 2019-02-22 16:22:27 -08:00
Matt Guthaus 9459839c06 Clean up output file names for lvs. Update lvs script in magic. 2019-02-22 14:38:00 -08:00
Jesse Cirimelli-Low 8c9c910855 Merge branch 'datasheet_gen' into dev 2019-02-22 11:41:03 -08:00
Jesse Cirimelli-Low ff09254590 fixed analytical flag 2019-02-22 08:19:54 -08:00
Jesse Cirimelli-Low 0cabee060d fixed area rounding 2019-02-22 06:57:54 -08:00
Jesse Cirimelli-Low b4f1d53a1b fixed DRC datasheet error 2019-02-22 06:46:28 -08:00
Matt Guthaus d043c72277 Fix temp name error in openram.py 2019-02-21 11:16:21 -08:00
Matt Guthaus bb408d0a45 Add missing / in output path for log 2019-02-21 10:23:30 -08:00
Jennifer Eve Sowash 1249dcc34d Merge branch 'dev' into pdriver 2019-02-20 13:00:58 -08:00
Jennifer Eve Sowash 6d3a29328c Fixed a bug with corner_name in lib.py remaining static. 2019-02-20 12:59:40 -08:00
Jesse Cirimelli-Low 723ec9925f Merge branch 'datasheet_gen' into dev 2019-02-15 21:47:24 -08:00
Jesse Cirimelli-Low d533a8ae26 fixed logger typo 2019-02-15 21:45:05 -08:00
Jesse Cirimelli-Low e3ff9b53e9 fixed area not being found 2019-02-14 07:01:35 -08:00
Hunter Nichols 8c1fe253d5 Added variable fanouts to delay testing. 2019-02-13 22:24:58 -08:00
Jesse Cirimelli-Low 3f761afcbc Merge branch 'datasheet_gen' into dev 2019-02-13 17:43:31 -08:00
Matt Guthaus d4c21cd26e Remove extraneous character. 2019-02-13 17:41:33 -08:00
Matt Guthaus 2553439447 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into dev 2019-02-13 17:01:41 -08:00
Matt Guthaus c359bbf42a Fix deprecation warnings in regex by converting to raw strings. Add error if unable to find DRC errors in Magic. 2019-02-13 17:01:26 -08:00
Jesse Cirimelli-Low e890c0e188 fixed -v logging 2019-02-13 15:21:16 -08:00
Hunter Nichols 4faec52409 Allowed data collection and analysis to run independently. 2019-02-12 20:58:50 -08:00
Hunter Nichols a4bb481612 Added tracking for available data. 2019-02-12 16:28:37 -08:00
Jesse Cirimelli-Low 36d8d98b17 Merge branch 'dev' into datasheet_gen 2019-02-08 12:05:04 -08:00
Hunter Nichols 9e23e6584a Made variance plot look slightly better. 2019-02-07 15:30:47 -08:00
Hunter Nichols 5e9851c5f1 Merge branch 'dev' into multiport_characterization 2019-02-07 14:31:26 -08:00
Hunter Nichols ebf43298c0 Added mean/variance plotting 2019-02-07 14:26:48 -08:00
Matt Guthaus d9efb682dd Do not clean up if preserve temp in local_drc_check 2019-02-07 11:08:34 -08:00
Jesse Cirimelli-Low bfc20a9aa9 removes debug corners 2019-02-07 06:38:07 -08:00
Jesse Cirimelli-Low be4b7697cb Merge branch 'dev' into datasheet_gen 2019-02-07 06:35:57 -08:00
Jesse Cirimelli-Low 6cde6beafa added documetation to functions 2019-02-07 06:33:39 -08:00
Hunter Nichols d0edda93ad Added more variance analysis for the delay data 2019-02-07 02:27:22 -08:00
Jesse Cirimelli-Low e131af2cc3 power added to datasheet (finally) 2019-02-06 20:31:22 -08:00
Hunter Nichols 690055174d Fixed bug in control logic test with port configs. 2019-02-06 20:09:01 -08:00
Hunter Nichols 56e79c050b Changed test values to fix tests. 2019-02-06 15:27:29 -08:00
Hunter Nichols 01c8405d12 Fix bitline measurement delays and adjusted default delay chain for column mux srams 2019-02-06 00:46:25 -08:00
Hunter Nichols 5f01a52113 Fixed some delay model bugs. 2019-02-05 21:15:12 -08:00
Jesse Cirimelli-Low 374e7a31eb Merge branch 'dev' into datasheet_gen 2019-02-05 17:14:58 -08:00
Hunter Nichols e3d003d410 Adjusted test values to account for recent changes. 2019-02-05 00:43:16 -08:00
Hunter Nichols 543e0a1b9a Merge branch 'dev' into multiport_characterization 2019-02-04 23:54:16 -08:00
Hunter Nichols 12723adb0c Modified some testing and initial delay chain sizes. 2019-02-04 23:38:26 -08:00
Jesse Cirimelli-Low c22025839c datasheet now indicates if analytical or characterizer is used 2019-01-31 08:28:51 -08:00
Jesse Cirimelli-Low 21868e1b60 removed expanded process names from corners 2019-01-31 08:09:00 -08:00
Hunter Nichols 8d7823e4dd Added delay ratio comparisons between model and measurements 2019-01-31 00:26:27 -08:00
Jesse Cirimelli-Low 475db65d26 added units to AREA on datasheet 2019-01-30 17:49:43 -08:00
Matt Guthaus ec1fb087b5 Check membership of keys without using keys() list 2019-01-30 13:02:34 -08:00
Hunter Nichols 45fceb1f4e Added word per row to sram config with a default arguement to fix test. 2019-01-30 11:43:47 -08:00
Matt Guthaus 74fbe8fe63 Convert source and target lists to sets for faster contains check. 2019-01-30 11:15:47 -08:00
Matt Guthaus 07f4d639eb Remove non-rectangular error and just skip them. 2019-01-30 10:25:01 -08:00
Matt Guthaus 7836929db2 Use hash of tuples instead of checking rectangle in list 2019-01-30 10:03:07 -08:00
Matt Guthaus aaf028cacf Optimize hpwl runtime. Fix error in via cost when L shape. 2019-01-30 08:49:47 -08:00