luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
3,383 Commits 4 Branches 63 Tags 78 MiB
Commit Graph

2951 Commits

Author SHA1 Message Date
Hunter Nichols d6d8a037f1 Added values to datasheet info which will be used for model training 2021-01-11 15:20:56 -08:00
mrg 2101d89646 Merge branch 'dev' into supply_router 2021-01-11 13:52:59 -08:00
mrg 1c6d4eedd1 Add new empty debug function. 2021-01-11 13:52:41 -08:00
Hunter Nichols 6b053c8185 Adjusted margin for the period in elmore model 2021-01-11 12:53:14 -08:00
mrg 7506ba81be Refactor how blocked_grids work. Must still calculate blockages based on enclosed pins. 2021-01-11 11:12:45 -08:00
mrg 504f9aa892 Space tx in pinv_dec for power routing. 2021-01-08 11:34:58 -08:00
mrg f428ff4bfd v1.1.14 2021-01-07 10:33:21 -08:00
mrg 1a1b5a49b2 Merge remote-tracking branch 'private/dev' into dev 2021-01-07 10:32:50 -08:00
mrg c0df3ff1da Merge remote-tracking branch 'private/dev' 2021-01-07 10:20:17 -08:00
mrg 0faa14c0e3 Sort escape pins by distance to perimeter to reduce blockages. 2021-01-07 10:12:02 -08:00
Hunter Nichols d8437249f7 Condensed some datasheet code in lib.py 2021-01-06 15:53:22 -08:00
mrg 66ff1fe990 Only unblock source/target instead of all components for cleaner routes 2021-01-06 15:14:56 -08:00
Hunter Nichols bb841fc84d Added option to output the datasheet.info file. 2021-01-06 12:45:34 -08:00
mrg 7eb1e2f2d1 Keep previous pin shapes which were used in router pin connections. 2021-01-06 11:31:16 -08:00
mrg 9a6ca328f6 Temporarily disable flatten and readonly in magic DRC 2021-01-06 09:42:56 -08:00
mrg be79789097 Return empty string instead of None when no grid type 2021-01-06 09:41:13 -08:00
mrg 72dc1c58da Initialize queue only in init_queue function 2021-01-06 09:40:49 -08:00
mrg ec6f0f1873 Escape route to any side 2021-01-06 09:40:32 -08:00
mrg b22d2a76a7 Make clear source/target option instead of general setter (bug to remove source/target fixed) 2021-01-06 09:39:50 -08:00
mrg d61fcb3be3 Fix lpp erase bug in removing router annotations 2021-01-06 09:39:01 -08:00
Hunter Nichols cd84cf1973 Merged and addressed conflict in delay.py 2021-01-06 01:37:16 -08:00
Hunter Nichols 48baf3ab4e Updated test to use new analytical class 2021-01-06 01:34:44 -08:00
mrg 4fc0357282 Small readability edit to dff_buf 2021-01-04 13:16:23 -08:00
mrg 82178bcf89 Change info from exit to escape 2021-01-04 11:52:02 -08:00
mrg 81220068f7 v1.1.13 2020-12-23 11:59:54 -08:00
mrg 80c0bccd70 Merge remote-tracking branch 'private/dev' into dev 2020-12-23 11:59:38 -08:00
mrg c89e156bfe Separate add pins and route pins so pins can block supply router. 2020-12-23 10:49:47 -08:00
mrg 96c75d7c4b Remove outdated unit tests for router 2020-12-23 07:42:36 -08:00
mrg 35c1f2d8a5 Delete temp files 2020-12-23 07:41:04 -08:00
mrg 9ef4cf14c5 Check for drc/lvs aux scripts in test 30 2020-12-23 07:25:24 -08:00
mrg e59333a232 Change options to use route perimeter pins and supply as tree by default. 2020-12-23 07:25:07 -08:00
mrg 1885794016 Only write drc/lvs scripts if drc/lvs is enabled 2020-12-23 07:16:43 -08:00
mrg 94b1e729ab Don't add vias when placing dff array 2020-12-22 17:08:53 -08:00
Hunter Nichols 9edaca0616 Changed tech path in linear regression to use openram_tech option. 2020-12-22 16:45:04 -08:00
mrg 286ac635d6 Escape router changes. 
Rename exit router to escape router.
Perform supply and signal escape routing after channel and other routing.
 2020-12-22 16:35:05 -08:00
mrg 52119fe3b3 Cleanup exit route. Pins are on perimeter mostly. 2020-12-22 15:56:51 -08:00
Hunter Nichols 6eac0530a1 Added words per row to datasheet 2020-12-22 15:00:11 -08:00
mrg ae1c889235 Updates to IO signal router. 
Route signals to perimeter using maze router.
Move IO pins without perimeter pins to M3 using add_io_pin (like add_power_pin).
 2020-12-22 09:39:58 -08:00
mrg 348001b1c8 Supply tree uses signal grid. PEP8 cleanup. 2020-12-21 13:51:50 -08:00
mrg 98250cf115 Copy pins as rects before removing them. 2020-12-21 13:47:05 -08:00
mrg fc91c0da23 Only warn if characterizing. 2020-12-21 12:44:37 -08:00
mrg 6101195b51 Function to remove layout pins. 2020-12-21 12:44:04 -08:00
mrg bcd837205b v1.1.12 2020-12-18 13:05:42 -08:00
mrg e3bc5454f9 Merge remote-tracking branch 'private/dev' into dev 2020-12-18 13:05:11 -08:00
mrg 3c08dfcca5 Enable single pin for vdd/gnd after supply router 2020-12-18 11:09:10 -08:00
mrg 946ad66e7a Make width based on bitcell offsets, not number of columns 2020-12-18 09:22:10 -08:00
mrg 3a3ecb27d2 Merge branch 'dev' into supply_router 2020-12-17 15:53:31 -08:00
Hunter Nichols 732404b330 Added an option that prevents lib.py from generating corners and only uses corners in config file. 2020-12-17 15:32:15 -08:00
mrg 29880a0b5a Write mask and array supply pins on the ends 2020-12-17 15:25:19 -08:00
mrg bad735fd89 Uncomment flatten as it is neeeded for correct extraction 2020-12-17 15:24:44 -08:00
Hunter Nichols 240dc784af Fixed issue with static inputs causing errors. Added corners to linear regression inputs. 2020-12-17 14:54:43 -08:00
Hunter Nichols b760656572 Made process a required feature. Fixed issue with features that have the same max and min 2020-12-17 14:08:45 -08:00
mrg e6ff73dbc1 Move supply pins for wmask and array to edge to avoid channel route congestion 2020-12-17 11:48:08 -08:00
mrg c0ab0af201 Retry routes with expanding detour allowed. 2020-12-17 11:39:17 -08:00
Hunter Nichols 56c4c89720 Adjusted error margin for period in analytical model and added check in model test. 2020-12-17 01:34:53 -08:00
mrg 11384ef926 Improve output messaging of tree router 2020-12-16 16:57:40 -08:00
mrg 2b0f8bf263 Don't exit with error when source is target for maze router 2020-12-16 16:57:29 -08:00
mrg d5ed45dadf Make default router tree router 2020-12-16 16:42:19 -08:00
mrg f55b57033d Route col decoder address with data bits in channel 2020-12-15 16:37:23 -08:00
mrg 878a9cee8a Add channel routes as flat instances to appease Magic extraction. 2020-12-15 16:01:39 -08:00
mrg 0bd169708c v1.1.11 2020-12-15 14:38:54 -08:00
mrg 642c4e1715 Merge remote-tracking branch 'private/dev' into dev 2020-12-15 14:38:29 -08:00
mrg fd118c62e5 Default zom is None not negative. 2020-12-15 13:27:36 -08:00
mrg 9d9f0fddf0 Only do total DRC count. 2020-12-15 13:00:20 -08:00
Hunter Nichols f1f6a1a520 Removed windows end of line characters. 2020-12-15 12:08:31 -08:00
mrg 028d2a2954 v1.1.10 2020-12-15 10:56:45 -08:00
mrg 6714e9fac0 Only run DRC and LVS at SRAM level if not a unit test to reduce run time. 2020-12-15 10:46:55 -08:00
Hunter Nichols 942675051a Added test for linear regression model. 2020-12-14 14:37:53 -08:00
Hunter Nichols 06232dee8f Added leakage and slew data. Added temporary fix to model output format. 2020-12-14 14:32:10 -08:00
mrg 5c4389efa4 PEP8 fixes 2020-12-14 14:18:53 -08:00
mrg da48b8d98c Fix replica column bit index 2020-12-14 14:18:39 -08:00
mrg 2954f13294 Update temp file to be relative 2020-12-14 14:18:18 -08:00
mrg 9a3776e758 Use default zoom for text 2020-12-14 14:18:00 -08:00
Hunter Nichols 25544c3974 Added similar interface to linear regression as elmore 2020-12-14 13:59:31 -08:00
mrg 87493e1e30 Disable pex tests. 2020-12-11 11:47:10 -08:00
mrg 35a6b1d2ee Fix copy gds/sp error with new relative paths 2020-12-11 10:22:35 -08:00
mrg 38bf12771b Make DRC/LVS scripts use relative paths 2020-12-11 10:06:00 -08:00
Hunter Nichols 0adcf8935f Added linear regression model for power. 2020-12-09 15:31:43 -08:00
Hunter Nichols 393a9ca0d8 Data scaling is only dependent on a single file rather than a directory now. 2020-12-09 15:03:04 -08:00
Hunter Nichols fc55cd194d Added model selection option. 2020-12-09 12:54:11 -08:00
mrg d19e4edb98 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-12-09 11:43:55 -08:00
mrg 0a9a946cd1 Make default no magnification to text. PEP8 Cleanup 2020-12-09 11:42:28 -08:00
mrg b5e532940c v1.1.9 2020-12-08 12:05:30 -08:00
mrg 9717794400 Remove extra debug statement 2020-12-08 11:59:14 -08:00
mrg 41d6cb639d Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-12-08 11:56:40 -08:00
mrg ac60c4fe3c Initial maglef flow for sky130 2020-12-08 11:56:23 -08:00
mrg 47cc4cbfca Remove extra debug statement 2020-12-08 11:55:53 -08:00
mrg 971f2ac114 v1.1.8 2020-12-08 10:50:35 -08:00
mrg ebe19abf60 Merge remote-tracking branch 'private/dev' into dev 2020-12-08 10:50:02 -08:00
Arya Reais-Parsi 9eb2f3c0e6 add error message when configuration files are not valid python module names 2020-12-08 10:43:29 -08:00
mrg 6062565973 Add col/row cap modules 2020-12-08 10:34:24 -08:00
mrg 0008de3e59 Change test 14 to odd sizes for use in sky130. 2020-12-08 10:32:23 -08:00
mrg d542b7dd76 Add separate box for pins if it has its own purpose 2020-12-08 10:31:57 -08:00
mrg a2ebaf9f81 Fix typo 2020-12-08 10:31:39 -08:00
mrg 0100ae57a3 Fix mirror with odd number of rows 2020-12-08 10:31:22 -08:00
Hunter Nichols 8a75b83889 Fixed input scaling bugs delay prediction model 2020-12-07 14:36:01 -08:00
Hunter Nichols 77d7e3b1cf Merge branch 'dev' into automated_analytical_model 2020-12-07 14:24:04 -08:00
Hunter Nichols 6e7d1695b5 Cleaned code to remove validation during training. 2020-12-07 14:22:53 -08:00
Hunter Nichols 5f4a2f0231 Added function to get all data and scale vs just a portion 2020-12-07 13:11:04 -08:00
mrg bad1274bdb Use internal name for col/row caps. gds ordered read enabled. 2020-12-03 10:03:47 -08:00
Hunter Nichols dcd20a250a Changed linear regression model to reference data in tech dir vs local ref. 2020-12-02 15:20:50 -08:00
Hunter Nichols d111041385 Refactored analytical model to be it's own module with shared code moved to simulation 2020-12-02 14:06:39 -08:00
Hunter Nichols ce9036af76 Moved model scripts to characterizer dir 2020-12-02 13:25:03 -08:00
mrg 28354bffe0 Add offset to output when printing verbose GDS 2020-12-02 12:03:10 -08:00
mrg 4f28351dcd Add printGDS script to aid debugging things. 2020-12-02 11:52:38 -08:00
mrg 3c115f0ecb LVS using Netgen not Magic 2020-12-02 11:26:00 -08:00
mrg edf3d9557d Purge temp at the start of every run if it exists. 2020-12-02 11:09:40 -08:00
mrg 0250d9add7 v1.1.7 2020-12-01 17:15:03 -08:00
mrg 705d8e3105 Fix wrong via starting layer 2020-12-01 17:12:35 -08:00
mrg f320017b86 Decrease verbosity of script output 2020-12-01 17:12:17 -08:00
mrg 583a70c24e Fix select layer for column mux array 2020-12-01 15:20:44 -08:00
mrg b4cab6ec57 Change mult to 1 always. 2020-12-01 15:20:24 -08:00
mrg c3472b5bc5 Remove old commented code 2020-12-01 13:27:50 -08:00
mrg a31e0dab02 Remove via-to-via path width hack 2020-12-01 13:27:32 -08:00
mrg a5b5f7c22b Change layer away from wordlines 2020-12-01 11:33:55 -08:00
mrg 62bf713913 Only remove files at end of openram 2020-12-01 11:19:37 -08:00
mrg 3829213afe Use and2_dec instead of buf_dec for better wldriver layout 2020-12-01 11:19:12 -08:00
mrg b621c3bdc0 Allow verbose output from scripts with one -v and not unit test 2020-12-01 11:18:27 -08:00
mrg fb4cf0d4d1 Remove env variable from run_lvs script 2020-12-01 09:52:23 -08:00
mrg e817b02ade Fix syntax error. Enable script echo on -v -v. 2020-11-30 09:38:42 -08:00
Tim 'mithro' Ansell 59c6980052 Rework run_script command. 
* Use Python subprocess module.
 * Echo the command output to the console.
 * Print while things are still running.
 2020-11-29 13:03:58 -08:00
Tim 'mithro' Ansell fa5296e621 Improving magic verification shell scripts. 
* Output header at start of script.
 * Output footer at end.
 * Add a bunch more progress report to magic output.
 * Make script return the same exit code as magic.
 2020-11-29 12:19:19 -08:00
mrg 0ccb3487b6 Set default port map 2020-11-24 13:27:11 -08:00
mrg 4e10f6d8a6 Make cell/bitcell custom cell external accessible. 2020-11-24 12:01:00 -08:00
mrg cdcd115cec Fix typos 2020-11-24 10:35:14 -08:00
jcirimel d2bc7340ed finish col cap start row cap 2020-11-24 03:02:55 -08:00
jcirimel f40e5f6dba start of adding additional granularity to 1port col caps 2020-11-23 06:55:47 -08:00
mrg 5ee3f4cc66 Many edits. 
Use internal vdd/gnd names.
Refactor getters in bitcell to base class.
Add BIAS signal type.
 2020-11-22 08:24:47 -08:00
mrg 6e51c3cda0 PEP8 cleanup bitcell_base 2020-11-22 07:11:08 -08:00
mrg 95573c858c Can redefine number of ports in custom_cell_properties 2020-11-21 08:05:49 -08:00
mrg aa03eec943 Fix syntax error. 2020-11-21 07:16:45 -08:00
mrg 4c75bc003e Fix bounding box of replica array to include wordline grounds. 2020-11-21 07:03:59 -08:00
mrg 718c327527 Fix iteration bug with new type 2020-11-20 17:33:15 -08:00
mrg e134e07522 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-11-20 16:57:14 -08:00
mrg f729e9fca7 Fix new replica_bitcell_array refactor with end caps. Remove single port end cap exceptions. 2020-11-20 16:56:07 -08:00
mrg 27a652ac1b Fix bounding box of cap arrays 2020-11-20 16:54:53 -08:00
Hunter Nichols 53e64fb696 Merge branch 'dev' into characterizer_bug_fixes 2020-11-20 11:16:41 -08:00
Hunter Nichols 9fd473ce70 Fixed issue with selection of column address when checking bitline names. 2020-11-20 01:11:08 -08:00
Hunter Nichols b201fa4bca Fixed path measurement in delay 2020-11-19 22:53:38 -08:00
mrg b77f168270 Fix original pin name bug in bitcell too. 2020-11-19 15:12:02 -08:00
mrg 033111a5f3 Default to no hierarchical word lines. 2020-11-19 10:48:35 -08:00
mrg 35c162acbd Use internal pin names in path names for signal traces. 2020-11-19 08:45:09 -08:00
mrg fbed738b4a Merge multiple cell_name fix. 2020-11-18 16:27:28 -08:00
mrg 8c72d3f2e7 PEP8 and small fix 2020-11-18 14:01:25 -08:00
mrg 8507881ea8 Merge branch 's8_single_port' into dev 2020-11-18 13:59:43 -08:00
jcirimel 50a0b88ef8 fix typo 2020-11-18 11:02:40 -08:00
jcirimel 520b496611 check for cell prop names list 2020-11-18 10:47:05 -08:00
mrg 6cfa20731c Consistent naming in example configs 2020-11-18 09:59:38 -08:00
mrg 305b546ad5 PEP8 cleanup 2020-11-17 16:56:00 -08:00
mrg 02c1fac3b8 Remove partial Verilog output 2020-11-17 16:51:08 -08:00