Fixed issue with selection of column address when checking bitline names.

compiler/characterizer/delay.py

@@ -1163,7 +1163,7 @@ class delay(simulation):
 
         # The inverse address needs to share the same bitlines as the probe address as the trimming will remove all other bitlines
         # This is only an issue when there is a column mux and the address maps to different bitlines.
-        column_addr = self.probe_address[:self.sram.col_addr_size] # do not invert this part
+        column_addr = self.get_column_addr() # do not invert this part
         inverse_address = ""
         for c in self.probe_address[self.sram.col_addr_size:]: # invert everything else
             if c=="0":

compiler/characterizer/simulation.py

@@ -403,6 +403,10 @@ class simulation():
         pin_names.append("{0}".format("gnd"))
         return pin_names
 
+    def get_column_addr(self):
+        """Returns column address of probe bit"""
+        return self.probe_address[:self.sram.col_addr_size]
+
     def add_graph_exclusions(self):
         """
         Exclude portions of SRAM from timing graph which are not relevant
@@ -434,11 +438,12 @@ class simulation():
                 debug.warning("Error occurred while determining SEN name. Can cause faults in simulation.")
 
             debug.info(2, "s_en name = {}".format(self.sen_name))
-
+            
+            column_addr = self.get_column_addr()
             bl_name_port, br_name_port = self.get_bl_name(self.graph.all_paths, port)
-            port_pos = -1 - len(str(self.probe_data)) - len(str(port))
+            port_pos = -1 - len(str(column_addr)) - len(str(port))
 
-            if bl_name_port.endswith(str(port) + "_" + str(self.probe_data)):
+            if bl_name_port.endswith(str(port) + "_" + str(column_addr)):
                 self.bl_name = bl_name_port[:port_pos] + "{}" + bl_name_port[port_pos + len(str(port)):]
             elif not bl_name_port[port_pos].isdigit(): # single port SRAM case, bl will not be numbered eg bl_0
                 self.bl_name = bl_name_port
@@ -446,7 +451,7 @@ class simulation():
                 self.bl_name = bl_name_port
                 debug.warning("Error occurred while determining bitline names. Can cause faults in simulation.")
 
-            if br_name_port.endswith(str(port) + "_" + str(self.probe_data)):
+            if br_name_port.endswith(str(port) + "_" + str(column_addr)):
                 self.br_name = br_name_port[:port_pos] + "{}" + br_name_port[port_pos + len(str(port)):]
             elif not br_name_port[port_pos].isdigit(): # single port SRAM case, bl will not be numbered eg bl_0
                 self.br_name = br_name_port

compiler/options.py

@@ -151,7 +151,7 @@ class options(optparse.Values):
     bitcell_array = "bitcell_array"
     bitcell = "bitcell"
     buf_dec = "pbuf"
-    column_mux_array = "single_level_column_mux_array"
+    column_mux_array = "column_mux_array"
     control_logic = "control_logic"
     decoder = "hierarchical_decoder"
     delay_chain = "delay_chain"

compiler/pgates/ptx.py

@@ -549,3 +549,7 @@ class ptx(design.design):
         """
         self.add_graph_edges(graph, port_nets)
 
+    def is_non_inverting(self):
+        """Return input to output polarity for module"""
+        
+        return True