mirror of https://github.com/VLSIDA/OpenRAM.git
Remove extra debug statement
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parent
41d6cb639d
commit
9717794400
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@ -27,8 +27,8 @@ class bitcell_array_1rw_1r_test(openram_test):
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OPTS.num_w_ports = 0
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globals.setup_bitcell()
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debug.info(2, "Testing 4x4 array for cell_1rw_1r")
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a = factory.create(module_type="bitcell_array", cols=4, rows=4)
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debug.info(2, "Testing 2x2 array for cell_2port")
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a = factory.create(module_type="bitcell_array", cols=2, rows=2)
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self.local_check(a)
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globals.end_openram()
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@ -23,6 +23,7 @@ class sram_1bank_2mux_1rw_1r_test(openram_test):
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globals.init_openram(config_file)
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from sram_config import sram_config
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OPTS.route_supplies = False
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OPTS.num_rw_ports = 1
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OPTS.num_r_ports = 1
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OPTS.num_w_ports = 0
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@ -153,7 +153,6 @@ def write_drc_script(cell_name, gds_name, extract, final_verification, output_pa
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from tech import blackbox_cells
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except ImportError:
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blackbox_cells = []
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import pdb; pdb.set_trace()
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for cell_name in blackbox_cells:
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mag_file = OPTS.openram_tech + "maglef_lib/" + cell_name + ".mag"
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debug.check(os.path.isfile(mag_file), "Could not find blackbox cell {}".format(mag_file))
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