mirror of https://github.com/VLSIDA/OpenRAM.git
finish col cap start row cap
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@ -214,9 +214,14 @@ class cell_properties():
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self._col_cap_1port_bitcell = _cell(["bl", "br", "vdd", "gnd"],
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["OUTPUT", "OUTPUT", "POWER", "GROUND"])
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self._col_cap_1port_strap = _cell(["vdd", "gnd"],
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["POWER", "GROUND"])
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self._col_cap_1port_strap_power = _cell(["vdd"],
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["POWER"])
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self._col_cap_1port_strap_ground = _cell(["gnd"],
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["GROUND"])
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self._row_cap_1port_cell = _cell(['vdd]'],
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['POWRER'])
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self._row_cap_1port = _bitcell(["wl", "gnd"],
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["INPUT", "POWER", "GROUND"])
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@ -280,8 +285,16 @@ class cell_properties():
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return self._col_cap_1port_bitcell
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@property
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def col_cap_1port_strap(self):
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return self._col_cap_1port_strap
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def col_cap_1port_strap_power(self):
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return self._col_cap_1port_strap_power
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@property
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def col_cap_1port_strap_ground(self):
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return self._col_cap_1port_strap_ground
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@property
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def row_cap_1port_cell(self):
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return self._row_cap_1port_cell
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@property
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def row_cap_1port(self):
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