Enable single pin for vdd/gnd after supply router

compiler/router/router.py

@@ -1152,7 +1152,20 @@ class router(router_tech):
                                            width=pin.width(),
                                            height=pin.height())
 
+    def get_pin(self, pin_name):
+        """ Return the lowest, leftest pin group """
+        keep_pin = None
+        for index,pg in enumerate(self.pin_groups[pin_name]):
+            for pin in pg.enclosures:
+                if not keep_pin:
+                    keep_pin = pin
+                else:
+                    if pin.lx() <= keep_pin.lx() and pin.by() <= keep_pin.by():
+                        keep_pin = pin
+                        
+        return keep_pin
 
+    
 # FIXME: This should be replaced with vector.snap_to_grid at some point
 def snap_to_grid(offset):
     """

compiler/router/signal_grid.py

@@ -125,7 +125,6 @@ class signal_grid(grid):
                     #else:
                     #    print("Cost bounded")
 
-        debug.warning("Unable to route path. Expand the detour_scale to allow detours.")
         return (None,None)
 
     def expand_dirs(self,curpath):

compiler/sram/sram_base.py

@@ -221,9 +221,9 @@ class sram_base(design, verilog, lef):
 
         # Copy the pins to the top level
         # This will either be used to route or left unconnected.
-        for inst in self.insts:
-            self.copy_power_pins(inst, "vdd")
-            self.copy_power_pins(inst, "gnd")
+        for pin_name in ["vdd", "gnd"]:
+            for inst in self.insts:
+                self.copy_power_pins(inst, pin_name)
 
         if not OPTS.route_supplies:
             # Do not route the power supply (leave as must-connect pins)
@@ -245,6 +245,16 @@ class sram_base(design, verilog, lef):
         rtr=router(grid_stack, self)
         rtr.route()
 
+        vdd_pin = rtr.get_pin("vdd")
+        gnd_pin = rtr.get_pin("gnd")
+        for pin_name, pin in [("vdd", vdd_pin), ("gnd", gnd_pin)]:
+            self.remove_layout_pin(pin_name)
+            self.add_layout_pin(pin_name,
+                                pin.layer,
+                                pin.ll(),
+                                pin.width(),
+                                pin.height())
+
     def compute_bus_sizes(self):
         """ Compute the independent bus widths shared between two and four bank SRAMs """