mirror of https://github.com/VLSIDA/OpenRAM.git
Change options to use route perimeter pins and supply as tree by default.
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@ -92,7 +92,7 @@ class options(optparse.Values):
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# When enabled, layout is not generated (and no DRC or LVS are performed)
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netlist_only = False
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# Whether we should do the final power routing
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route_supplies = False
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route_supplies = "tree"
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# This determines whether LVS and DRC is checked at all.
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check_lvsdrc = False
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# This determines whether LVS and DRC is checked for every submodule.
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@ -141,7 +141,7 @@ class options(optparse.Values):
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# run (doesn't purge on errors, anyhow)
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# Route the input/output pins to the perimeter
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perimeter_pins = False
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perimeter_pins = True
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keep_temp = False
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@ -11,9 +11,6 @@ num_words = 16
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tech_name = OPTS.tech_name
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perimeter_pins = True
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nominal_corner_only = True
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route_supplies = "tree"
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check_lvsdrc = True
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