mirror of https://github.com/VLSIDA/OpenRAM.git
Refactored analytical model to be it's own module with shared code moved to simulation
This commit is contained in:
Hunter Nichols
parent
ce9036af76
commit
d111041385
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@ -11,6 +11,7 @@ import globals
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from globals import OPTS,find_exe,get_tool
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from .lib import *
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from .delay import *
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from .elmore import *
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from .setup_hold import *
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from .functional import *
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from .simulation import *
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@ -52,21 +52,6 @@ class delay(simulation):
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self.create_signal_names()
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self.add_graph_exclusions()
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def create_measurement_names(self):
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""" Create measurement names. The names themselves currently define the type of measurement """
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self.delay_meas_names = ["delay_lh", "delay_hl", "slew_lh", "slew_hl"]
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self.power_meas_names = ["read0_power",
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"read1_power",
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"write0_power",
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"write1_power",
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"disabled_read0_power",
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"disabled_read1_power",
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"disabled_write0_power",
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"disabled_write1_power"]
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# self.voltage_when_names = ["volt_bl", "volt_br"]
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# self.bitline_delay_names = ["delay_bl", "delay_br"]
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def create_measurement_objects(self):
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""" Create the measurements used for read and write ports """
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@ -927,29 +912,11 @@ class delay(simulation):
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"""
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Probe address and data can be set separately to utilize other
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functions in this characterizer besides analyze.
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Netlist reduced for simulation.
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"""
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self.probe_address = probe_address
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self.probe_data = probe_data
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self.bitline_column = self.get_data_bit_column_number(probe_address, probe_data)
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self.wordline_row = self.get_address_row_number(probe_address)
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super().set_probe(probe_address, probe_data)
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self.prepare_netlist()
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def get_data_bit_column_number(self, probe_address, probe_data):
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"""Calculates bitline column number of data bit under test using bit position and mux size"""
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if self.sram.col_addr_size>0:
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col_address = int(probe_address[0:self.sram.col_addr_size], 2)
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else:
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col_address = 0
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bl_column = int(self.sram.words_per_row * probe_data + col_address)
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return bl_column
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def get_address_row_number(self, probe_address):
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"""Calculates wordline row number of data bit under test using address and column mux size"""
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return int(probe_address[self.sram.col_addr_size:], 2)
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def prepare_netlist(self):
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""" Prepare a trimmed netlist and regular netlist. """
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@ -1193,14 +1160,6 @@ class delay(simulation):
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# Add test cycle of read/write port pair. One port could have been used already, but the other has not.
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self.gen_test_cycles_one_port(cur_read_port, cur_write_port)
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def sum_delays(self, delays):
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"""Adds the delays (delay_data objects) so the correct slew is maintained"""
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delay = delays[0]
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for i in range(1, len(delays)):
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delay+=delays[i]
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return delay
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def analytical_delay(self, slews, loads):
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"""
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Return the analytical model results for the SRAM.
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@ -1301,11 +1260,3 @@ class delay(simulation):
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self.stim.gen_pwl("CSB{0}".format(port), self.cycle_times, self.csb_values[port], self.period, self.slew, 0.05)
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if port in self.readwrite_ports:
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self.stim.gen_pwl("WEB{0}".format(port), self.cycle_times, self.web_values[port], self.period, self.slew, 0.05)
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def get_empty_measure_data_dict(self):
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"""Make a dict of lists for each type of delay and power measurement to append results to"""
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measure_names = self.delay_meas_names + self.power_meas_names
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# Create list of dicts. List lengths is # of ports. Each dict maps the measurement names to lists.
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measure_data = [{mname: [] for mname in measure_names} for i in self.all_ports]
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return measure_data
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@ -0,0 +1,105 @@
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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from .simulation import simulation
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from globals import OPTS
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import debug
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class elmore(simulation):
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"""
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Delay model for the SRAM which calculates Elmore delays along the SRAM critical path.
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"""
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def __init__(self, sram, spfile, corner):
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super().__init__(sram, spfile, corner)
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# self.targ_read_ports = []
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# self.targ_write_ports = []
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# self.period = 0
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# if self.write_size:
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# self.num_wmasks = int(math.ceil(self.word_size / self.write_size))
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# else:
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# self.num_wmasks = 0
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#self.set_load_slew(0, 0)
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self.set_corner(corner)
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self.create_signal_names()
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self.add_graph_exclusions()
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def analytical_delay(self, slews, loads):
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"""
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Return the analytical model results for the SRAM.
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"""
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if OPTS.num_rw_ports > 1 or OPTS.num_w_ports > 0 and OPTS.num_r_ports > 0:
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debug.warning("In analytical mode, all ports have the timing of the first read port.")
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# Probe set to 0th bit, does not matter for analytical delay.
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self.set_probe('0' * self.addr_size, 0)
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self.create_graph()
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self.set_internal_spice_names()
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self.create_measurement_names()
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port = self.read_ports[0]
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self.graph.get_all_paths('{}{}'.format("clk", port),
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'{}{}_{}'.format(self.dout_name, port, self.probe_data))
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# Select the path with the bitline (bl)
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bl_name, br_name = self.get_bl_name(self.graph.all_paths, port)
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bl_path = [path for path in self.graph.all_paths if bl_name in path][0]
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# Set delay/power for slews and loads
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port_data = self.get_empty_measure_data_dict()
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power = self.analytical_power(slews, loads)
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debug.info(1, 'Slew, Load, Delay(ns), Slew(ns)')
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max_delay = 0.0
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for slew in slews:
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for load in loads:
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# Calculate delay based on slew and load
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path_delays = self.graph.get_timing(bl_path, self.corner, slew, load)
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total_delay = self.sum_delays(path_delays)
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max_delay = max(max_delay, total_delay.delay)
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debug.info(1,
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'{}, {}, {}, {}'.format(slew,
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load,
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total_delay.delay / 1e3,
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total_delay.slew / 1e3))
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# Delay is only calculated on a single port and replicated for now.
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for port in self.all_ports:
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for mname in self.delay_meas_names + self.power_meas_names:
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if "power" in mname:
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port_data[port][mname].append(power.dynamic)
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elif "delay" in mname and port in self.read_ports:
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port_data[port][mname].append(total_delay.delay / 1e3)
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elif "slew" in mname and port in self.read_ports:
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port_data[port][mname].append(total_delay.slew / 1e3)
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else:
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debug.error("Measurement name not recognized: {}".format(mname), 1)
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# Estimate the period as double the delay with margin
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period_margin = 0.1
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sram_data = {"min_period": (max_delay / 1e3) * 2 * period_margin,
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"leakage_power": power.leakage}
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debug.info(2, "SRAM Data:\n{}".format(sram_data))
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debug.info(2, "Port Data:\n{}".format(port_data))
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return (sram_data, port_data)
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def analytical_power(self, slews, loads):
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"""Get the dynamic and leakage power from the SRAM"""
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# slews unused, only last load is used
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load = loads[-1]
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power = self.sram.analytical_power(self.corner, load)
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# convert from nW to mW
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power.dynamic /= 1e6
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power.leakage /= 1e6
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debug.info(1, "Dynamic Power: {0} mW".format(power.dynamic))
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debug.info(1, "Leakage Power: {0} mW".format(power.leakage))
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return power
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@ -11,6 +11,7 @@ import math
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import datetime
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from .setup_hold import *
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from .delay import *
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from .elmore import *
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from .charutils import *
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import tech
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import numpy as np
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@ -582,11 +583,12 @@ class lib:
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def compute_delay(self):
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"""Compute SRAM delays for current corner"""
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self.d = delay(self.sram, self.sp_file, self.corner)
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if self.use_model:
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self.d = elmore(self.sram, self.sp_file, self.corner)
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char_results = self.d.analytical_delay(self.slews,self.loads)
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self.char_sram_results, self.char_port_results = char_results
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else:
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self.d = delay(self.sram, self.sp_file, self.corner)
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if (self.sram.num_spare_rows == 0):
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probe_address = "1" * self.sram.addr_size
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else:
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@ -39,6 +39,21 @@ class simulation():
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else:
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self.num_wmasks = 0
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def create_measurement_names(self):
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""" Create measurement names. The names themselves currently define the type of measurement """
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self.delay_meas_names = ["delay_lh", "delay_hl", "slew_lh", "slew_hl"]
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self.power_meas_names = ["read0_power",
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"read1_power",
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"write0_power",
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"write1_power",
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"disabled_read0_power",
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"disabled_read1_power",
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"disabled_write0_power",
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"disabled_write1_power"]
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# self.voltage_when_names = ["volt_bl", "volt_br"]
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# self.bitline_delay_names = ["delay_bl", "delay_br"]
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def set_corner(self, corner):
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""" Set the corner values """
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self.corner = corner
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@ -92,6 +107,32 @@ class simulation():
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self.cycle_comments = []
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self.fn_cycle_comments = []
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def set_probe(self, probe_address, probe_data):
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"""
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Probe address and data can be set separately to utilize other
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functions in this characterizer besides analyze.
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"""
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self.probe_address = probe_address
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self.probe_data = probe_data
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self.bitline_column = self.get_data_bit_column_number(probe_address, probe_data)
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self.wordline_row = self.get_address_row_number(probe_address)
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def get_data_bit_column_number(self, probe_address, probe_data):
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"""Calculates bitline column number of data bit under test using bit position and mux size"""
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if self.sram.col_addr_size>0:
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col_address = int(probe_address[0:self.sram.col_addr_size], 2)
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else:
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col_address = 0
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bl_column = int(self.sram.words_per_row * probe_data + col_address)
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return bl_column
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def get_address_row_number(self, probe_address):
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"""Calculates wordline row number of data bit under test using address and column mux size"""
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return int(probe_address[self.sram.col_addr_size:], 2)
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def add_control_one_port(self, port, op):
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"""Appends control signals for operation to a given port"""
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# Determine values to write to port
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@ -539,6 +580,21 @@ class simulation():
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for i in range(len(bl_names)):
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bl_names[i] = bl_names[i].split('.')[-1]
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return bl_names[0], bl_names[1]
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def get_empty_measure_data_dict(self):
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"""Make a dict of lists for each type of delay and power measurement to append results to"""
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measure_names = self.delay_meas_names + self.power_meas_names
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# Create list of dicts. List lengths is # of ports. Each dict maps the measurement names to lists.
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measure_data = [{mname: [] for mname in measure_names} for i in self.all_ports]
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return measure_data
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def sum_delays(self, delays):
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"""Adds the delays (delay_data objects) so the correct slew is maintained"""
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delay = delays[0]
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for i in range(1, len(delays)):
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delay+=delays[i]
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return delay
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