mirror of https://github.com/VLSIDA/OpenRAM.git
Only unblock source/target instead of all components for cleaner routes
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parent
7eb1e2f2d1
commit
66ff1fe990
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@ -90,6 +90,7 @@ class grid:
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else:
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self.add_map(n)
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self.map[n].source=True
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self.map[n].blocked=False
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self.source.add(n)
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def clear_target(self):
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@ -104,8 +105,9 @@ class grid:
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else:
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self.add_map(n)
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self.map[n].target=True
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self.map[n].blocked=False
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self.target.add(n)
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def add_source(self, track_list):
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debug.info(3, "Adding source list={0}".format(str(track_list)))
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for n in track_list:
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@ -355,7 +355,7 @@ class router(router_tech):
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# Start fresh. Not the best for run-time, but simpler.
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self.clear_blockages()
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# This adds the initial blockges of the design
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#print("BLOCKING:", self.blocked_grids)
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# print("BLOCKING:", self.blocked_grids)
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self.set_blockages(self.blocked_grids, True)
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# Block all of the supply rails
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@ -382,8 +382,9 @@ class router(router_tech):
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# Don't mark the other components as targets since we want to route
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# directly to a rail, but unblock all the source components so we can
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# route over them
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blockage_grids = {y for x in self.pin_groups[pin_name] for y in x.grids}
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self.set_blockages(blockage_grids, False)
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# 1/6/21: This would cause things that looked like loops in the supply tree router
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# blockage_grids = {y for x in self.pin_groups[pin_name] for y in x.grids}
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# self.set_blockages(blockage_grids, False)
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def convert_shape_to_units(self, shape):
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"""
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@ -144,15 +144,13 @@ class supply_tree_router(router):
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# Marks all pin components except index as target
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self.add_pin_component_target(pin_name, dest_idx)
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# Actually run the A* router
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if self.run_router(detour_scale=detour_scale):
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return
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self.write_debug_gds("debug_route.gds", True)
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def add_io_pin(self, instance, pin_name, new_name=""):
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"""
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Add a signle input or output pin up to metal 3.
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