Escape router changes.

Rename exit router to escape router.
Perform supply and signal escape routing after channel and other routing.

compiler/base/hierarchy_layout.py

@@ -477,6 +477,7 @@ class layout():
         """
         Remove the old pin and replace with a new one
         """
+        import pdb; pdb.set_trace()
         self.remove_layout_pin(text)
         self.add_layout_pin(text=text,
                             layer=pin.layer,

compiler/router/signal_escape_router.py

@@ -11,7 +11,8 @@ from router import router
 from datetime import datetime
 from supply_grid import supply_grid
 
-class signal_exit_router(router):
+
+class signal_escape_router(router):
     """
     A router that routes signals to perimeter and makes pins.
     """
@@ -31,7 +32,7 @@ class signal_exit_router(router):
         debug.info(1,"Size: {0} x {1}".format(size.x, size.y))
         self.rg = supply_grid(self.ll, self.ur, self.track_width)
 
-    def exit_route(self, pin_list):
+    def escape_route(self, pin_list):
         """
         Takes a list of tuples (name, side) and routes them. After routing,
         it removes the old pin and places a new one on the perimeter.

compiler/router/supply_tree_router.py

@@ -14,6 +14,7 @@ from scipy.sparse import csr_matrix
 from scipy.sparse.csgraph import minimum_spanning_tree
 from signal_grid import signal_grid
 
+
 class supply_tree_router(router):
     """
     A router class to read an obstruction map from a gds and

compiler/sram/sram_1bank.py

@@ -8,7 +8,8 @@
 from vector import vector
 from sram_base import sram_base
 from contact import m2_via
-import channel_route
+from channel_route import channel_route
+from signal_escape_router import signal_escape_router as router
 
 
 class sram_1bank(sram_base):
@@ -105,7 +106,7 @@ class sram_1bank(sram_base):
         # We need to temporarily add some pins for the x offsets
         # but we'll remove them so that they have the right y
         # offsets after the DFF placement.
-        self.add_layout_pins(exit_route=False)
+        self.add_layout_pins(escape_route=False)
         self.route_dffs(add_routes=False)
         self.remove_layout_pins()
         
@@ -244,7 +245,7 @@ class sram_1bank(sram_base):
             self.data_pos[port] = vector(x_offset, y_offset)
             self.spare_wen_pos[port] = vector(x_offset, y_offset)
 
-    def add_layout_pins(self, exit_route=True):
+    def add_layout_pins(self, escape_route=True):
         """
         Add the top-level pins for a single bank SRAM with control.
         """
@@ -311,18 +312,13 @@ class sram_1bank(sram_base):
                                     "spare_wen{0}[{1}]".format(port, bit))
                     all_pins.append(("spare_wen{0}[{1}]".format(port, bit), bottom_or_top))
 
-        if exit_route:
-            from signal_exit_router import signal_exit_router as router
+        if escape_route:
             rtr=router(self.m3_stack, self)
-            rtr.exit_route(all_pins)
+            rtr.escape_route(all_pins)
 
     def route_layout(self):
         """ Route a single bank SRAM """
 
-        self.route_supplies()
-
-        self.add_layout_pins()
-
         self.route_clk()
 
         self.route_control_logic()
@@ -331,6 +327,9 @@ class sram_1bank(sram_base):
 
         self.route_dffs()
 
+        self.route_supplies()
+
+        self.add_layout_pins()
         
     def route_dffs(self, add_routes=True):
 
@@ -384,10 +383,10 @@ class sram_1bank(sram_base):
             if port == 0:
                 offset = vector(self.control_logic_insts[port].rx() + self.dff.width,
                                 - self.data_bus_size[port] + 2 * self.m3_pitch)
-                cr = channel_route.channel_route(netlist=route_map,
-                                                 offset=offset,
-                                                 layer_stack=layer_stack,
-                                                 parent=self)
+                cr = channel_route(netlist=route_map,
+                                   offset=offset,
+                                   layer_stack=layer_stack,
+                                   parent=self)
                 if add_routes:
                     # This causes problem in magic since it sometimes cannot extract connectivity of isntances
                     # with no active devices.
@@ -399,10 +398,10 @@ class sram_1bank(sram_base):
             else:
                 offset = vector(0,
                                 self.bank.height + self.m3_pitch)
-                cr = channel_route.channel_route(netlist=route_map,
-                                                 offset=offset,
-                                                 layer_stack=layer_stack,
-                                                 parent=self)
+                cr = channel_route(netlist=route_map,
+                                   offset=offset,
+                                   layer_stack=layer_stack,
+                                   parent=self)
                 if add_routes:
                     # This causes problem in magic since it sometimes cannot extract connectivity of isntances
                     # with no active devices.