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Escape route to any side

This commit is contained in:
mrg 2021-01-06 09:40:32 -08:00
parent b22d2a76a7
commit ec6f0f1873
2 changed files with 15 additions and 28 deletions
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21
compiler/router/signal_escape_router.py
View File

@ -9,7 +9,7 @@ import debug
from globals import print_time
from router import router
from datetime import datetime
from supply_grid import supply_grid
from signal_grid import signal_grid
class signal_escape_router(router):
@ -30,22 +30,15 @@ class signal_escape_router(router):
"""
size = self.ur - self.ll
debug.info(1,"Size: {0} x {1}".format(size.x, size.y))
self.rg = supply_grid(self.ll, self.ur, self.track_width)
self.rg = signal_grid(self.ll, self.ur, self.track_width)
def escape_route(self, pin_list):
def escape_route(self, pin_names):
"""
Takes a list of tuples (name, side) and routes them. After routing,
it removes the old pin and places a new one on the perimeter.
"""
pin_names = [x[0] for x in pin_list]
# Clear the pins if we have previously routed
if (hasattr(self,'rg')):
self.clear_pins()
else:
self.create_routing_grid()
self.create_routing_grid()
# Get the pin shapes
start_time = datetime.now()
self.find_pins_and_blockages(pin_names)
print_time("Finding pins and blockages",datetime.now(), start_time, 3)
@ -53,8 +46,8 @@ class signal_escape_router(router):
# Route the supply pins to the supply rails
# Route vdd first since we want it to be shorter
start_time = datetime.now()
for pin_name, side in pin_list:
self.route_signal(pin_name, side)
for pin_name in pin_names:
self.route_signal(pin_name)
print_time("Maze routing pins",datetime.now(), start_time, 3)
@ -62,7 +55,7 @@ class signal_escape_router(router):
return True
def route_signal(self, pin_name, side):
def route_signal(self, pin_name, side="all"):
for detour_scale in [5 * pow(2, x) for x in range(5)]:
debug.info(1, "Escape routing {0} with scale {1}".format(pin_name, detour_scale))

22
compiler/sram/sram_1bank.py
View File

@ -254,43 +254,37 @@ class sram_1bank(sram_base):
# List of pin to new pin name
pins_to_route = []
for port in self.all_ports:
# Depending on the port, use the bottom/top or left/right sides
# Port 0 is left/bottom
# Port 1 is right/top
bottom_or_top = "bottom" if port==0 else "top"
left_or_right = "left" if port==0 else "right"
# Connect the control pins as inputs
for signal in self.control_logic_inputs[port]:
if signal.startswith("rbl"):
continue
if signal=="clk":
pins_to_route.append(("{0}{1}".format(signal, port), bottom_or_top))
pins_to_route.append("{0}{1}".format(signal, port))
else:
pins_to_route.append(("{0}{1}".format(signal, port), left_or_right))
pins_to_route.append("{0}{1}".format(signal, port))
if port in self.write_ports:
for bit in range(self.word_size + self.num_spare_cols):
pins_to_route.append(("din{0}[{1}]".format(port, bit), bottom_or_top))
pins_to_route.append("din{0}[{1}]".format(port, bit))
if port in self.readwrite_ports or port in self.read_ports:
for bit in range(self.word_size + self.num_spare_cols):
pins_to_route.append(("dout{0}[{1}]".format(port, bit), bottom_or_top))
pins_to_route.append("dout{0}[{1}]".format(port, bit))
for bit in range(self.col_addr_size):
pins_to_route.append(("addr{0}[{1}]".format(port, bit), bottom_or_top))
pins_to_route.append("addr{0}[{1}]".format(port, bit))
for bit in range(self.row_addr_size):
pins_to_route.append(("addr{0}[{1}]".format(port, bit + self.col_addr_size), left_or_right))
pins_to_route.append("addr{0}[{1}]".format(port, bit + self.col_addr_size))
if port in self.write_ports:
if self.write_size:
for bit in range(self.num_wmasks):
pins_to_route.append(("wmask{0}[{1}]".format(port, bit), bottom_or_top))
pins_to_route.append("wmask{0}[{1}]".format(port, bit))
if port in self.write_ports:
for bit in range(self.num_spare_cols):
pins_to_route.append(("spare_wen{0}[{1}]".format(port, bit), bottom_or_top))
pins_to_route.append("spare_wen{0}[{1}]".format(port, bit))
rtr=router(self.m3_stack, self)
rtr.escape_route(pins_to_route)