luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Disable pex tests.

This commit is contained in:
mrg 2020-12-11 11:47:10 -08:00
parent 35a6b1d2ee
commit 87493e1e30
2 changed files with 19 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
compiler/tests/26_hspice_pex_pinv_test.py
View File

@ -17,6 +17,7 @@ from globals import OPTS
import debug
@unittest.skip("SKIPPING 26_hspice_pex_pinv_test")
class hspice_pex_pinv_test(openram_test):
def runTest(self):
@ -39,10 +40,10 @@ class hspice_pex_pinv_test(openram_test):
OPTS.keep_temp = True
debug.info(2, "Checking 1x size inverter")
tx = pinv.pinv(name="pinv", size=1)
tempgds = "{0}{1}.gds".format(OPTS.openram_temp, tx.name)
tx.gds_write(tempgds)
tempsp = "{0}{1}.sp".format(OPTS.openram_temp, tx.name)
tx.sp_write(tempsp)
tempgds = "{}.gds".format(tx.name)
tx.gds_write("{0}{1}".format(OPTS.openram_temp, tempgds))
tempsp = "{}.sp".format(tx.name)
tx.sp_write("{0}{1}".format(OPTS.openram_temp, tempsp))
# make sure that the library simulation is successful
sp_delay = self.simulate_delay(test_module=tempsp,
@ -74,7 +75,7 @@ class hspice_pex_pinv_test(openram_test):
def simulate_delay(self, test_module, top_level_name):
from charutils import parse_spice_list
# setup simulation
sim_file = OPTS.openram_temp + "stim.sp"
sim_file = "stim.sp"
log_file_name = "timing"
test_sim = self.write_simulation(sim_file, test_module, top_level_name)
test_sim.run_sim("stim.sp")
@ -86,7 +87,7 @@ class hspice_pex_pinv_test(openram_test):
import tech
from characterizer import measurements, stimuli
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
sim_file = open(sim_file, "w")
sim_file = open(OPTS.openram_temp + sim_file, "w")
simulation = stimuli(sim_file, corner)
# library files

18
compiler/tests/26_ngspice_pex_pinv_test.py
View File

@ -16,7 +16,7 @@ import globals
from globals import OPTS
import debug
@unittest.skip("SKIPPING 26_ngspice_pex_pinv_test")
class ngspice_pex_pinv_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
@ -37,10 +37,10 @@ class ngspice_pex_pinv_test(openram_test):
OPTS.keep_temp = True # force set keep to true to save the sp file
debug.info(2, "Checking 1x size inverter")
tx = pinv.pinv(name="pinv", size=1)
tempgds = "{0}{1}.gds".format(OPTS.openram_temp, tx.name)
tx.gds_write(tempgds)
tempsp = "{0}{1}.sp".format(OPTS.openram_temp, tx.name)
tx.sp_write(tempsp)
tempgds = "{}.gds".format(tx.name)
tx.gds_write("{0}{1}".format(OPTS.openram_temp, tempgds))
tempsp = "{}.sp".format(tx.name)
tx.sp_write("{0}{1}".format(OPTS.openram_temp, tempsp))
# make sure that the library simulation is successful
sp_delay = self.simulate_delay(test_module=tempsp,
@ -72,12 +72,17 @@ class ngspice_pex_pinv_test(openram_test):
def simulate_delay(self, test_module, top_level_name):
from charutils import parse_spice_list
cwd = os.getcwd()
os.chdir(OPTS.openram_temp)
# setup simulation
sim_file = OPTS.openram_temp + "stim.sp"
sim_file = "stim.sp"
log_file_name = "timing"
test_sim = self.write_simulation(sim_file, test_module, top_level_name)
test_sim.run_sim("stim.sp")
delay = parse_spice_list(log_file_name, "pinv_delay")
os.chdir(cwd)
return delay
def write_simulation(self, sim_file, cir_file, top_module_name):
@ -89,6 +94,7 @@ class ngspice_pex_pinv_test(openram_test):
simulation = stimuli(sim_file, corner)
# library files
import pdb; pdb.set_trace()
simulation.write_include(cir_file)
# supply voltages