mirror of https://github.com/VLSIDA/OpenRAM.git
Merge remote-tracking branch 'private/dev' into dev
This commit is contained in:
mrg
commit
e3bc5454f9
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@ -236,7 +236,7 @@ class layout():
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# This is commented out for runtime reasons
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# debug.info(4, "instance list: " + ",".join(x.name for x in self.insts))
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return self.insts[-1]
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def get_inst(self, name):
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""" Retrieve an instance by name """
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for inst in self.insts:
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@ -244,6 +244,19 @@ class layout():
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return inst
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return None
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def add_flat_inst(self, name, mod, offset=[0, 0]):
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""" Copies all of the items in instance into this module """
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for item in mod.objs:
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item.offset += offset
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self.objs.append(item)
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for item in mod.insts:
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item.offset += offset
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self.insts.append(item)
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debug.check(len(item.mod.pins) == 0, "Cannot add flat instance with subinstances.")
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self.connect_inst([])
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debug.info(3, "adding flat instance {}".format(name))
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return None
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def add_rect(self, layer, offset, width=None, height=None):
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"""
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Adds a rectangle on a given layer,offset with width and height
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@ -1078,18 +1091,24 @@ class layout():
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"""
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import channel_route
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cr = channel_route.channel_route(netlist, offset, layer_stack, directions, vertical=True, parent=self)
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self.add_inst(cr.name, cr)
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self.connect_inst([])
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# This causes problem in magic since it sometimes cannot extract connectivity of isntances
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# with no active devices.
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# self.add_inst(cr.name, cr)
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# self.connect_inst([])
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self.add_flat_inst(cr.name, cr)
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def create_horizontal_channel_route(self, netlist, offset, layer_stack, directions=None):
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"""
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Wrapper to create a horizontal channel route
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"""
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import channel_route
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cr = channel_route.channel_route(netlist, offset, layer_stack, directions, vertical=False, parent=self)
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self.add_inst(cr.name, cr)
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self.connect_inst([])
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# This causes problem in magic since it sometimes cannot extract connectivity of isntances
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# with no active devices.
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# self.add_inst(cr.name, cr)
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# self.connect_inst([])
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self.add_flat_inst(cr.name, cr)
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def add_boundary(self, ll=vector(0, 0), ur=None):
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""" Add boundary for debugging dimensions """
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if OPTS.netlist_only:
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@ -1362,8 +1362,9 @@ class delay(simulation):
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else:
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debug.error("Measurement name not recognized: {}".format(mname), 1)
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# Estimate the period as double the delay with margin
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period_margin = 0.1
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# Margin for error in period. Calculated by averaging required margin for a small and large
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# memory. FIXME: margin is quite large, should be looked into.
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period_margin = 1.85
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sram_data = {"min_period": (max_delay / 1e3) * 2 * period_margin,
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"leakage_power": power.leakage}
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@ -11,7 +11,7 @@ import math
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from sram_factory import factory
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from vector import vector
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from globals import OPTS
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from tech import layer
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class write_mask_and_array(design.design):
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"""
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@ -95,9 +95,9 @@ class write_mask_and_array(design.design):
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if not self.offsets:
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self.offsets = []
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for i in range(self.columns):
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self.offsets.append(i * self.driver_spacing)
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self.offsets.append((i + self.write_size - 1) * self.driver_spacing)
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self.width = self.offsets[-1] + self.driver_spacing
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self.width = self.offsets[-1] + self.bitcell.width
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self.height = self.and2.height
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write_bits = self.columns / self.num_wmasks
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@ -138,12 +138,13 @@ class write_mask_and_array(design.design):
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self.add_via_stack_center(from_layer=en_pin.layer,
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to_layer="m3",
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offset=en_pos)
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for supply in ["gnd", "vdd"]:
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supply_pin=self.and2_insts[i].get_pin(supply)
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self.add_power_pin(supply, supply_pin.center(), start_layer=supply_pin.layer)
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for supply in ["gnd", "vdd"]:
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supply_pin_left = self.and2_insts[0].get_pin(supply)
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supply_pin_right = self.and2_insts[self.num_wmasks - 1].get_pin(supply)
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self.add_path(supply_pin_left.layer, [supply_pin_left.lc(), supply_pin_right.rc()])
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supply_pin = self.and2_insts[0].get_pin(supply)
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supply_pin_yoffset = supply_pin.cy()
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left_loc = vector(0, supply_pin_yoffset)
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right_loc = vector(self.width, supply_pin_yoffset)
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self.add_path(supply_pin.layer, [left_loc, right_loc])
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self.add_power_pin(supply, left_loc, start_layer=supply_pin.layer)
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self.add_power_pin(supply, right_loc, start_layer=supply_pin.layer)
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@ -865,7 +865,7 @@ class router(router_tech):
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debug.check(index<self.num_pin_components(pin_name),"Pin component index too large.")
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pin_in_tracks = self.pin_groups[pin_name][index].grids
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debug.info(2, "Set target: " + str(pin_name) + " " + str(pin_in_tracks))
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debug.info(3, "Set target: " + str(pin_name) + " " + str(pin_in_tracks))
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self.rg.add_target(pin_in_tracks)
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def add_pin_component_target_except(self, pin_name, index):
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@ -1000,8 +1000,7 @@ class router(router_tech):
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# Double check source and taget are not same node, if so, we are done!
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for k, v in self.rg.map.items():
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if v.source and v.target:
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debug.error("Grid cell is source and target! {}".format(k))
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return False
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return True
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# returns the path in tracks
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(path, cost) = self.rg.route(detour_scale)
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@ -1013,12 +1012,9 @@ class router(router_tech):
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path_set = grid_utils.flatten_set(path)
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self.path_blockages.append(path_set)
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return True
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else:
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self.write_debug_gds("failed_route.gds")
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# clean up so we can try a reroute
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self.rg.reinit()
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return False
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return True
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def annotate_pin_and_tracks(self, pin, tracks):
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""""
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@ -1156,7 +1152,20 @@ class router(router_tech):
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width=pin.width(),
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height=pin.height())
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def get_pin(self, pin_name):
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""" Return the lowest, leftest pin group """
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keep_pin = None
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for index,pg in enumerate(self.pin_groups[pin_name]):
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for pin in pg.enclosures:
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if not keep_pin:
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keep_pin = pin
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else:
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if pin.lx() <= keep_pin.lx() and pin.by() <= keep_pin.by():
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keep_pin = pin
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return keep_pin
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# FIXME: This should be replaced with vector.snap_to_grid at some point
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def snap_to_grid(offset):
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"""
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@ -125,7 +125,6 @@ class signal_grid(grid):
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#else:
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# print("Cost bounded")
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debug.warning("Unable to route path. Expand the detour_scale to allow detours.")
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return (None,None)
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def expand_dirs(self,curpath):
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@ -5,20 +5,14 @@
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#(acting for and on behalf of Oklahoma State University)
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#All rights reserved.
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#
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import gdsMill
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import tech
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import math
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import debug
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from globals import OPTS,print_time
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from contact import contact
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from pin_group import pin_group
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from pin_layout import pin_layout
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from vector3d import vector3d
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from globals import print_time
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from router import router
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from direction import direction
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from datetime import datetime
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import grid
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import grid_utils
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from scipy.sparse import csr_matrix
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from scipy.sparse.csgraph import minimum_spanning_tree
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class supply_tree_router(router):
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"""
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@ -36,7 +30,6 @@ class supply_tree_router(router):
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router.__init__(self, layers, design, gds_filename, self.rail_track_width)
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def create_routing_grid(self):
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"""
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Create a sprase routing grid with A* expansion functions.
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@ -133,7 +126,6 @@ class supply_tree_router(router):
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self.set_blockages(blockage_grids,False)
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def route_pins(self, pin_name):
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"""
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This will route each of the remaining pin components to the other pins.
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@ -141,15 +133,46 @@ class supply_tree_router(router):
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"""
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remaining_components = sum(not x.is_routed() for x in self.pin_groups[pin_name])
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debug.info(1,"Maze routing {0} with {1} pin components to connect.".format(pin_name,
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remaining_components))
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debug.info(1,"Routing {0} with {1} pin components to connect.".format(pin_name,
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remaining_components))
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for index,pg in enumerate(self.pin_groups[pin_name]):
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if pg.is_routed():
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continue
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# Create full graph
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pin_size = len(self.pin_groups[pin_name])
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adj_matrix = [[0] * pin_size for i in range(pin_size)]
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debug.info(1,"Routing component {0} {1}".format(pin_name, index))
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for index1,pg1 in enumerate(self.pin_groups[pin_name]):
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for index2,pg2 in enumerate(self.pin_groups[pin_name]):
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if index1>=index2:
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continue
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dist = int(grid_utils.distance_set(list(pg1.grids)[0], pg2.grids))
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adj_matrix[index1][index2] = dist
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# Find MST
|
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X = csr_matrix(adj_matrix)
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Tcsr = minimum_spanning_tree(X)
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mst = Tcsr.toarray().astype(int)
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connections = []
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for x in range(pin_size):
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for y in range(pin_size):
|
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if x >= y:
|
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continue
|
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if mst[x][y]>0:
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connections.append((x, y))
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debug.info(1,"MST has {0} segments.".format(len(connections)))
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# Route MST components
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for (src, dest) in connections:
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self.route_signal(pin_name, src, dest)
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#self.write_debug_gds("final.gds", True)
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#return
|
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|
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def route_signal(self, pin_name, src_idx, dest_idx):
|
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|
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for detour_scale in [5 * pow(2, x) for x in range(5)]:
|
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debug.info(2, "Routing {0} to {1} with scale {2}".format(src_idx, dest_idx, detour_scale))
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|
||||
# Clear everything in the routing grid.
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self.rg.reinit()
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||||
|
||||
|
|
@ -159,35 +182,16 @@ class supply_tree_router(router):
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|
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# Add the single component of the pin as the source
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||||
# which unmarks it as a blockage too
|
||||
self.add_pin_component_source(pin_name,index)
|
||||
self.add_pin_component_source(pin_name, src_idx)
|
||||
|
||||
# Marks all pin components except index as target
|
||||
self.add_pin_component_target_except(pin_name,index)
|
||||
# Add the prevous paths as a target too
|
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self.add_path_target(self.paths)
|
||||
|
||||
print("SOURCE: ")
|
||||
for k,v in self.rg.map.items():
|
||||
if v.source:
|
||||
print(k)
|
||||
|
||||
print("TARGET: ")
|
||||
for k,v in self.rg.map.items():
|
||||
if v.target:
|
||||
print(k)
|
||||
|
||||
import pdb; pdb.set_trace()
|
||||
if index==1:
|
||||
self.write_debug_gds("debug{}.gds".format(pin_name),False)
|
||||
|
||||
self.add_pin_component_target(pin_name, dest_idx)
|
||||
|
||||
# Actually run the A* router
|
||||
if not self.run_router(detour_scale=5):
|
||||
self.write_debug_gds("debug_route.gds",True)
|
||||
|
||||
#if index==3 and pin_name=="vdd":
|
||||
# self.write_debug_gds("route.gds",False)
|
||||
|
||||
if self.run_router(detour_scale=detour_scale):
|
||||
return
|
||||
|
||||
self.write_debug_gds("debug_route.gds", True)
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -402,25 +402,6 @@ class sram_1bank(sram_base):
|
|||
bank_pins = [self.bank_inst.get_pin(x) for x in bank_names]
|
||||
route_map.extend(list(zip(bank_pins, dff_pins)))
|
||||
|
||||
if port == 0:
|
||||
offset = vector(self.control_logic_insts[port].rx() + self.dff.width,
|
||||
- self.data_bus_size[port] + 2 * self.m1_pitch)
|
||||
else:
|
||||
offset = vector(0,
|
||||
self.bank.height + 2 * self.m1_space)
|
||||
|
||||
cr = channel_route.channel_route(netlist=route_map,
|
||||
offset=offset,
|
||||
layer_stack=self.m1_stack,
|
||||
parent=self)
|
||||
if add_routes:
|
||||
self.add_inst(cr.name, cr)
|
||||
self.connect_inst([])
|
||||
else:
|
||||
self.col_addr_bus_size[port] = cr.height
|
||||
|
||||
route_map = []
|
||||
|
||||
# wmask dff
|
||||
if self.num_wmasks > 0 and port in self.write_ports:
|
||||
dff_names = ["dout_{}".format(x) for x in range(self.num_wmasks)]
|
||||
|
|
@ -464,26 +445,32 @@ class sram_1bank(sram_base):
|
|||
|
||||
if port == 0:
|
||||
offset = vector(self.control_logic_insts[port].rx() + self.dff.width,
|
||||
- self.data_bus_size[port] + 2 * self.m1_pitch)
|
||||
- self.data_bus_size[port] + 2 * self.m3_pitch)
|
||||
cr = channel_route.channel_route(netlist=route_map,
|
||||
offset=offset,
|
||||
layer_stack=layer_stack,
|
||||
parent=self)
|
||||
if add_routes:
|
||||
self.add_inst(cr.name, cr)
|
||||
self.connect_inst([])
|
||||
# This causes problem in magic since it sometimes cannot extract connectivity of isntances
|
||||
# with no active devices.
|
||||
# self.add_inst(cr.name, cr)
|
||||
# self.connect_inst([])
|
||||
self.add_flat_inst(cr.name, cr)
|
||||
else:
|
||||
self.data_bus_size[port] = max(cr.height, self.col_addr_bus_size[port]) + self.data_bus_gap
|
||||
else:
|
||||
offset = vector(0,
|
||||
self.bank.height + 2 * self.m1_space)
|
||||
self.bank.height + self.m3_pitch)
|
||||
cr = channel_route.channel_route(netlist=route_map,
|
||||
offset=offset,
|
||||
layer_stack=layer_stack,
|
||||
parent=self)
|
||||
if add_routes:
|
||||
self.add_inst(cr.name, cr)
|
||||
self.connect_inst([])
|
||||
# This causes problem in magic since it sometimes cannot extract connectivity of isntances
|
||||
# with no active devices.
|
||||
# self.add_inst(cr.name, cr)
|
||||
# self.connect_inst([])
|
||||
self.add_flat_inst(cr.name, cr)
|
||||
else:
|
||||
self.data_bus_size[port] = max(cr.height, self.col_addr_bus_size[port]) + self.data_bus_gap
|
||||
|
||||
|
|
|
|||
|
|
@ -221,31 +221,40 @@ class sram_base(design, verilog, lef):
|
|||
|
||||
# Copy the pins to the top level
|
||||
# This will either be used to route or left unconnected.
|
||||
for inst in self.insts:
|
||||
self.copy_power_pins(inst, "vdd")
|
||||
self.copy_power_pins(inst, "gnd")
|
||||
for pin_name in ["vdd", "gnd"]:
|
||||
for inst in self.insts:
|
||||
self.copy_power_pins(inst, pin_name)
|
||||
|
||||
if not OPTS.route_supplies:
|
||||
# Do not route the power supply (leave as must-connect pins)
|
||||
return
|
||||
|
||||
grid_stack = set()
|
||||
try:
|
||||
from tech import power_grid
|
||||
grid_stack = power_grid
|
||||
except ImportError:
|
||||
# if no power_grid is specified by tech we use sensible defaults
|
||||
import tech
|
||||
if "m4" in tech.layer:
|
||||
# Route a M3/M4 grid
|
||||
grid_stack = self.m3_stack
|
||||
elif "m3" in tech.layer:
|
||||
grid_stack =("m3",)
|
||||
# Route a M3/M4 grid
|
||||
grid_stack = self.m3_stack
|
||||
|
||||
from supply_grid_router import supply_grid_router as router
|
||||
if OPTS.route_supplies == "grid":
|
||||
from supply_grid_router import supply_grid_router as router
|
||||
elif OPTS.route_supplies:
|
||||
from supply_tree_router import supply_tree_router as router
|
||||
|
||||
rtr=router(grid_stack, self)
|
||||
rtr.route()
|
||||
|
||||
vdd_pin = rtr.get_pin("vdd")
|
||||
gnd_pin = rtr.get_pin("gnd")
|
||||
for pin_name, pin in [("vdd", vdd_pin), ("gnd", gnd_pin)]:
|
||||
self.remove_layout_pin(pin_name)
|
||||
self.add_layout_pin(pin_name,
|
||||
pin.layer,
|
||||
pin.ll(),
|
||||
pin.width(),
|
||||
pin.height())
|
||||
|
||||
def compute_bus_sizes(self):
|
||||
""" Compute the independent bus widths shared between two and four bank SRAMs """
|
||||
|
||||
|
|
|
|||
|
|
@ -63,7 +63,9 @@ class model_delay_test(openram_test):
|
|||
|
||||
# Only compare the delays
|
||||
spice_delays = {key:value for key, value in spice_data.items() if 'delay' in key}
|
||||
spice_delays['min_period'] = spice_data['min_period']
|
||||
model_delays = {key:value for key, value in model_data.items() if 'delay' in key}
|
||||
model_delays['min_period'] = model_data['min_period']
|
||||
debug.info(1,"Spice Delays={}".format(spice_delays))
|
||||
debug.info(1,"Model Delays={}".format(model_delays))
|
||||
|
||||
|
|
|
|||
|
|
@ -12,6 +12,6 @@ num_words = 16
|
|||
tech_name = OPTS.tech_name
|
||||
|
||||
nominal_corner_only = True
|
||||
route_supplies = True
|
||||
route_supplies = "tree"
|
||||
check_lvsdrc = True
|
||||
|
||||
|
|
|
|||
|
|
@ -89,7 +89,7 @@ def write_drc_script(cell_name, gds_name, extract, final_verification, output_pa
|
|||
f.write("drc off\n")
|
||||
f.write("gds polygon subcell true\n")
|
||||
f.write("gds warning default\n")
|
||||
f.write("#gds flatten true\n")
|
||||
f.write("gds flatten true\n")
|
||||
f.write("gds readonly true\n")
|
||||
f.write("#gds ordering true\n")
|
||||
f.write("gds read {}\n".format(gds_name))
|
||||
|
|
|
|||
Loading…
Reference in New Issue