mirror of https://github.com/VLSIDA/OpenRAM.git
Make default router tree router
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mrg
parent
f55b57033d
commit
d5ed45dadf
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@ -5,20 +5,14 @@
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#(acting for and on behalf of Oklahoma State University)
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#All rights reserved.
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#
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import gdsMill
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import tech
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import math
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import debug
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from globals import OPTS,print_time
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from contact import contact
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from pin_group import pin_group
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from pin_layout import pin_layout
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from vector3d import vector3d
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from globals import print_time
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from router import router
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from direction import direction
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from datetime import datetime
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import grid
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import grid_utils
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from scipy.sparse import csr_matrix
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from scipy.sparse.csgraph import minimum_spanning_tree
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class supply_tree_router(router):
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"""
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@ -36,7 +30,6 @@ class supply_tree_router(router):
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router.__init__(self, layers, design, gds_filename, self.rail_track_width)
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def create_routing_grid(self):
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"""
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Create a sprase routing grid with A* expansion functions.
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@ -133,7 +126,6 @@ class supply_tree_router(router):
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self.set_blockages(blockage_grids,False)
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def route_pins(self, pin_name):
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"""
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This will route each of the remaining pin components to the other pins.
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@ -144,48 +136,73 @@ class supply_tree_router(router):
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debug.info(1,"Maze routing {0} with {1} pin components to connect.".format(pin_name,
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remaining_components))
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for index,pg in enumerate(self.pin_groups[pin_name]):
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if pg.is_routed():
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continue
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# Create full graph
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pin_size = len(self.pin_groups[pin_name])
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adj_matrix = [[0] * pin_size for i in range(pin_size)]
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debug.info(1,"Routing component {0} {1}".format(pin_name, index))
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for index1,pg1 in enumerate(self.pin_groups[pin_name]):
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for index2,pg2 in enumerate(self.pin_groups[pin_name]):
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if index1>=index2:
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continue
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dist = int(grid_utils.distance_set(list(pg1.grids)[0], pg2.grids))
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adj_matrix[index1][index2] = dist
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# Clear everything in the routing grid.
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self.rg.reinit()
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# Find MST
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X = csr_matrix(adj_matrix)
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Tcsr = minimum_spanning_tree(X)
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mst = Tcsr.toarray().astype(int)
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connections = []
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for x in range(pin_size):
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for y in range(pin_size):
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if x >= y:
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continue
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if mst[x][y]>0:
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connections.append((x, y))
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# Route MST components
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for (src, dest) in connections:
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self.route_signal(pin_name, src, dest)
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#self.write_debug_gds("final.gds", True)
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#return
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# This is inefficient since it is non-incremental, but it was
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# easier to debug.
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self.prepare_blockages(pin_name)
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def route_signal(self, pin_name, src_idx, dest_idx):
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debug.info(2, "Routing {0} to {1} on pin {2}".format(src_idx, dest_idx, pin_name))
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# Clear everything in the routing grid.
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self.rg.reinit()
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# Add the single component of the pin as the source
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# which unmarks it as a blockage too
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self.add_pin_component_source(pin_name,index)
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# This is inefficient since it is non-incremental, but it was
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# easier to debug.
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self.prepare_blockages(pin_name)
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# Marks all pin components except index as target
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self.add_pin_component_target_except(pin_name,index)
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# Add the prevous paths as a target too
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self.add_path_target(self.paths)
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# Add the single component of the pin as the source
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# which unmarks it as a blockage too
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self.add_pin_component_source(pin_name, src_idx)
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print("SOURCE: ")
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for k,v in self.rg.map.items():
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if v.source:
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print(k)
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# Marks all pin components except index as target
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self.add_pin_component_target(pin_name, dest_idx)
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# Add the prevous paths as a target too
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#self.add_path_target(self.paths)
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print("TARGET: ")
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for k,v in self.rg.map.items():
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if v.target:
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print(k)
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# print("SOURCE: ")
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# for k,v in self.rg.map.items():
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# if v.source:
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# print(k)
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# print("TARGET: ")
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# for k,v in self.rg.map.items():
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# if v.target:
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# print(k)
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import pdb; pdb.set_trace()
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if index==1:
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self.write_debug_gds("debug{}.gds".format(pin_name),False)
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# Actually run the A* router
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if not self.run_router(detour_scale=5):
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self.write_debug_gds("debug_route.gds", True)
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# Actually run the A* router
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if not self.run_router(detour_scale=5):
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self.write_debug_gds("debug_route.gds",True)
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#if index==3 and pin_name=="vdd":
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# self.write_debug_gds("route.gds",False)
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# if index==3 and pin_name=="vdd":
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# self.write_debug_gds("route.gds",False)
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@ -229,20 +229,19 @@ class sram_base(design, verilog, lef):
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# Do not route the power supply (leave as must-connect pins)
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return
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grid_stack = set()
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try:
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from tech import power_grid
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grid_stack = power_grid
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except ImportError:
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# if no power_grid is specified by tech we use sensible defaults
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import tech
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if "m4" in tech.layer:
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# Route a M3/M4 grid
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grid_stack = self.m3_stack
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elif "m3" in tech.layer:
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grid_stack =("m3",)
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# Route a M3/M4 grid
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grid_stack = self.m3_stack
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from supply_grid_router import supply_grid_router as router
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if OPTS.route_supplies == "grid":
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from supply_grid_router import supply_grid_router as router
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elif OPTS.route_supplies:
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from supply_tree_router import supply_tree_router as router
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rtr=router(grid_stack, self)
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rtr.route()
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@ -12,6 +12,6 @@ num_words = 16
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tech_name = OPTS.tech_name
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nominal_corner_only = True
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route_supplies = True
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route_supplies = "tree"
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check_lvsdrc = True
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