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328 Commits

Author SHA1 Message Date
Hunter Nichols 4103745de2 Merged with dev, fixed conflict in ptx 2020-04-08 02:33:05 -07:00
Hunter Nichols 95363856e4 Added logical effort and input load for ptx module. 2020-04-08 02:29:57 -07:00
mrg a3797094d0 Swap lvs and sp dimensions for s8 2020-04-07 10:37:49 -07:00
mrg ab5dd47182 Ptx is in microns if lvs_lib exists 2020-04-03 14:06:56 -07:00
mrg 0d6c84036d Adjust fudge factor for pin spacing. 2020-04-02 09:47:13 -07:00
mrg 3b662026d2 pnand3 constant hack for input separation 2020-04-01 11:36:04 -07:00
mrg 7956b63d9f Add licon option to precharge 2020-04-01 11:26:45 -07:00
mrg 3074cf3b86 Small format cleanup 2020-04-01 11:15:29 -07:00
mrg bc9cbe70a7 Poly overlap doesn't convert to tx device 2020-04-01 09:42:07 -07:00
mrg d2c97d75a7 Add well contact and min area to power pin of precharge 2020-03-26 11:49:32 -07:00
mrg 1e3734cb26 Hack to fix pnand3 in freepdk45 2020-03-26 11:08:53 -07:00
mrg 2f353187ba Skywater extraction mode for si unit scales 2020-03-24 12:41:15 -07:00
mrg 1e2163c3a6 Hack for pnand3 pin spacing 2020-03-24 12:40:41 -07:00
mrg e9d0db44fd Add li_stack contact to ptx and pgate if it exists. 2020-03-23 16:55:38 -07:00
mrg f491876a5a Move up B input in pnor2 2020-03-23 13:49:08 -07:00
mrg f598a359d5 Remove unused contact in pnor2 2020-03-23 11:55:17 -07:00
mrg 717cbb0fe5 Remove unused contact in pnand3 2020-03-23 11:52:19 -07:00
mrg 0ee6963198 Remove unused contact in pnand2 2020-03-23 11:46:21 -07:00
mrg f21791a904 Add source drain contact options to ptx. 2020-03-23 11:36:45 -07:00
mrg c5a1be703c Rotate via and PEP8 formatting 2020-03-06 13:39:46 -08:00
mrg 23501c7b35 Convert pnand+pinv to pand in decoders. 2020-03-06 13:26:40 -08:00
mrg 5312629702 Remove jog in precharge. Jog is in port data 2020-03-05 12:10:13 -08:00
mrg 287a31f598 Precharge updates. 
Enable different layers for bitlines.
Jog bitlines to fit precharge transistors for close proximity bitlines.
PEP8 cleanup.
 2020-03-04 17:39:11 -08:00
mrg 7ba9e09e12 Incomplete precharge layer decoupling 2020-03-04 22:23:05 +00:00
mrg bb2305d56a PEP8 format fixes 2020-02-28 18:24:39 +00:00
mrg 0b73979388 Space inputs by M1 pitch 2020-02-28 18:23:49 +00:00
mrg 073bd47b31 Add source/drain/gate to structure 2020-02-28 18:23:36 +00:00
mrg 266d68c395 Generalize pgate width based on nwell/pwell contacts 2020-02-25 17:09:07 +00:00
mrg 254e584e35 Cleanup and simplify ptx for multiple technologies 2020-02-25 00:36:22 +00:00
mrg 585a708e0c Generalize y offsets in pnand3 2020-02-25 00:36:02 +00:00
mrg d565c9ac72 Generalize input y offsets 2020-02-25 00:35:32 +00:00
mrg 6bcffb8efb Change default cell height and fix contact width error 2020-02-25 00:34:59 +00:00
Bastian Koppelmann f9babcf666 port_data: Each submodule now specifies their bl/br names 
before the names of bl/br from the bitcell were assumed. If we want to
allow renaming of bl/br from bitcells, we have to seperate the other
modules from that. Note, that we don't touch every occurence of bl/br,
but only the once necessary that pin renaming of the bitcell works.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-02-12 15:00:50 +01:00
Bastian Koppelmann 64bf93e4e5 bank: Connect instances by their individual bl/br names 
each module should be able to state how their bl/br lines are named. Here we
always connect port_data with the bitcell_array, so port_data needs function
that return the names of bl/br.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-02-12 15:00:50 +01:00
mrg f7915ec55e Route to top of NMOS to prevent poly overlap nmos 2020-02-10 17:12:39 +00:00
mrg 4b06ab9eaf Move port 2 column address bus down. 
PEP 8 cleanup.
 2020-02-06 19:46:10 +00:00
mrg 5e514215d5 Force vertical vias on pnand3 2020-02-06 16:44:19 +00:00
mrg f0ecf385e8 Nwell fixes in pgates. 
Fix minor PEP8 format fixes.
Fix nwell to be 55% of cell height.
Move contact in hierarchical decoder for DRC error.
 2020-02-06 16:20:09 +00:00
mrg 596302d9a9 Update pgate well and well contacts. 
Extend well left and right past a cell boundary.
Use asymmetric well contacts.
 2020-02-05 18:22:45 +00:00
mrg 304971ff60 Fix ptx so nmos and pmos have same active offset and gates align 2020-02-04 17:38:35 +00:00
mrg 34c9b3a0a5 Fix well offset computation for PMOS 2020-02-03 17:37:53 +00:00
mrg 400cf0333a Pgates are 8 M1 high by default. Port data is bitcell height. 2020-01-30 03:34:04 +00:00
mrg 79391b84da Cleanup and rename vias. 2020-01-30 01:45:33 +00:00
Bastian Koppelmann 90a4a72bba modules: Use add_power_pin API for all modules 
sense_amp_array, write_driver_array, and single_column_mux were the only offenders.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-01-28 11:47:49 +01:00
mrg 71cbe74017 Round middle position fix 2020-01-24 18:00:28 +00:00
mrg 9beb0f4ece Add separate well design rules. 
Needed to fix various pgates with wells.
Did some cleanup of these gates as well.
 2020-01-23 19:43:41 +00:00
Matthew Guthaus a6f5e59e18 Remove unused layers and simplify layer check to work without it. 2019-12-23 21:49:47 +00:00
Matthew Guthaus 082f575e2a Use active_width in ptx again despite colliding with DRC rule 2019-12-23 21:45:09 +00:00
Matthew Guthaus bec12f5b94 Cleanup. 2019-12-23 21:16:08 +00:00
Matt Guthaus 4ad920eaf7 Small fixes to tech usage. 2019-12-23 08:42:52 -08:00
Matt Guthaus 89396698ef Non-preferred via in pnand active 2019-12-20 10:36:14 -08:00
Matt Guthaus 0da8164ea6 Remove some unnecessary via directions. 2019-12-19 13:54:50 -08:00
Matt Guthaus b7d78ec2ec Fix ptx active contact orientation to non-default M1 direction. 2019-12-19 12:54:10 -08:00
Matt Guthaus aceaa9fb21 Standardize contact names. 2019-12-17 15:55:20 -08:00
Matt Guthaus ed28b4983b Clean up and generalize layer rules. 
Convert metalN to mN.
Generalize helper constants in modules for
space, width, enclose, etc.
Use layer stacks whever possible.
Try to remove drc() calls in liu of helper constants.
 2019-12-17 11:03:36 -08:00
Matt Guthaus f71cfe0d9d Generalize active and poly stacks 2019-12-13 14:56:14 -08:00
Matt Guthaus e143a6033f Use layer stacks from tech file in design class and throughout 2019-12-13 14:13:41 -08:00
Matt Guthaus e048ada23c Abstract basic DRC checks 2019-12-11 17:56:55 -08:00
Matthew Guthaus f3286fb0c2 Don't add boundary to ptx 2019-12-06 02:37:12 +00:00
Matthew Guthaus 7397f110c5 Add bbox for special DRC rule boundary 2019-12-05 23:14:25 +00:00
Matt Guthaus 69bb245f28 Updates to gdsMill/tech layers 
Create active and poly contact types.
Define standard cell boundary option.
DataType and PurposeLayer are the same. Text must have type 0.
Remove vector from vlsiLayout. More debug in reader.
 2019-12-04 16:12:53 -08:00
Matt Guthaus b71d630643 None for layer means unused. 2019-11-26 13:34:39 -08:00
Matt Guthaus 04045cf672 Fix syntax error 2019-11-26 13:24:19 -08:00
Matt Guthaus 102758881a Use layer instead of special flags for wells 2019-11-26 13:22:52 -08:00
Matthew Guthaus 04af5480d2 Add skeleton files for pwrite_driver 2019-10-30 21:34:03 +00:00
Matt Guthaus 84c7146792 Fix some pep8 errors/warnings in pgate and examples. 2019-10-06 17:30:16 +00:00
Matt Guthaus 585ce63dff Removing unused tech parms. Simplifying redundant parms. 2019-09-04 16:08:18 -07:00
jsowash 27ec617315 Fixed M1.5 error in 8mux tests which came from pdriver. 2019-08-22 09:34:53 -07:00
Matt Guthaus 2b7025335c Use pand2 of correct size. Simplify width checking of AND array. 2019-08-21 11:20:35 -07:00
Matt Guthaus 54ab9440db Use pdriver instead of pinv in pand gates. 2019-08-21 10:18:46 -07:00
Hunter Nichols d273c0eef5 Merge branch 'dev' into analytical_cleanup 2019-08-08 13:20:27 -07:00
Hunter Nichols fc1cba099c Made all cin function relate to farads and all input_load relate to relative units. 2019-08-08 01:57:04 -07:00
Matt Guthaus 275891084b Add pand3 2019-08-07 16:33:29 -07:00
Matt Guthaus c2655fcaa9 Update pnor2 to new placement logic 2019-08-07 16:01:05 -07:00
Hunter Nichols 6860d3258e Added graph functions to compute analytical delay based on graph path. 2019-08-07 01:50:48 -07:00
Hunter Nichols 2ce7323838 Removed all unused analytical delay functions. 2019-08-06 17:09:25 -07:00
Matt Guthaus ad35f8745e Add direction to pins of all modules 2019-08-06 14:14:09 -07:00
mrg 8b0b2e2817 Merge branch 'dev' into rbl_revamp 2019-07-03 14:05:28 -07:00
mrg bc4a3ee2b7 New port_data module works in SCMOS 2019-07-03 13:17:12 -07:00
Hunter Nichols 4e08e2da87 Merged and fixed conflicts with dev 2019-06-25 16:55:50 -07:00
Hunter Nichols 4f3340e973 Cleaned up graph additions to characterizer. 2019-06-25 16:37:35 -07:00
Matt Guthaus 6e044b776f Merge branch 'pep8_cleanup' into dev 2019-06-14 08:47:10 -07:00
Matt Guthaus a234b0af88 Fix space before comment 2019-06-14 08:43:41 -07:00
mrg fc12ea24e9 Add boundary to every module and pgate for visual debug. 2019-06-03 15:27:37 -07:00
Hunter Nichols d8617acff2 Merged with dev 2019-05-15 18:48:00 -07:00
Hunter Nichols d54074d68e Made timing graph more gate-level. Changed edges to be defined by inputs/ouputs and name based. 2019-05-07 00:52:27 -07:00
Matt Guthaus 0f03553689 Update copyright to correct years. 2019-05-06 06:50:15 -07:00
Matt Guthaus 3f9a987e51 Update copyright. Add header to all OpenRAM files. 2019-04-26 12:33:53 -07:00
Matt Guthaus 0439b129bb Some pgates are designs since not a fixed height 2019-04-26 12:33:53 -07:00
Matt Guthaus 05ad4285af Cleanup pgate code. 
Moved create_netlist and create_layout to the pgate class
from which everything is derived. Modified all pgates
to have consistent debug output and order of init function.
 2019-04-26 12:30:42 -07:00
Hunter Nichols e292767166 Added graph creation and functions in base class and lower level modules. 2019-04-24 14:23:22 -07:00
Hunter Nichols 4f28295e20 Added initial graph for correct naming 2019-04-19 01:27:06 -07:00
Matt Guthaus 25bc3a66ed Add far left option for contact placement in pgates. 2019-04-17 13:41:35 -07:00
Matt Guthaus be20408fb2 Rewrite add_contact to use layer directions. 2019-04-15 18:00:36 -07:00
Hunter Nichols 25c034f85d Added more accurate bitline delay capacitance estimations 2019-04-09 01:56:32 -07:00
Hunter Nichols 1438519495 Added check to pdriver for 0 fanout which can break compute_sizes. 2019-04-03 17:53:28 -07:00
Hunter Nichols f6eefc1728 Added updated analytical characterization with combined models 2019-04-02 01:09:31 -07:00
Hunter Nichols 97777475b4 Added additions to account for custom delay chains. 2019-03-28 17:16:23 -07:00
Hunter Nichols 80a325fe32 Added corner information for analytical power estimation. 2019-03-04 19:27:53 -08:00
Hunter Nichols 0e96648211 Added linear corner factors in analytical delay model. 2019-03-04 00:42:18 -08:00
Hunter Nichols 5f01a52113 Fixed some delay model bugs. 2019-02-05 21:15:12 -08:00
Hunter Nichols d1218778b1 Fixed merge conflicts 2019-01-28 22:33:08 -08:00
Matt Guthaus 18805423e3 Simplify pdriver code. 2019-01-25 17:18:12 -08:00
Matt Guthaus beceb3fb60 Fix buggy analytical delay in pdriver 2019-01-25 16:22:59 -08:00
Matt Guthaus 09d6a63861 Change path to wire_path for Anaconda package conflict 2019-01-25 15:07:56 -08:00
Matt Guthaus 6f32bac1a2 Use rx of last pdriver instance after placing instances 2019-01-25 14:17:37 -08:00
Matt Guthaus 614aa54f17 Move clkbuf output lower to avoid dff outputs 2019-01-25 14:03:52 -08:00
Matt Guthaus ddf734891a Fix pdriver width error 2019-01-25 10:26:31 -08:00
Matt Guthaus 091b4e4c62 Add size commments to spize. Change pdriver stage effort. 2019-01-23 17:27:15 -08:00
Matt Guthaus b58fd03083 Change pbuf/pinv to pdriver in control logic. 2019-01-23 12:03:52 -08:00
Matt Guthaus 91636be642 Convert all contacts to use the sram_factory 2019-01-16 16:56:06 -08:00
Matt Guthaus 5192a01f2d Convert pgates to use ptx through the factory 2019-01-16 16:30:31 -08:00
Matt Guthaus a418431a42 First draft of sram_factory code 2019-01-16 16:15:38 -08:00
Hunter Nichols 6152ec7ec5 Merge branch 'dev' into multiport_characterization 2019-01-15 16:33:39 -08:00
Hunter Nichols 8eb4812e16 Made parasitic delay parameter in Freepdk45 more accurate, added stage names to delay model. 2018-12-17 23:32:02 -08:00
Jennifer Eve Sowash 4a5c18b6cc Removed line to skip pdriver_test 2018-12-13 19:10:38 -08:00
Jennifer Eve Sowash bc44c80d40 Added height to init in pdriver.py 2018-12-13 19:03:31 -08:00
Hunter Nichols 0510aeb3ec Merged with dev, removed commented out code. 2018-12-12 16:02:16 -08:00
Jennifer Eve Sowash a51aacfa90 Added corner case for 1 inv pos polarity and renamed variables. 2018-12-07 19:42:11 -08:00
Jennifer Eve Sowash a6eec10f41 Passed freepdk45 tests with pdriver.py 2018-12-07 12:58:05 -08:00
Jennifer Eve Sowash a24e5229cb Fixed method of determining inverter number. 2018-12-07 10:19:18 -08:00
Jennifer Eve Sowash 653ab3eda4 Changed method of determining number of inverters. 2018-12-06 19:34:19 -08:00
Jennifer Eve Sowash 8ea85e3e65 Merge branch 'dev' into pdriver 2018-12-06 14:38:08 -08:00
Jennifer Eve Sowash 5e19cf1e24 Updated naming, added compute_sizes(), and fixed sizing function. 2018-12-06 14:36:01 -08:00
Hunter Nichols ea55bda493 Changed s_en delay calculation based recent control logic changes. 2018-12-05 17:10:11 -08:00
Jennifer Eve Sowash 2534a32e20 pdriver.py passes resgression tests. Size and number of inverters has been added. 2018-12-03 12:55:48 -08:00
Jennifer Sowash 887674aa85 Added pdriver.py for testing. 2018-12-03 09:11:12 -08:00
Hunter Nichols 722bc907c4 Merged with dev. Fixed conflicts in tests. 2018-12-02 23:09:00 -08:00
Matt Guthaus 2ed8fc1506 pgate inputs and outputs are all on M1 for flexible via placement when using gates. 2018-11-28 12:42:29 -08:00
Matt Guthaus d2ca2efdbe Limit ps, pd, as, ad precision in ptx. 2018-11-28 09:47:54 -08:00
Matt Guthaus c45f990413 Change en to en_bar in precharge. Fix logic for inverted p_en_bar. 2018-11-27 14:17:55 -08:00
Matt Guthaus 9e0b31d685 Make pand2 and pbuf derive pgate. Initial DRC wrong layout. 2018-11-26 16:19:18 -08:00
Matt Guthaus b440031855 Add netlist only mode to new pgates 2018-11-26 15:29:42 -08:00
Matt Guthaus 2eff166527 Rotate vias in pand2 2018-11-26 14:05:04 -08:00
Matt Guthaus 5209619987 Move pnand2 output to allow input pin access on M2 2018-11-26 13:59:53 -08:00
Matt Guthaus 8fba32ca12 Add pand2 draft 2018-11-26 13:45:22 -08:00
Jennifer Eve Sowash bb7773ca7f Editted pbuf.py to pass regression. 2018-11-20 14:39:11 -08:00
Hunter Nichols 6e47de3f9b Separated relative delay into rise/fall. 2018-11-14 23:34:53 -08:00
Jennifer Sowash b6f1409fb9 Testing to ensure branch is up to date with dev. Added 04_pbuf_test.py and made changes to pbuf.py to align with comments. 2018-11-12 13:24:27 -08:00
Jennifer Sowash b366d88041 Merge branch 'dev' into pdriver 2018-11-12 11:30:37 -08:00
Jennifer Sowash 82abd32785 Added pbuf.py to create a single buffer. 2018-11-12 09:53:21 -08:00
Hunter Nichols bad55cfd05 Merged with dev. Fixed merge conflict. 2018-11-09 17:18:19 -08:00
Matt Guthaus c01effc819 Adjust ptx positions in precharge to be under the bl rail 2018-11-09 10:26:15 -08:00
Matt Guthaus ac7229f8d3 Move vdd pin in precharge inside cell 2018-11-09 10:11:24 -08:00
Matt Guthaus 21f5fb0870 precharge bl is on metal2 only. simplify via position code. 2018-11-09 09:11:00 -08:00
Hunter Nichols 8957c556db Added sense amp enable delay calculation. 2018-11-08 23:54:18 -08:00
Hunter Nichols b8061d3a4e Added initial code for determining the logical effort delay of the wordline. 2018-11-08 23:54:18 -08:00
Matt Guthaus 31eff6f24e Merge branch 'dev' into multiport_layout 2018-11-08 18:00:28 -08:00
Matt Guthaus 5dfba21acc Change tx mux size back to 8. Document why it was chosen. 2018-11-07 16:03:48 -08:00
Matt Guthaus 3d2abc0873 Change default col mux size to 2. Add some comments. 2018-11-07 15:43:08 -08:00