mirror of https://github.com/VLSIDA/OpenRAM.git
Remove unused contact in pnand2
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parent
f21791a904
commit
0ee6963198
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@ -66,13 +66,23 @@ class pnand2(pgate.pgate):
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def add_ptx(self):
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""" Create the PMOS and NMOS transistors. """
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self.nmos = factory.create(module_type="ptx",
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width=self.nmos_width,
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mults=self.tx_mults,
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tx_type="nmos",
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connect_poly=True,
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connect_active=True)
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self.add_mod(self.nmos)
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self.nmos_nd = factory.create(module_type="ptx",
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width=self.nmos_width,
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mults=self.tx_mults,
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tx_type="nmos",
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add_drain_contact=False,
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connect_poly=True,
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connect_active=True)
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self.add_mod(self.nmos_nd)
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self.nmos_ns = factory.create(module_type="ptx",
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width=self.nmos_width,
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mults=self.tx_mults,
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tx_type="nmos",
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add_source_contact=False,
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connect_poly=True,
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connect_active=True)
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self.add_mod(self.nmos_ns)
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self.pmos = factory.create(module_type="ptx",
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width=self.pmos_width,
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@ -99,9 +109,9 @@ class pnand2(pgate.pgate):
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# This is the extra space needed to ensure DRC rules
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# to the active contacts
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extra_contact_space = max(-self.nmos.get_pin("D").by(), 0)
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extra_contact_space = max(-self.nmos_nd.get_pin("D").by(), 0)
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# This is a poly-to-poly of a flipped cell
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self.top_bottom_space = max(0.5 * self.m1_width + self.m1_space + extra_contact_space,
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self.top_bottom_space = max(0.5 * self.m1_width + self.m1_space + extra_contact_space,
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self.poly_extend_active + self.poly_space)
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def route_supply_rails(self):
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@ -130,11 +140,11 @@ class pnand2(pgate.pgate):
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self.connect_inst(["Z", "B", "vdd", "vdd"])
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self.nmos1_inst = self.add_inst(name="pnand2_nmos1",
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mod=self.nmos)
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mod=self.nmos_nd)
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self.connect_inst(["Z", "B", "net1", "gnd"])
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self.nmos2_inst = self.add_inst(name="pnand2_nmos2",
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mod=self.nmos)
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mod=self.nmos_ns)
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self.connect_inst(["net1", "A", "gnd", "gnd"])
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def place_ptx(self):
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@ -160,7 +170,7 @@ class pnand2(pgate.pgate):
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# Output position will be in between the PMOS and NMOS
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self.output_pos = vector(0,
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0.5 * (pmos1_pos.y + nmos1_pos.y + self.nmos.active_height))
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0.5 * (pmos1_pos.y + nmos1_pos.y + self.nmos_nd.active_height))
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def add_well_contacts(self):
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"""
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@ -169,7 +179,7 @@ class pnand2(pgate.pgate):
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"""
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self.add_nwell_contact(self.pmos, self.pmos2_pos)
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self.add_pwell_contact(self.nmos, self.nmos2_pos)
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self.add_pwell_contact(self.nmos_nd, self.nmos2_pos)
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def connect_rails(self):
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""" Connect the nmos and pmos to its respective power rails """
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