mirror of https://github.com/VLSIDA/OpenRAM.git
Use active_width in ptx again despite colliding with DRC rule
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@ -146,11 +146,11 @@ class ptx(design.design):
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# Active width is determined by enclosure on both ends and contacted pitch,
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# at least one poly and n-1 poly pitches
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self.ptx_active_width = 2 * self.end_to_poly + self.poly_width + \
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self.active_width = 2 * self.end_to_poly + self.poly_width + \
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(self.mults - 1) * self.poly_pitch
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# Active height is just the transistor width
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self.ptx_active_height = self.tx_width
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self.active_height = self.tx_width
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# Poly height must include poly extension over active
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self.poly_height = self.tx_width + 2 * self.poly_extend_active
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@ -178,11 +178,11 @@ class ptx(design.design):
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# This is the center of the first active contact offset (centered vertically)
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self.contact_offset = self.active_offset + vector(active_enclose_contact + 0.5 * self.contact_width,
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0.5 * self.ptx_active_height)
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0.5 * self.active_height)
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# Min area results are just flagged for now.
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debug.check(self.ptx_active_width * self.ptx_active_height >= self.minarea_active,
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debug.check(self.active_width * self.active_height >= self.minarea_active,
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"Minimum active area violated.")
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# We do not want to increase the poly dimensions to fix
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# an area problem as it would cause an LVS issue.
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@ -312,16 +312,16 @@ class ptx(design.design):
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"""
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self.add_rect(layer="active",
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offset=self.active_offset,
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width=self.ptx_active_width,
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height=self.ptx_active_height)
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width=self.active_width,
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height=self.active_height)
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# If the implant must enclose the active, shift offset
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# and increase width/height
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enclose_width = self.implant_enclose_active
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enclose_offset = [enclose_width] * 2
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self.add_rect(layer="{}implant".format(self.implant_type),
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offset=self.active_offset - enclose_offset,
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width=self.ptx_active_width + 2 * enclose_width,
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height=self.ptx_active_height + 2 * enclose_width)
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width=self.active_width + 2 * enclose_width,
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height=self.active_height + 2 * enclose_width)
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def add_well_implant(self):
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"""
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