mirror of https://github.com/VLSIDA/OpenRAM.git
Space inputs by M1 pitch
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073bd47b31
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0b73979388
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@ -36,7 +36,8 @@ class pnand3(pgate.pgate):
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self.pmos_width = self.pmos_size * drc("minwidth_tx")
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# FIXME: Allow these to be sized
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debug.check(size == 1,"Size 1 pnand3 is only supported now.")
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debug.check(size == 1,
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"Size 1 pnand3 is only supported now.")
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self.tx_mults = 1
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# Creates the netlist and layout
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@ -66,7 +67,6 @@ class pnand3(pgate.pgate):
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self.route_inputs()
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self.route_output()
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def add_ptx(self):
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""" Create the PMOS and NMOS transistors. """
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self.nmos = factory.create(module_type="ptx",
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@ -148,8 +148,7 @@ class pnand3(pgate.pgate):
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"""
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pmos1_pos = vector(self.pmos.active_offset.x,
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self.height - self.pmos.active_height \
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- self.top_bottom_space)
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self.height - self.pmos.active_height - self.top_bottom_space)
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self.pmos1_inst.place(pmos1_pos)
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pmos2_pos = pmos1_pos + self.ptx_offset
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@ -168,9 +167,6 @@ class pnand3(pgate.pgate):
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self.nmos3_pos = nmos2_pos + self.ptx_offset
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self.nmos3_inst.place(self.nmos3_pos)
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# This will help with the wells and the input/output placement
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self.output_pos = vector(0, 0.5*self.height)
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def add_well_contacts(self):
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""" Add n/p well taps to the layout and connect to supplies """
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@ -187,29 +183,30 @@ class pnand3(pgate.pgate):
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self.connect_pin_to_rail(self.pmos2_inst, "D", "vdd")
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def route_inputs(self):
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""" Route the A and B inputs """
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self.inputC_yoffset = self.nmos3_inst.uy() + 0.5 * contact.poly_contact.height
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""" Route the A and B and C inputs """
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# Put B right on the well line
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self.inputB_yoffset = self.nwell_y_offset
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self.route_input_gate(self.pmos2_inst,
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self.nmos2_inst,
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self.inputB_yoffset,
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"B",
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position="center")
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self.inputC_yoffset = self.inputB_yoffset - self.m1_pitch
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self.route_input_gate(self.pmos3_inst,
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self.nmos3_inst,
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self.inputC_yoffset,
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"C",
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position="center")
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self.inputA_yoffset = self.pmos1_inst.by() - self.poly_extend_active \
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- contact.poly_contact.height
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self.inputA_yoffset = self.inputB_yoffset + self.m1_pitch
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self.route_input_gate(self.pmos1_inst,
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self.nmos1_inst,
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self.inputA_yoffset,
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"A",
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position="center")
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self.inputB_yoffset = 0.5*(self.inputA_yoffset + self.inputC_yoffset)
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self.route_input_gate(self.pmos2_inst,
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self.nmos2_inst,
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self.inputB_yoffset,
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"B",
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position="center")
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def route_output(self):
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""" Route the Z output """
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