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Fix ptx so nmos and pmos have same active offset and gates align

This commit is contained in:
mrg 2020-02-04 17:38:35 +00:00
parent 53217e4030
commit 304971ff60
2 changed files with 14 additions and 8 deletions
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4
compiler/pgates/pgate.py
View File

@ -75,8 +75,10 @@ class pgate(design.design):
pmos_gate_pin = pmos_inst.get_pin("G")
# Check if the gates are aligned and give an error if they aren't!
if nmos_gate_pin.ll().x != pmos_gate_pin.ll().x:
self.gds_write("unaliged_gates.gds")
debug.check(nmos_gate_pin.ll().x == pmos_gate_pin.ll().x,
"Connecting unaligned gates not supported.")
"Connecting unaligned gates not supported. See unaligned_gates.gds.")
# Pick point on the left of NMOS and connect down to PMOS
nmos_gate_pos = nmos_gate_pin.ll() + vector(0.5 * self.poly_width, 0)

18
compiler/pgates/ptx.py
View File

@ -156,13 +156,17 @@ class ptx(design.design):
self.poly_height = self.tx_width + 2 * self.poly_extend_active
# The active offset is due to the well extension
# but we need to do the active offset for the other tx type too
# so that they align in pgates.
well_enclose_active = 0
if self.well_type=="p" and "pwell" in layer:
well_enclose_active = max(drc("pwell_enclose_active"), well_enclose_active)
if self.well_type=="n" and "nwell" in layer:
well_enclose_active = max(drc("nwell_enclose_active"), well_enclose_active)
if "pwell" in layer:
pwell_enclose_active = drc("pwell_enclose_active")
else:
pwell_enclose_active = 0
if "nwell" in layer:
nwell_enclose_active = drc("nwell_enclose_active")
else:
nwell_enclose_active = 0
# Use the max of either so that the poly gates will align properly
well_enclose_active = max(pwell_enclose_active,
nwell_enclose_active)
self.active_offset = vector([well_enclose_active] * 2)
# Well enclosure of active, ensure minwidth as well