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Remove jog in precharge. Jog is in port data

This commit is contained in:
mrg 2020-03-05 12:10:13 -08:00
parent 9c1f0657dd
commit 5312629702
1 changed files with 6 additions and 13 deletions
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19
compiler/pgates/precharge.py
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@ -228,32 +228,25 @@ class precharge(design.design):
layer_width = drc("minwidth_" + self.bitline_layer)
layer_space = drc("{0}_to_{0}".format(self.bitline_layer))
yoffset = self.initial_yoffset - 0.5 * self.m2_pitch
# adds the BL
self.bl_xoffset = layer_space + 0.5 * layer_width
top_pos = vector(self.bl_xoffset, self.height)
mid1_pos = vector(self.bl_xoffset, yoffset)
mid2_pos = vector(self.bitcell_bl_pin.cx(), yoffset)
pin_pos = vector(self.bitcell_bl_pin.cx(), 0)
self.add_path(self.bitline_layer,
[top_pos, mid1_pos, mid2_pos, pin_pos])
pin_pos = vector(self.bl_xoffset, 0)
self.add_path(self.bitline_layer, [top_pos, pin_pos])
self.bl_pin = self.add_layout_pin_segment_center(text="bl",
layer=self.bitline_layer,
start=pin_pos,
end=mid2_pos)
end=top_pos)
# adds the BR
self.br_xoffset = self.width - layer_space - 0.5 * layer_width
top_pos = vector(self.br_xoffset, self.height)
mid1_pos = vector(self.br_xoffset, yoffset)
mid2_pos = vector(self.bitcell_br_pin.cx(), yoffset)
pin_pos = vector(self.bitcell_br_pin.cx(), 0)
self.add_path(self.bitline_layer,
[top_pos, mid1_pos, mid2_pos, pin_pos])
pin_pos = vector(self.br_xoffset, 0)
self.add_path(self.bitline_layer, [top_pos, pin_pos])
self.br_pin = self.add_layout_pin_segment_center(text="br",
layer=self.bitline_layer,
start=pin_pos,
end=mid2_pos)
end=top_pos)
def connect_to_bitlines(self):
"""