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Force vertical vias on pnand3

This commit is contained in:
mrg 2020-02-06 16:44:19 +00:00
parent f0ecf385e8
commit 5e514215d5
1 changed files with 6 additions and 3 deletions
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9
compiler/pgates/pnand3.py
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@ -233,11 +233,14 @@ class pnand3(pgate.pgate):
# Go up to metal2 for ease on all output pins
self.add_via_center(layers=self.m1_stack,
offset=pmos1_pin.center())
offset=pmos1_pin.center(),
directions=("V", "V"))
self.add_via_center(layers=self.m1_stack,
offset=pmos3_pin.center())
offset=pmos3_pin.center(),
directions=("V", "V"))
self.add_via_center(layers=self.m1_stack,
offset=nmos3_pin.center())
offset=nmos3_pin.center(),
directions=("V", "V"))
# PMOS3 and NMOS3 are drain aligned
self.add_path("m2", [pmos3_pin.center(), nmos3_pin.uc()])