mirror of https://github.com/VLSIDA/OpenRAM.git
Don't add boundary to ptx
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@ -59,9 +59,9 @@ class ptx(design.design):
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# some transistor sizes in other netlist depend on pbitcell
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self.create_layout()
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ll = self.find_lowest_coords()
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ur = self.find_highest_coords()
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self.add_boundary(ll, ur)
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#ll = self.find_lowest_coords()
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#ur = self.find_highest_coords()
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#self.add_boundary(ll, ur)
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# (0,0) will be the corner ofthe active area (not the larger well)
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self.translate_all(self.active_offset)
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