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328 Commits

Author SHA1 Message Date
jcirimel 9857a3f7e7 Merge branch 'dev' into discrete_models 2020-06-05 16:47:01 -07:00
jcirimel 08f6bd8d24 optimize tx binning for area 2020-06-05 02:53:03 -07:00
mrg e06dc3810a Move precharge pin to bottom 2020-06-04 12:12:19 -07:00
mrg b2b7e7800b Undo same bitline pitch 2020-06-03 16:39:05 -07:00
mrg 4183638f03 Align precharge bitlines with col mux 2020-06-03 16:05:57 -07:00
mrg 4bc1e9a026 Fix the bitline spacing in the column mux to a constant. 2020-06-03 15:47:03 -07:00
Joey Kunzler 84021c9ccb merge conflict 2 - port data 2020-06-02 16:32:08 -07:00
Joey Kunzler 001bf1b827 merge conflict - port data 2020-06-02 14:15:39 -07:00
mrg b0aa70ffda Fix precharge vdd route layer 2020-06-02 09:23:27 -07:00
mrg b3b03d4d39 Hard cells can accept height parameter too. 2020-06-01 16:46:00 -07:00
mrg 82dc937768 Add missing vias by using via stack function 2020-05-29 16:53:47 -07:00
mrg 4a67f7dc71 Thin-cell decoder changes. 
Add hard decoder gates (nand, inv, pnan)
Add conditions for routing using LI layer in s8.
Generalize bus layers for decoders.
Move custom cells to own directory.
Fixed via directions, etc.
Add 4x16 hierarchical decoder and test case
 2020-05-29 10:36:07 -07:00
Joey Kunzler 9a6b38b67e merge conflict 2020-05-26 16:03:36 -07:00
mrg a305d788d7 Vertical gates need both well contacts. 2020-05-13 16:54:35 -07:00
mrg 4b526f0d5f Check min size inverter. 2020-05-13 16:54:26 -07:00
mrg f8bcc54338 Determine width after routing with no well contacts. 2020-05-13 16:04:38 -07:00
mrg 617bf302d1 Add option to remove wells. Save area in pgates with redundant wells. 2020-05-13 14:46:42 -07:00
mrg c96a6d0b9d Add no well option. Add stack gates vertical option. 2020-05-11 16:22:08 -07:00
mrg b7c66d7e07 Changes to simplify metal preferred directions and pitches. 
Changes to allow decoder height to be a 2x multiple of bitcell height.
Split of control logic tests.
Fixed track spacing in SRAM and channel router
PEP8 cleanup.
 2020-05-10 11:32:45 -07:00
mrg dd73afc983 Changes to allow decoder height to be a 2x multiple of bitcell height. 
Convert to use li layer in pgates.
Fix multifinger devices with li layers.
Simplify wordline driver input routing.
Fix power pin direction option update.
PEP8 cleanup
Changes to simplify metal preferred directions and pitches.
Split of control logic tests.
 2020-05-10 06:56:22 -07:00
jcirimel 5666e79287 Merge branch 'dev' into discrete_models 2020-05-08 03:13:16 -07:00
Joey Kunzler e642b8521b increase col_mux bitline spacing to fix cyclic vcg 2020-05-06 13:02:33 -07:00
jcirimel d8a51ecafb remove prints, scaling bug fix 2020-05-05 21:59:28 -07:00
jcirimel 71a1dd8f38 fix tx binning in col mux for memories with >1 word per row 2020-05-05 16:35:51 -07:00
Joey Kunzler 0bae652be9 fix merge conflicts 2020-04-23 11:51:46 -07:00
Joey Kunzler fed1c0bbe1 s8 col mux array 2020-04-22 16:22:34 -07:00
mrg 32576fb62c Convert wordline driver to pand2 rather than pnand2+pdriver 2020-04-22 13:27:50 -07:00
mrg 0bb4a7f93d Merge branch 'dev' into tech_migration 2020-04-21 16:37:36 -07:00
Joey Kunzler 3d4a40b338 freepdk45 col_mux fix 2020-04-21 15:38:19 -07:00
mrg fc85dfe29f Add boundary to all pgates 2020-04-21 15:21:57 -07:00
Joey Kunzler ee1de9ac8c Merge branch 's8_update' of github.com:VLSIDA/PrivateRAM into s8_update 2020-04-20 22:14:09 -07:00
Joey Kunzler 829f3e03fa col_mux.py update with correct contacts 2020-04-20 22:08:29 -07:00
Joey Kunzler 63bea67fb5 col_mux.py changes 2020-04-20 20:22:46 -07:00
jcirimel f590ecf83c fix minimum pinv sizing 2020-04-18 05:51:21 -07:00
jcirimel add9ec7b28 remove excess newlines 2020-04-18 05:42:23 -07:00
jcirimel 85bc801689 fix pinv drc bug 2020-04-18 05:34:55 -07:00
jcirimel 1f094b03bc use more optimal discrete pinv sizing 2020-04-18 05:26:39 -07:00
jcirimel 486819ae0d fix width bin typo 2020-04-17 15:27:36 -07:00
jcirimel a158ad1e81 add missing import 2020-04-17 14:24:52 -07:00
jcirimel 24e0e326d4 merge dev in to disc... 2020-04-16 02:18:39 -07:00
jcirimel ebb1a7bedb merge local with dev 2020-04-16 02:16:56 -07:00
jcirimel 6c1c72c520 fix pgates binning off-by-one 2020-04-15 04:09:58 -07:00
mrg 43dcf675a1 Move pnand outputs to M1. Debug hierarchical decoder multirow. 2020-04-14 10:52:25 -07:00
jcirimel 5f4ed47c57 netlist only discrete simulating 2020-04-13 20:48:34 -07:00
jcirimel afcb5174ac discrete dff tests working 2020-04-11 01:19:04 -07:00
mrg 2e67d44cd7 First pass of multiple bitcells per decoder row 2020-04-10 13:29:41 -07:00
jcirimel a0eb9839ad revert units on sp_lib, begin discrete tx simulation 2020-04-09 19:39:21 -07:00
mrg 745450fadc Syntax error 2020-04-08 17:04:50 -07:00
mrg cddfaa0dc8 Tech dependent fudge factor 2020-04-08 17:04:14 -07:00
mrg 0c27942bb2 Dynamically try and DRC decoder for height 2020-04-08 16:45:28 -07:00
Hunter Nichols 4103745de2 Merged with dev, fixed conflict in ptx 2020-04-08 02:33:05 -07:00
Hunter Nichols 95363856e4 Added logical effort and input load for ptx module. 2020-04-08 02:29:57 -07:00
mrg a3797094d0 Swap lvs and sp dimensions for s8 2020-04-07 10:37:49 -07:00
mrg ab5dd47182 Ptx is in microns if lvs_lib exists 2020-04-03 14:06:56 -07:00
mrg 0d6c84036d Adjust fudge factor for pin spacing. 2020-04-02 09:47:13 -07:00
mrg 3b662026d2 pnand3 constant hack for input separation 2020-04-01 11:36:04 -07:00
mrg 7956b63d9f Add licon option to precharge 2020-04-01 11:26:45 -07:00
mrg 3074cf3b86 Small format cleanup 2020-04-01 11:15:29 -07:00
mrg bc9cbe70a7 Poly overlap doesn't convert to tx device 2020-04-01 09:42:07 -07:00
mrg d2c97d75a7 Add well contact and min area to power pin of precharge 2020-03-26 11:49:32 -07:00
mrg 1e3734cb26 Hack to fix pnand3 in freepdk45 2020-03-26 11:08:53 -07:00
mrg 2f353187ba Skywater extraction mode for si unit scales 2020-03-24 12:41:15 -07:00
mrg 1e2163c3a6 Hack for pnand3 pin spacing 2020-03-24 12:40:41 -07:00
mrg e9d0db44fd Add li_stack contact to ptx and pgate if it exists. 2020-03-23 16:55:38 -07:00
mrg f491876a5a Move up B input in pnor2 2020-03-23 13:49:08 -07:00
mrg f598a359d5 Remove unused contact in pnor2 2020-03-23 11:55:17 -07:00
mrg 717cbb0fe5 Remove unused contact in pnand3 2020-03-23 11:52:19 -07:00
mrg 0ee6963198 Remove unused contact in pnand2 2020-03-23 11:46:21 -07:00
mrg f21791a904 Add source drain contact options to ptx. 2020-03-23 11:36:45 -07:00
mrg c5a1be703c Rotate via and PEP8 formatting 2020-03-06 13:39:46 -08:00
mrg 23501c7b35 Convert pnand+pinv to pand in decoders. 2020-03-06 13:26:40 -08:00
mrg 5312629702 Remove jog in precharge. Jog is in port data 2020-03-05 12:10:13 -08:00
mrg 287a31f598 Precharge updates. 
Enable different layers for bitlines.
Jog bitlines to fit precharge transistors for close proximity bitlines.
PEP8 cleanup.
 2020-03-04 17:39:11 -08:00
mrg 7ba9e09e12 Incomplete precharge layer decoupling 2020-03-04 22:23:05 +00:00
mrg bb2305d56a PEP8 format fixes 2020-02-28 18:24:39 +00:00
mrg 0b73979388 Space inputs by M1 pitch 2020-02-28 18:23:49 +00:00
mrg 073bd47b31 Add source/drain/gate to structure 2020-02-28 18:23:36 +00:00
mrg 266d68c395 Generalize pgate width based on nwell/pwell contacts 2020-02-25 17:09:07 +00:00
mrg 254e584e35 Cleanup and simplify ptx for multiple technologies 2020-02-25 00:36:22 +00:00
mrg 585a708e0c Generalize y offsets in pnand3 2020-02-25 00:36:02 +00:00
mrg d565c9ac72 Generalize input y offsets 2020-02-25 00:35:32 +00:00
mrg 6bcffb8efb Change default cell height and fix contact width error 2020-02-25 00:34:59 +00:00
Bastian Koppelmann f9babcf666 port_data: Each submodule now specifies their bl/br names 
before the names of bl/br from the bitcell were assumed. If we want to
allow renaming of bl/br from bitcells, we have to seperate the other
modules from that. Note, that we don't touch every occurence of bl/br,
but only the once necessary that pin renaming of the bitcell works.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-02-12 15:00:50 +01:00
Bastian Koppelmann 64bf93e4e5 bank: Connect instances by their individual bl/br names 
each module should be able to state how their bl/br lines are named. Here we
always connect port_data with the bitcell_array, so port_data needs function
that return the names of bl/br.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-02-12 15:00:50 +01:00
mrg f7915ec55e Route to top of NMOS to prevent poly overlap nmos 2020-02-10 17:12:39 +00:00
mrg 4b06ab9eaf Move port 2 column address bus down. 
PEP 8 cleanup.
 2020-02-06 19:46:10 +00:00
mrg 5e514215d5 Force vertical vias on pnand3 2020-02-06 16:44:19 +00:00
mrg f0ecf385e8 Nwell fixes in pgates. 
Fix minor PEP8 format fixes.
Fix nwell to be 55% of cell height.
Move contact in hierarchical decoder for DRC error.
 2020-02-06 16:20:09 +00:00
mrg 596302d9a9 Update pgate well and well contacts. 
Extend well left and right past a cell boundary.
Use asymmetric well contacts.
 2020-02-05 18:22:45 +00:00
mrg 304971ff60 Fix ptx so nmos and pmos have same active offset and gates align 2020-02-04 17:38:35 +00:00
mrg 34c9b3a0a5 Fix well offset computation for PMOS 2020-02-03 17:37:53 +00:00
mrg 400cf0333a Pgates are 8 M1 high by default. Port data is bitcell height. 2020-01-30 03:34:04 +00:00
mrg 79391b84da Cleanup and rename vias. 2020-01-30 01:45:33 +00:00
Bastian Koppelmann 90a4a72bba modules: Use add_power_pin API for all modules 
sense_amp_array, write_driver_array, and single_column_mux were the only offenders.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-01-28 11:47:49 +01:00
mrg 71cbe74017 Round middle position fix 2020-01-24 18:00:28 +00:00
mrg 9beb0f4ece Add separate well design rules. 
Needed to fix various pgates with wells.
Did some cleanup of these gates as well.
 2020-01-23 19:43:41 +00:00
Matthew Guthaus a6f5e59e18 Remove unused layers and simplify layer check to work without it. 2019-12-23 21:49:47 +00:00
Matthew Guthaus 082f575e2a Use active_width in ptx again despite colliding with DRC rule 2019-12-23 21:45:09 +00:00
Matthew Guthaus bec12f5b94 Cleanup. 2019-12-23 21:16:08 +00:00
Matt Guthaus 4ad920eaf7 Small fixes to tech usage. 2019-12-23 08:42:52 -08:00