mirror of https://github.com/VLSIDA/OpenRAM.git
Fix syntax error
This commit is contained in:
parent
f4599b7121
commit
04045cf672
|
|
@ -153,7 +153,7 @@ class ptx(design.design):
|
|||
|
||||
# Well enclosure of active, ensure minwidth as well
|
||||
well_name = "{}well".format(self.well_type)
|
||||
if layer[well_name]):
|
||||
if layer[well_name]:
|
||||
self.cell_well_width = max(self.active_width + 2 * self.well_enclose_active,
|
||||
self.well_width)
|
||||
self.cell_well_height = max(self.tx_width + 2 * self.well_enclose_active,
|
||||
|
|
|
|||
Loading…
Reference in New Issue