a47b7352b4
Add casex/z support
...
A casex statement cannot be directly translated to a VHDL case
statement as VHDL does not treat the don't-care bit as special.
The solution here is to generate an if statement from the casex
which compares only the non-don't-care bit positions.
2008-10-14 20:16:10 +01:00
fd4018cb33
Fix IVL_LPM_MUX where inputs are different signedness to outputs
2008-10-05 17:08:19 +01:00
b40de5ccb0
Implement IVL_LPM_CMP_NE(E)
...
Looks like I forgot this one
2008-10-05 17:04:19 +01:00
a7cbb38248
Fix resizing of constant bit vectors
...
Emitting a VHDL expression like Resize("01", 32) is ambiguous
between interpreting "01" as a Signed or an Unsigned. There's
no point actually outputting this as we can sign-extend the
constant value in the code generator, which is what this
patch does.
2008-10-05 13:49:07 +01:00
4394aff909
Merge branch 'master' of git://icarus.com/~steve-icarus/verilog into vhdl
...
Conflicts:
tgt-vhdl/stmt.cc
2008-10-05 12:44:30 +01:00
c5263268ed
Tidy up reduction functions in support.cc
...
This removes some unnecessary code duplication as the functions
only differ (or need to differ) in two places.
2008-09-13 18:20:12 +01:00
e5abe182c1
Add reduction XOR/XNOR in expressions
2008-09-13 18:09:11 +01:00
e5343ef73f
Implement arithmetic right shift >>>
...
This is currently implemented using the numeric_std
shift_right function as the sra operator is not defined on
signed/unsigned types before VHDL-2006.
2008-09-13 15:23:42 +01:00
2516d63805
A basic translation of the Verilog power operator to VHDL
...
The exponentiation operator in VHDL is not defined for numeric_std
types. We can get around this by converting the operands to integers,
performing the operation, then converting the result back to the
original type. This will work OK in simulation but certainly will not
synthesise unless the operands are constant.
However, even this does not work quite correctly. The Integer type in
VHDL is signed and usually only 32 bits, therefore any result larger
than this will overflow and raise an exception. I can't see a way
around this at the moment.
2008-09-12 20:19:22 +01:00
f233793061
Spelling fixes
...
No code changes.
2008-09-09 19:21:42 -07:00
ec2511da64
Use British spelling and fix a few typos
2008-09-09 19:57:32 +01:00
4898cd04c6
Remove redundant back-end selections.
...
Target selection is done by the DLL target code generator, so there
is no value having a layer of target selection ahead of it. Remove
all that redundant code and simplify the target config files to reflect
this.
2008-09-07 16:43:54 -07:00
8fc35fa32a
Avoid emitting empty string at end of $display translation
...
This happened if the last part of a format string was a % code.
2008-09-06 13:23:55 +01:00
6fe7583784
Cary R.'s additional system functions, real value error messages, etc.
...
I've changed the find_entity() error messages to asserts since
this should be fixed by the previous patch.
2008-09-06 12:06:01 +01:00
a34348bb35
Add (temporary) error for ICT_SCOPE_GENERATE
...
Generate scopes were previously ignored, and this would cause a segfault
later on. This patch gives an error whenever it encounters a generate
scope. This should be removed once generate statements are implemented.
2008-09-06 11:38:37 +01:00
4cb2090978
Fix vhdl_expr::cast when expression has no assigned type
...
This avoids a couple of segfaults
2008-09-02 20:22:50 +01:00
ff766899b0
Add IVL_LPM_CMP_GT
2008-09-02 19:07:38 +01:00
122890fef4
Make sure LPM expression is cast to the output type
...
This fixes some signed/unsigned bugs identified by the signedX tests.
2008-09-02 19:02:54 +01:00
319b886118
Build files compatible with snapshot 20080830
2008-08-30 17:09:51 -07:00
0e458501b3
Ensure binary operands have correct signedness
...
Previously only signedness was only corrected for the
result. This patch ensures the VHDL operands have the
same signedness as their Verilog counterparts.
This fixes a few of the signedX tests.
2008-08-28 21:53:12 +01:00
8323d5d01d
Finish cast.cc cleanup
...
Replace big if statement with switch statemetn
2008-08-27 16:59:05 +01:00
b5e65ac9ed
Refactor and clean up cast.cc
...
This splits up the monolithic and confusing vhdl_expr::cast function into
several smaller to_XXX functions which each generate code to cast an
expression to type XXX. This makes it much easier to understand and maintain.
2008-08-27 16:47:07 +01:00
8e023d1227
Remove redundant function
2008-08-22 21:27:24 +01:00
d21b3258e3
Support conversion of (un)signed to std_logic
...
Take the least-significant bit. This fixes a couple of broken
test cases.
2008-08-22 20:59:14 +01:00
331a51e842
Add more warnings about untranslatable constructs
2008-08-22 20:25:58 +01:00
63a1e25129
Catch case where component name and instance differ only in case
...
This causes an error in VHDL (which is case-insensitive). This
patch simply appends _Inst to the instance name if it detects this.
2008-08-22 20:20:17 +01:00
fae7ab2418
Use case-insensitive string comparison for get_decl
...
This will allow us to detect cases where identifiers differ only by case
2008-08-22 20:15:45 +01:00
535ef6be38
Change function return value from Verilog_Result to <funcname>_Result
2008-08-21 19:44:12 +01:00
4ebe09bb72
Various fixes to support automatic functions
...
Mostly this ensures that a recursive call to a function
is made with the correct types (this may involve generating
code to cast expressions to the correct type).
2008-08-20 22:54:53 +01:00
cb1d4fd278
Amend inaccurate comment
2008-08-18 16:15:05 +01:00
e1deba51ab
Handle BUFIF logic when vector inputs
2008-08-18 15:48:07 +01:00
d53014a07f
Fix leading comma it expression only has "others" part
...
Stop syntax errors caused by things like this:
(, others => '1')
2008-08-18 15:36:11 +01:00
7865264de0
Implement IVL_LPM_REPEAT
2008-08-18 15:34:58 +01:00
86661c1538
Add a few more `unsupported' messages
2008-08-18 15:29:30 +01:00
e2dd7425bd
Add error messages for unsupported statement types
2008-08-18 15:24:38 +01:00
026d941734
Avoid printing field widths in $display/$write output
...
This removes some unwanted artifacts from the output.
2008-08-15 19:43:16 +01:00
a577ee447b
Generate process for sequential UDPs
2008-08-13 17:03:03 +01:00
d7b85c42a0
Split sequential and combinatorial UDPs into separate functions
2008-08-13 11:57:05 +01:00
dea54df71b
Catch possibly NULL return value
...
This is caused by using a hierarchical reference (which can't
be translated to VHDL). The result of get_decl is NULL since
the signal has been declared in a different VHDL architecture.
Adding the assert is cleaner than having it segfault, for the
moment, until a nicer error message can be added.
2008-08-12 09:47:03 +01:00
a3929330b0
Fix regression caused by UDP delay patch
...
translate_time_expr cannot be passed a NULL ivl_expr_t.
2008-08-11 20:53:13 +01:00
c404b761b7
Change `out' ports to `buffer' when the signal is read
...
Previously this was handled by creating an internal
signal that was connected to the output and could also
be read inside the entity. The correct solution is to
make the output `buffer' rather than `out'. However, this
does not work in the case when an output is connected to
an output of a child entity, and that values is read
in the parent. In this case *both* the outputs of the child
and the parent need to be made `buffer'.
2008-08-11 20:48:28 +01:00
9b1f2d5971
Remove UDP debug messages from output
2008-08-11 20:37:10 +01:00
9d7e4ac15f
Allow delays in combinatorial UDPs
...
Add a `after' clause to the `with .. select' statement.
2008-08-11 20:36:09 +01:00
d55a3a073a
Handle '?' in vl_to_vhdl_bit
...
The rough translation is '-', although the semantics are incompatible
in some cases (e.g. '-' = '1' is false)
2008-08-11 13:53:42 +01:00
01bf741983
Implement combinatorial UDPs
...
Using a `with .. select' statement
2008-08-11 13:23:50 +01:00
bf3734110e
Add VHDL syntax element for `with .. select' statement
...
This will be used to implement combinatorial UDPs
2008-08-11 13:09:52 +01:00
6dcf936807
Generate combined input for UDP devices
...
Combinatorial UDPs will be implemented with a `with ... select'
statemetnt. However the input to this must be "locally static".
This patch joins the inputs into a vector which can be used as
the select expression.
2008-08-11 12:58:46 +01:00
8e0bf3ebff
Add conversion from std_logic to (un)signed types
...
Implemented using the expression (0 => X, others => '0')
2008-08-10 11:22:23 +01:00
7ed8c0915d
Add file/line comments to signal declarations
2008-08-08 20:28:16 +01:00
eef1c968dc
Add message that casex cannot be translated
...
...with the correct behavior. It would be possible to
just translate it as a regular VHDL case statement (as
it was before this patch). But the behavior is not
correct as VHDL only does the equivalent of case-equality
in case statements and this can be confusing when debugging
the output. An alternative might be to emit a warning rather
than an error.
2008-08-08 20:09:40 +01:00
0985158090
Handle %% in $display
2008-08-08 20:07:22 +01:00
090ae5fa56
Catch case where signal with same name in task and module
...
This fixes task3.14C
2008-08-08 19:47:20 +01:00
13cb81f4bb
Add task signals to containing architecture
...
This is necessary to support the in-line expansion of tasks
2008-08-08 19:31:45 +01:00
bb0efda526
Make make_safe_name case insensitive
2008-08-07 17:58:42 +01:00
e4d0a92d7c
Division and modulus operators
2008-08-07 14:18:26 +01:00
28d782e13c
Remove redundant verilog_support.vhd file
2008-08-07 13:10:53 +01:00
6f5f700cb9
Very minimal implementation of tasks
...
This expands the task in-line inside the process to avoid
problems with global variables (VHDL processes cannot
reference globals)
2008-08-07 10:54:39 +01:00
4cbec1c817
Add XNOR binary operand
2008-08-06 11:18:01 +01:00
f86f454956
Apply the last patch to if/case statements too
...
This further cleans up the output by removing more
useless `wait for 0ns' statements.
2008-08-05 11:09:51 +01:00
e01e038cf9
Avoid generating useless `wait for 0ns' statements
...
If the final statement in a process is a non-blocking
assignment then there is no point adding a `wait for 0ns'
after it since it will be immediately followed by another
wait. This case is suprisingly common, so this patch helps
generate much cleaner output without breaking the cases
where the 0ns wait is actually required (e.g. to implement
non-blocking assignment properly).
2008-08-05 11:02:36 +01:00
c849dfeec4
Add XNOR logic device
2008-08-05 10:45:01 +01:00
8d7b03576c
Correctly implement unary XNOR
...
Forgot to negate the output.
2008-08-05 10:38:43 +01:00
72019959a8
Translate some ternary expressions to if statements
...
This re-implements some earlier functionality where
ternary expressions on an assignment RHS are translated
to an if statement.
2008-08-03 15:47:32 +01:00
9565ea1034
Add some whitespace above component instantiations
2008-08-03 14:50:13 +01:00
49a2693357
Add file / line number information to functions
2008-08-03 14:46:57 +01:00
10a5ca199d
Add file / line number comments to instantiations
2008-08-03 14:38:08 +01:00
c2f622327f
Use ivl_scope_def_* for definition file/line numbers
2008-08-03 14:34:41 +01:00
0e2628a3fb
Minimal implementation of IVL_LPM_MUX
...
This handles the (common) case of the select being only
1 bit wide. Implemented as a concurrent assignment with
a `when' clause.
2008-08-03 12:46:50 +01:00
45dfa28dba
Remember signal pin a nexus was attached to
...
Also modify nexus_to_var_ref to set the correct array
offset when the signal is an array (the offset comes
from the pin).
2008-08-03 11:41:26 +01:00
c8cbac58f5
Add forward declarations for functions
...
This patch adds a forward declaration for every user funciton.
This fixes VHDL compile problems if a function calls another
before it has been declared.
2008-08-03 10:50:31 +01:00
c1b5424ca6
Implement assignment with multiple lvals
...
Multiple lvals are implemented by first assigning the complete
RHS to a temporary, and then assigning each lval in turn as
bit-selects of the temporary
2008-08-02 18:40:24 +01:00
c706c94e38
Generate a vhdl_var_ref for every assignment lval
...
This completes the refactoring of make_assignment
necessary to implement multiple lvals.
2008-08-02 18:20:18 +01:00
fad8abee34
Start refactoring make_assignment for multiple lvals
...
This patch lifts the RHS generating code out of the
lval-specific code and sticks a loop around the lvals.
2008-08-02 16:38:44 +01:00
9448c5939c
Always user Ternary_* support functions for ternary assignments
...
Previously the code generator expanded ternary assignments to
and `if' statement. This patch replaces that with a single assignment
and a call to a Ternary_* support function. This will make it
much easier to support multiple lvals later.
2008-08-02 15:46:36 +01:00
752a90dc2f
Insert blank line before VHDL process in output
2008-08-02 10:45:38 +01:00
a60216ec15
Use ivl_process_* functions for file/line number information
2008-08-02 10:44:03 +01:00
5d0df8d880
Change format of line file/line numbers
2008-08-02 10:42:00 +01:00
bb80b432e6
Add comments file/line number comments
...
Added to entities, architectures, and processes
2008-08-01 21:21:42 +01:00
e0834f7f38
Add NAND and NOR logic devices
2008-08-01 17:46:04 +01:00
a26d91557b
Add binary NAND and NOR operators
2008-08-01 17:42:26 +01:00
3f73c9bb54
Make sure argument to unary - is signed
2008-08-01 16:35:47 +01:00
09f3eb4a36
Don't bother calling reduction function if argument is std_logic
2008-08-01 16:27:55 +01:00
d21277f1b9
Tidy up whitespace in output
2008-07-31 21:17:49 +01:00
7b0f675785
Add check for sequential UDPs
2008-07-31 21:08:59 +01:00
db339b8fc3
Stub for UDP logic devices
2008-07-31 20:59:20 +01:00
baa2363e85
Split logic device code into separate file
2008-07-30 10:13:08 +01:00
e5b8abfb23
Remove debugging output
2008-07-29 21:15:51 +01:00
9f6f711f8d
Remove unused variable
2008-07-29 21:08:50 +01:00
9a5b7bb0b0
Connect signals together if joined in a nexus
2008-07-29 21:03:00 +01:00
eaf1cc9120
Fix assertion failure with arrayed signals
2008-07-29 19:47:17 +01:00
3bcd42dc8f
Fix case where logic device has no valid output
2008-07-29 19:39:20 +01:00
744fbed783
Finish re-writing nexus code
2008-07-29 19:33:40 +01:00
c9454b346e
Fix module3.12B
2008-07-29 19:04:41 +01:00
5ec2c37e7e
Get functions working again
2008-07-29 15:29:49 +01:00
25602e487d
Comment
2008-07-29 15:12:51 +01:00
e037ffd952
Create temporaries for LPM outputs
2008-07-29 15:09:58 +01:00
48c1a7982c
Make seen_nexus private
2008-07-29 14:24:04 +01:00
a842b327c7
Generate constant drivers as concurrent assignments
2008-07-29 14:02:05 +01:00
f8034d69ef
Fix constants in nexuses
2008-07-29 13:30:54 +01:00
d94dac28a8
Remove redundant lpm_output
2008-07-29 13:08:13 +01:00
680c6f0503
Make sure LPMs have valid inputs/outputs
2008-07-29 13:06:21 +01:00
39717989a8
Call set_active_entity in the right places
2008-07-29 13:04:29 +01:00
c26b7ce675
Port maps
2008-07-29 13:02:55 +01:00
c6f6ea7358
Instantiation working again
2008-07-29 12:21:19 +01:00
c0c838f1bc
Logic devices now working again
2008-07-29 12:11:44 +01:00
1a45e9164f
Find signal a logic device is connected to
2008-07-29 12:04:40 +01:00
8a5f129e56
Draw nexus in multiple passes
2008-07-29 12:00:26 +01:00
65c2ceb89d
Build entity hierarchy in separate stages
2008-07-29 11:01:02 +01:00
7a2e9c02cd
Simplify support function emitting code
2008-07-28 22:48:21 +01:00
f88415b1d7
Conversion of std_logic to integer
2008-07-28 22:46:39 +01:00
506a0ba7d6
Support repeat in concatenation
2008-07-28 21:46:19 +01:00
1d4914c590
Undo last commit
2008-07-28 13:04:30 +01:00
78028a3310
Fully support ternary expressions
2008-07-28 12:59:10 +01:00
b9cecbef64
Make sure LPM comparison result is std_logic not Boolean
2008-07-27 19:05:49 +01:00
8b32096e2a
Convert std_logic to Boolean in loop tests
2008-07-27 18:39:16 +01:00
ba462eb8b7
Merge branch 'vhdl' of git@github.com:nickg/iverilog into vhdl
2008-07-25 20:00:26 +01:00
5a09819729
Catch case of select expression on non-variable
2008-07-24 16:00:12 +01:00
d3296d4895
Refactor while/for loop code to use common base
2008-07-24 15:22:25 +01:00
39c9c54760
Add repeat statement
2008-07-24 14:52:06 +01:00
8bee5b1108
Add `forever' statement type
2008-07-24 14:30:10 +01:00
e4c2400eb2
Refactor the expression->time code into a single function
2008-07-23 16:18:49 +01:00
1409207def
Correctly indent case statements
2008-07-23 14:31:41 +01:00
30fdadc525
Support delays in logic devices
2008-07-23 13:40:42 +01:00
a5db0297b0
Unary minus
2008-07-22 15:44:29 +01:00
e25f946ac0
Merge branch 'vhdl' of file:///media/disk/data/iverilog/ into vhdl
2008-07-21 15:20:42 +01:00
2f4f075005
Typo
2008-07-21 15:20:40 +01:00
3ca85491ee
Unary AND and XOR
2008-07-20 16:41:57 +01:00
d8351ec1b2
Fix reduction OR in procedural code
2008-07-20 15:13:20 +01:00
77508b9afa
Reduction OR operator
2008-07-20 15:10:00 +01:00
38de6ebf3a
Compress support function definitions a bit
2008-07-19 21:04:52 +01:00
af3ee49f57
Refactor support function code a bit
2008-07-19 20:49:55 +01:00
0cb6ea34d7
Move type conversion code into a separate file
2008-07-19 15:23:47 +01:00
b6df73d3b9
Support functions for converting (un)signed -> boolean
2008-07-19 15:15:16 +01:00
2d79e1a2e0
Store the currently active entity
2008-07-19 14:45:00 +01:00
7b311b6adb
Translate internal delays in assignments
2008-07-18 14:47:35 +01:00
df4a380e42
Fix implementation of IVL_LPM_UFUNC
...
Function name was not correct.
2008-07-18 14:31:12 +01:00
6ff80e80a4
Catch case where (un)signed is converted to boolean
2008-07-18 12:30:24 +01:00
8b6b111541
Add IVL_LPM_CMP_EQ
2008-07-18 11:58:26 +01:00
fd8f01e317
Add IVL_LPM_CMP_GE
2008-07-18 11:56:00 +01:00
00317dd47f
Dummy implementation of $time
2008-07-18 11:50:05 +01:00
e9637f6d11
Generate synthesisable code for sequential processes
...
Whilst adding `wait until ...' at the end of every
process is a valid translation of the input, it is not
actually synthesisable in at least one commercial
synthesiser (XST). According to the XST manual the
correct template is to use `wait until ...' at the
start of sequential processes and `wait on ...'
(equivalent to `wait until ...' with 'Event on all
the signals) at the end of combinatorial processes.
This patch implements that.
2008-07-17 17:36:42 +01:00
1f9ed2c5ec
VHDL AST element for `wait on' statement
2008-07-17 17:23:21 +01:00
7677b59650
Make sure offset of IVL_LPM_ARRAY is integer
2008-07-17 16:41:34 +01:00
9cf4792d53
Translate array references in expressions
2008-07-17 14:47:10 +01:00
4d9f029000
Generate correct array bounds
2008-07-17 14:38:07 +01:00
9916686c24
Convert constant bits to integers
2008-07-17 14:29:56 +01:00
c86377790f
Automatically convert constant bit strings to integers
2008-07-17 14:26:35 +01:00
2a791bfb38
Assignment to arrays
2008-07-17 13:41:44 +01:00
1d3ac6bc1f
Generate VHDL array type declarations of Verilog arrays
2008-07-17 13:08:55 +01:00
3fa5a04947
Merge branch 'vhdl' into array
2008-07-17 12:01:09 +01:00
7c5b0f737c
Class for VHDL type declarations
2008-07-17 11:59:02 +01:00
c116808fdb
Remove duplicated code
2008-07-17 11:46:36 +01:00
553f3d77a9
Code for VHDL array type
2008-07-17 11:43:59 +01:00
642fbe9fc5
Correct check for arrays
2008-07-17 11:31:06 +01:00
395a2248d8
Make sure 1-bit constants are std_logic not (un)signed
2008-07-16 16:52:15 +01:00
be67cae29f
Add translation for IVL_ST_CASEX
2008-07-16 16:42:44 +01:00
f62a00bedb
Fix LPM binop with different signedness
...
Need to explicitly cast between signed/unsigned to
make sure both arguments have the same type or the
VHDL won't compile.
2008-07-16 16:20:08 +01:00
646a6056a2
Add IVL_LPM_CMP_EEQ support
2008-07-16 12:50:55 +01:00
4504c2bceb
Fix initialisation order bug with `if' statements
...
If an assignment appears inside an if statement branch
it could be incorrectly used as the signal's initial
value.
2008-07-16 12:11:00 +01:00
d343db34fd
Fix initialisation order
...
Initial processes set a magic flag in the code generator
which allows it to push constant assignments into the
VHDL signal initialisation and omit the assignment.
However, it should only do this if the signal has not
already been read (otherwise the previous read would
not get the undefined value as expected)
2008-07-16 12:00:11 +01:00
b5e12077b2
Fix assignment to lval slice
...
It was broken in yeserday's refactoring
2008-07-15 18:40:30 +01:00
f3753ea9ad
Add warning that arrays are not yet implemented
2008-07-15 18:09:18 +01:00
45e289d32d
Implement IVL_LPM_SHIFTL/R
2008-07-15 18:01:37 +01:00
40cabff44f
Leave blank line at end of function
2008-07-15 16:30:50 +01:00
a9c98ad5f2
Handle `if' with empty cond_true part
...
Fixes assertion failure with following statement:
if (foo)
begin
end
else
...
2008-07-15 14:26:19 +01:00
b8e758edf0
Refactor LPM code
2008-07-15 14:09:24 +01:00
0b48f69b4e
Tidy up blocking assignment code
2008-07-15 10:44:48 +01:00
d1e7e325b7
Remove redundant edge_detector function
2008-07-14 21:34:48 +01:00
75b1db0add
Fix assignment with ternary RHS
...
This was also broken in the last commit
2008-07-14 21:27:21 +01:00
6e965523a1
Fix PV assignment (was broken in last commit)
2008-07-14 21:09:19 +01:00
8589c0691b
Refactor assignment code
2008-07-14 21:04:09 +01:00
99ef8ec4f1
Simplify edge detector code
...
Now generates a `wait until' statement rather than a
sensitivity list.
2008-07-14 20:29:49 +01:00
d22c9a8b05
Simplify blocking assignment
...
Now generates 'wait for 0 ns' after non-blocking assignment
2008-07-14 19:54:45 +01:00
f84f50842c
Support bufif for tri1 nets
2008-07-14 19:13:11 +01:00
65720f49fe
Simple bufif cases
2008-07-14 19:00:58 +01:00
6243736481
Pull-up/pull-down logic devices
2008-07-14 12:04:20 +01:00
e331e4831b
Fix nexus_to_expr where nexus has IVL_LPM_SELECT_PV
2008-07-14 11:53:38 +01:00
78ee61558d
Remove redundant test
...
Signal is guaranteed to appear in arch_scope or its parent
by the surrounding `if' statement.
2008-07-13 15:27:07 +01:00
07c4ff7ea7
Add assertion about result of lpm_to_expr
2008-07-13 15:26:03 +01:00
e5422dddd2
Remove useless `ignore' param to nexus_to_expr
2008-07-13 15:24:35 +01:00
6af201ea03
Refactor nexus expansion functions.
...
Now a single function nexus_to_expr
2008-07-13 15:17:14 +01:00
27a40cfdcd
Constant assignments to outputs
...
If the Verilog source contained a continuous assignment
of a constant to an output, it would not be present in
the VHDL output. This patch generates a VHDL continous
assignment in these cases.
2008-07-13 13:02:17 +01:00
3bd480a375
Allow ouput to be read if connected to child output
...
If output P of A is connected to output Q of B (and A is
instantiated inside B) then VHDL does not allow B to read
the value of Q (also P), but Verilog does. To get around
this the output Q is mapped to P_Sig which is then connected
to P, this allows B to read the value of P/Q via P_Sig.
2008-07-13 12:41:02 +01:00
aa951af2b7
Change 'signdness' to 'signdness'
2008-07-10 19:27:17 +01:00
55747bf79d
Refactor signdness changing code into a single function
...
This is the code that generated calls to signed/unsigned in
the VHDL output.
2008-07-08 13:07:11 +01:00
1cd7689d03
Fix casting with signed/unsigned expressions
...
Previously the code generator tried to infer the VHDL types. Now it
takes a much more dumb approach and forces the VHDL type to be
the same as the ivl type (derived from ivl_expr_signed and
ivl_expr_width) in the expression tree. This works much better :-)
2008-07-08 12:58:50 +01:00
bd5cc96956
Correct vector sizes for bit select
2008-07-08 00:20:31 +01:00
a0dbb1aa5d
Fix more bugs in part selects
2008-07-07 21:45:27 +01:00
4777966b4c
Bit select bug fixes
2008-07-07 21:19:59 +01:00
860a74ddd8
Allow LPMs in port maps
2008-07-07 20:41:29 +01:00
2bb645e0bc
Refactor LPM code to allow lpm->expr function
2008-07-07 19:46:18 +01:00
47db80315c
Add sign extension LPM
2008-07-07 19:27:52 +01:00
0348664512
Correctly determine VHDL type of LHS of part select
2008-07-07 16:35:39 +01:00
3987e0753d
Fix case where booleans are compared against vectors
2008-07-07 16:31:27 +01:00
6b73cc39a5
Add Active_High support func and fix LPM part select
2008-07-07 16:17:54 +01:00
b0de1a8d7e
Implement part select for LHS of assignment
2008-07-07 16:11:45 +01:00
37fe6e4219
Dummy implementation of IVL_LO_BUF*
2008-07-07 15:49:51 +01:00
89cdbf63be
Reduction LPM types
2008-07-07 15:45:20 +01:00
7f955cc070
Move the VHDL support package
2008-07-07 15:36:13 +01:00
4db5b9d7ed
Add unary OR/NOR
...
These are currently implemented with reference to an external
Reduce_OR function
2008-07-07 15:23:57 +01:00
Nick Gasson
Larry Doolittle
Stephen Williams