This is a fix for pr2555831. A separate entity/architecture pair is
generated for each module that is instantiated with a unique
parameter combination.
For example:
-- Generated from Verilog module child (vhdl_tests/generics.v:30)
-- MY_VALUE = 3
entity child is
To make it clear which values were used for this entity.
This changes the implementation of $display/$write to use VHDL
report statements rather the the std.textio functions. The code
produced is simpler and more like what a real VHDL designed would
write. However it no longer exactly matches the Verilog output as
most VHDL simulators prepend the text with simulation time, entity
name, severity level, etc. There is a corresponding change in
ivtest to support this.
Previous we generated a "wait for 0 ns" statement after
every blocking assignment that wasn't the last statement
in the process. While this implements the Verilog semantics,
it generates excessive waits, and cannot usually be synthesised.
This patch only generates "wait for 0 ns" statements when it
cannot be avoid (e.g. when the target of a blocking assignment
is read in the same process).
An example:
begin
x = 5;
if (x == 2)
y = 7;
end
Becomes:
x <= 5;
wait for 0 ns; -- Required to implement assignment semantics
if x = 2 then
y <= 7; -- No need for wait here, not read
-- wait for 0 ns (previously)
end if;
E.g. $signed(x) > y with x, y different sizes should be
resize(signed(x), N) > y
Not
signed(resize(x, N)) > y
As this does not treat the sign bit correctly. Was causing
the signed5 test to fail.
The functions (malloc, free, etc.) that used to be provided in
malloc.h are now provided in cstdlib for C++ files and stdlib.h for
C files. Since we require a C99 compliant compiler it makes sense
that malloc.h is no longer needed.
This patch also modifies all the C++ files to use the <c...>
version of the standard C header files (e.g. <cstdlib> vs
<stdlib.h>). Some of the files used the C++ version and others did
not. There are still a few other header changes that could be done,
but this takes care of much of it.
This patch updates all the Makefile.in files and configure.in
as follows:
Do not use the -Wall warning flag when using the SunPro compiler.
The SunPro compiler uses -xMD instead of -MD.
There are still more fixes needed before Icarus will compile
on OpenSolaris.
This patch cleans up some style issues: no need to check that a value
is defined before freeing or deleting it, use C++ style casts, make
sure to NULL terminate strncpy(), empty() is faster than size() for
size == 0 or size >= 0 checks, re-scope some variables, etc.
Newer versions of GHDL seem to be stricter when checking this than
older versions. ModelSim still accepts an incomplete with-select,
however.
This patch makes the output 'U' if none of the conditions match.
The function draw_scope was extracting the input/output parameters
just by looking at the (unordered) list of signals in the function
scope rather than using the ivl_scope_ports list.
The Cygwin compiler is a bit picky. This patch adds some casts
to remove compilation warnings. In the past I have had warnings
off because of problems with the STL, but we may as well get
rid of the warnings we can. It also does not recognize that an
assert(0) or assert(false) ends a routine so it complains about
no return at end of function or variables not being defined.
These explicit dependencies are not normally needed (because they
are covered by automatic dependency generation) but when the "-jN"
flag is passed to gmake, they help gmake schedule parallel builds.
(cherry picked from commit 5479aaf721)
Try to put all the version stamps into common version_base.h
and version_stamp.h header files. All the source programs then
get their version from these header files.
Also handle the version stamps in the man pages by using the
version_*.h header file contents to edit the version strings
in the man page title bar markers.
Minor fixes and code reorganization to remove a few more issues
that cppcheck is complaining about. It has a few false warnings
and some issues that need more investigation.
The local "memory.h" file is no longer used in V0.9 or development,
so it does not need to be included in vvp/codes.h. The VHDL target
does not use the system <memory.h> header file so there is no need
to have a define for it in the vhld_config.h.in file.
- Add missing dependency of configure on aclocal.m4.
- Remove config stamp files in make distclean (and fix another for
loop in base make distclean that I missed)
- Add stamp files to .gitignore
Use the time stamp file technique recommended by the autoconf manual
to prevent unneccesary rebuilds because of an unchanged config.h.
Uses the automake trick of generating the stamp files in the
_AC_AM_CONFIG_HEADER_HOOK macro instead of littering the source
directory with stamp-h.in files.
Add an extra ./config.status run after ./config.status --recheck
because with --recheck it doesn't actually try to remake the generated
files (and thus doesn't make the timestamp files). Thus without the
extra run, each stamp-*-h target would need to independently run
./config.status to make sure it wasn't changed by the configuration
change.
An orthogonal fix of how config.status is called in subdirectories.
When in a subdirectory and config.status is called with
../config.status and $(srcdir) is a relative path, config.status gets
confused. Fixed by replacing '../config.status --file=Makefile.in'
with 'cd ..; ./config.status --file=<dir>/Makefile.in'
It was documented that a IVL_LPM_CONCAT would use _size() instead
of _selects(). This patch adds the functionality to _size() and
converts all the Icarus provided code generators to use _size().
_select() will be kept for compatibility in V0.9.
The newer mkinstalldirs can handle paths that have spaces in them.
While I'm at it, I also updated the Makefiles so that installation
can also work to DESTDIR directories that have spaces.
This patch adds code to generate process-local variables
for scopes of type IVL_SCT_BLOCK. This also handles using
the correct assignment operator (:=) for the local VHDL
variables.
This avoids generating invalid VHDL signal names in the
following cases:
- The name begins or ends with an underscore
- The name contains two consecutive underscores
- The name is the same as a component declaration
- The name differs from another only in case
This fixes a bug where temporary variables could be declared
more than once.
It also takes out a debugging print statement I accidentally
left in the last patch.
I forgot to modify the LPM generating code with the
last patch. This *should* now always ensure a signal
is readable before code is generated to read from it.
This patch corrects several bugs with the generation of
VHDL `buffer' ports. The code generator should now
generate a buffer only if the port needs to be read inside
the architecture, otherwise it will stay `out'.
This also correct a bug where an output port is connected
directly to the output of an instantiated component. Generating
`buffer's would work here, but a more idiomatic VHDL approach is
to declare an intermediate signal which both outputs are connected
to. This is implemented in the patch (fixes the regression of
readout.v in the testsuite).
Noticed this as part of the test case for pr2516774b. Under some
circumstances the input arguments would be cast to the wrong type.
This patch ensures that all the arguments have the correct type.
This patch changes the output of VHDL unsigned bit strings
which are 4, 8, 16, 32, or 64 bits to use VHDL hex string
constants.
So the following:
"00000001"
Becomes
X"01"
Which is much easier to read
This is a fix for pr2527366 where draw_nexus would sometimes
generate code to drive an input from in an input (where they
should have been left unconnected)
The patch for pr2516774 exposed a bug which caused
always3.1.8A to fail. This patch corrects that.
The test to decide when to use a sensitivity list
rather than an explicit wait statement wasn't tight enough.
This patch is a fix for pr2516774.
The idea is to generate a local variable inside
a function whenever an argument is assigned to. The
variable has an initial value of the argument value
and is used in its place for the remainder of the
function. This patch also handles the case where the
argument is assigned to inside a while loop.
Previously the VHDL code generator managed memory for
the AST objects by requiring that each AST element be
responsible for deleting its children. The disadvantages
of this are that it's quite easy to accidentally leak
memory by forgetting to delete a child, and no AST pointers
may be shared by multiple parents (or we'd end up with
double-deletes) -- this results in unnecessary copies of
objects being made.
There's no real need for fine-grained memory management of
AST objects since once they're allocated they tend to
persist until the code generator is about to terminate, when
they should all be freed.
This patch provides a custom new/delete operator for
vhdl_element which logs the vhdl_element objects allocated
in a std::vector (after calling the default operator new).
Once the code generator is finished a single free_all_objects
call deletes all the AST objects in one go. The custom delete
operator is required so that we can still explicitly deallocate
vhdl_element objects before the code generator completes.
There are also some allocation statistics printed at the end
when -pdebug=1 is specified.
This patch generates VHDL sensitivity lists for sequential
as well as combinatorial processes which do not contain
a wait statement. Otherwise it falls back on the original
wait-on/until behaviour.
This should make the generated VHDL more acceptable to
synthesisers.
This patch generates a sensitivity list for combinatorial
VHDL processes if they don't contain a wait statement, and
a wait-on statement if they do contain another wait statement.
This should help synthesisers correctly identifier
level-sensitive latches.
In particular this improves the code generated for flip-flops
so the output can be synthesised with certain tools (e.g. Synopsis).
See the comments above draw_synthesisable_wait for more details.
Rather then spread VERSION= defines throughout all the makefiles, put
the base version in version_base.in. Use that to generate a version.h
that includes the base version as well as the detailed version.
This reverts commit 31d67fcd3e.
The concensus has been that this causes too many build problems in
the general case and what is needed instead is a way to turn on the
extra warnings for developers only.
The code base is almost shadow-free now, so this won't add much noise to the compiles.
Problems I know about:
lxt{,2}_write.c: patch sent upstream
cflexor.c: exposes gray area of name space boundary
Finish cleaning up shadowed variables, flagged by turning on -Wshadow.
No intended change in functionality. Patch looks right, and is tested
to compile and run on my machine. No regressions in the test suite.
This is the end of the simple, coordination-free patches.
The remaining shadows are special cases that will need extra attention.
Previously only the X/Z state of the label expression was
considered to be a don't care. This patch adds that
functionality to the conditional expression as well.
This patch cleans up the Makefile.in files.
We only need to delete config.log in the lower directories.
We reference the *.in files at $(srcdir)/
We need to make distclean for the tgt-(fpga,pal,verilog) directories.
This is to cleanup the Makefile.
Add some missing "rm -r f dep"
This patch adds support for concatenation/repetition, signals and
part and bit select of signals for casez/x expression labels.
These along with the original constants can be mixed in almost any
order. Only constant selects are currently supported.
Specifying -pdepth=N only outputs entities that correspond
to Verilog modules found at depth < N in the hierarchy.
Setting -pdepth=0 (the default) outputs all entities.
This is for feature request 2391457
Collapse all the configure checks to a single configure script in
the root of the source tree. This makes the configure process run
a lot faster, expecially on Windows systems that are slower in general.
This patch optimises away straight line sequences like:
wait for 0 ns;
wait for X ns;
to:
wait for X ns;
This tidies up the output a bit.
It also has the effect of removing all code from initial
processes where the assignments have been extracted as
VHDL signal intialisers. (c.f. pr2391337)
This prints out an error message rather than crashing out with
an assertion failure when a function assigns to a non-local
variable, which cannot be done in VHDL.
This changes the assignment statement generator so that
each VHDL declaration "knows" which type of assignment
statement can/should be used on (i.e. signals must be
assigned with <=). This will help us catch cases when
we try to use, for example, := with signals. This occurs
in pr2362211 where we try to assign to a signal within
a function (where only := can be used).
If a module's input was connected to a nexus that contained
a constant driver. That constant would be incorrectly generated
as an assignment to the input *inside* the child module (instead
of an assignment inside the instantiating module).
With this small patch, building succeeds with Debian's current gcc-snapshot,
gcc (Debian 20081130-1) 4.4.0 20081130 (experimental) [trunk revision 142292]
That gcc also warns about the remaining #idents in
vvp/concat.cc
vvp/dff.h
The resulting build shows some regressions in the test suite, that
I am still investigating. The patch does not break building, or show
test suite regressions, with gcc-4.3.
Signals of width 1 are declared in VHDL as std_logic, as this
is the usual way to represent them. Unfortunately, we cannot
distinguish between
reg [0:0] a;
and
reg a;
This patch avoids trying to slice a std_logic so a[0] is equivalent to a.
This patch removes the CVS ident information from the Makefile.in
files it also puts in the current version 0.9.devel for the default
VERSION definition. This is normally passed down, but a local make
will use the value from the local Makefile. This will eventually be
replaced with a file based version to give us just one place to
reliably modify the version.
This patch updates the GNU address in the -V output, adds the
VERSION_TAG info to the tgt-vvp back end and adds the whole -V
hook to the tgt-vhdl back end.
Fix for pr2224949
The compiler generates a concatenation LPM to zero-pad ports when the
signal widths don't match up. However, when the VHDL generator generated
the input signals to this LPM it incorrectly sized them to be the width
of the result.
The VHDL converter erroneously treated a casez and casex exactly
the same. In reality a casez compares a 'x' value (it is not a
don't care). It also adds support for a full don't care case by
just returning True for the condition.
This configure option causes the installed commands to have
a suffix string that makes them distinct from other versions
that also have a suffix string. This allows for multiple
installed versions of Icarus Verilog.
Also, move installed C/C++ header files into a subdirectory of
their own under the target include directory, to make clearer
the purpose and source of those files.
VHDL can't select bits from arbitrary expression so sometimes
translating IVL_EX_SELECT would fail. This is easily fixed by
replacing the select with a shift in this instance (and the
resizing)
make_safe_name now makes sure a VHDL signal is never given a
name that conflicts with any reserved words. If it does, we
just prepend VL_.
(This code was already present, but the full list of reserved
words wasn't.)
Continue cleaning up shadowed variables, flagged by turning on -Wshadow.
No intended change in functionality. This patch set covers the tgt-vhdl
directory, and was tested by Nick.
Nick Gasson
Cary R
Stephen Williams
Jared Casper
Larry Doolittle