 mrg
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ef310970bf
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Use new Google PDK lib
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2020-10-12 15:46:11 -07:00 |
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mrg
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8d5db50062
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Fix missing update for left RBL offset
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2020-10-08 16:40:53 -07:00 |
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mrg
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b0b15e8151
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Fix indent bug that failed to create rbl wl pin labels.
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2020-10-08 15:28:01 -07:00 |
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mrg
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01fe02bd90
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Fixes to replica bitline array.
Copy pasta error for right dummy column offset.
Put end_caps in try/except block.
PEP 8 formatting
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2020-10-08 14:53:44 -07:00 |
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mrg
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03e1b9c50d
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Clean up custom cells
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2020-10-08 14:22:09 -07:00 |
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mrg
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8a9bf2d4f0
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Remove hardcoded structure
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2020-10-08 14:07:46 -07:00 |
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mrg
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3c2e8754e0
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Search all shapes for boundary rather than specify structure
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2020-10-08 14:04:19 -07:00 |
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mrg
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43d2058b3c
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Remove temp files
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2020-10-08 10:35:27 -07:00 |
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mrg
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76ab48def5
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Remove temp files
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2020-10-08 10:33:45 -07:00 |
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mrg
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9a0fc8047b
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Remove diff
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2020-10-08 09:53:52 -07:00 |
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mrg
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7076c376e0
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Remove log from branch
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2020-10-08 09:53:17 -07:00 |
|
 jcirimel
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1e7ae06b7e
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fix extra wl in col end, work on bring wl pins out to row end array, TODO: mirror alternating row end
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2020-10-08 05:32:03 -07:00 |
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jcirimel
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d40c3588ed
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no wl for col end
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2020-10-08 03:34:16 -07:00 |
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jcirimel
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4a1a7e637e
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merge in dev
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2020-10-07 11:54:07 -07:00 |
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mrg
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483f6b187c
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RBL driver supply location differs for sky130 and other techs
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2020-10-06 16:47:32 -07:00 |
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mrg
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c2629edc1b
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Allow 16-way column mux
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2020-10-06 16:27:02 -07:00 |
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mrg
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27d921d2db
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Fix run-time bug for duplicate instance check
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2020-10-06 16:26:35 -07:00 |
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mrg
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ba432669a1
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Add various riscv examples
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2020-10-06 16:25:44 -07:00 |
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jcirimel
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13e2a9f5f7
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fix missed self.left_rbl refactor
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2020-10-06 05:11:15 -07:00 |
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jcirimel
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888646cdf9
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merge in wlbuf and begin work on 32kb memory
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2020-10-06 05:03:59 -07:00 |
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mrg
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a145a37cf7
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PEP8 fixes in regress.py
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2020-10-05 15:56:12 -07:00 |
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mrg
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cb35c0aff4
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Add command line -j option for number of threads.
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2020-10-05 15:49:00 -07:00 |
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mrg
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da83824a70
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Merge branch 'wlbuffer' into dev
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2020-10-05 15:33:54 -07:00 |
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mrg
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c4952ca8be
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Skip full sram pex test too slow
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2020-10-05 13:51:20 -07:00 |
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mrg
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9fe6358569
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Change .spinit to .spiceinit
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2020-10-05 13:50:04 -07:00 |
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jcirimel
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5246d0a93b
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track s8 customs modules
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2020-10-05 12:10:44 -07:00 |
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mrg
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4a58f09c1c
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Use 4x16 decoder with dual port bitcell in tests.
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2020-10-05 10:52:56 -07:00 |
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mrg
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c06b02e6fc
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Rename single_level_column_mux to just column_mux
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2020-10-05 08:56:51 -07:00 |
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mrg
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f8146e3f69
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Add decoder4x16
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2020-10-02 15:52:09 -07:00 |
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mrg
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64cc620440
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Add sram pex test
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2020-10-02 14:55:10 -07:00 |
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mrg
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1fc4040607
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Add pand4 and pnand4
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2020-10-02 14:54:12 -07:00 |
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mrg
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a62b82128c
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Skip riscv func test because too slow
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2020-10-02 13:33:58 -07:00 |
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mrg
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1e24b780bb
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Initial pex sram test.
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2020-10-02 13:32:52 -07:00 |
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mrg
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b32c123dab
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PEP8 cleanup. Un-hard-code bitcell layers. Remove dead variable.
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2020-10-01 11:10:18 -07:00 |
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mrg
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18c8ad265e
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Unique name for sram channel routes
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2020-10-01 09:55:34 -07:00 |
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mrg
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aaa36bf5cf
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Default to 2 threads only
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2020-10-01 09:55:17 -07:00 |
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mrg
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d315ff18e5
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Add num_threads to options. PEP8 cleanup.
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2020-10-01 08:07:03 -07:00 |
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mrg
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b81cdab0d6
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Use unique instance names for channel routes.
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2020-10-01 07:43:06 -07:00 |
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mrg
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8ce23d7f17
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Provide unique WL driver instance name
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2020-10-01 07:17:32 -07:00 |
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mrg
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bd125e2ed3
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Check for duplicate instance names.
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2020-10-01 07:17:16 -07:00 |
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|
Matt Guthaus
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2b475670f7
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Check for failed result in functional simulation
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2020-09-30 12:40:07 -07:00 |
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|
Matt Guthaus
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112d57d90a
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Enable riscv tests
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2020-09-30 12:39:40 -07:00 |
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mrg
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f4e6a8895b
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Update riscv unit test
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2020-09-30 08:50:58 -07:00 |
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jcirimel
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7cbf456a4f
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sky130 rba done
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2020-09-30 07:34:05 -07:00 |
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mrg
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b147e8485c
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PEP8 formatting
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2020-09-29 16:52:27 -07:00 |
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mrg
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066570bfeb
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Fix length of write driver
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2020-09-29 16:51:55 -07:00 |
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mrg
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8e908f016e
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PEP8 formatting
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2020-09-29 13:43:59 -07:00 |
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mrg
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bca69b24e3
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Optional number of functional cycles
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2020-09-29 13:43:54 -07:00 |
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mrg
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54890a8d77
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Add new golden data
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2020-09-29 13:43:34 -07:00 |
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mrg
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449a4c2660
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Exclude bitcells in other local areas not of interest
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2020-09-29 12:15:42 -07:00 |
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