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base
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Use unique instance names for channel routes.
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2020-10-01 07:43:06 -07:00 |
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bitcells
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update to new metal stack names
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2020-07-31 05:27:19 -07:00 |
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characterizer
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Change .spinit to .spiceinit
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2020-10-05 13:50:04 -07:00 |
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custom
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Use 4x16 decoder with dual port bitcell in tests.
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2020-10-05 10:52:56 -07:00 |
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drc
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PEP8 cleanup
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2020-04-15 11:24:28 -07:00 |
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example_configs
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Add various riscv examples
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2020-10-06 16:25:44 -07:00 |
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modules
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Merge branch 'wlbuffer' into dev
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2020-10-05 15:33:54 -07:00 |
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pgates
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Use 4x16 decoder with dual port bitcell in tests.
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2020-10-05 10:52:56 -07:00 |
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sram
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Initial pex sram test.
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2020-10-02 13:32:52 -07:00 |
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tests
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PEP8 fixes in regress.py
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2020-10-05 15:56:12 -07:00 |
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verify
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Initial pex sram test.
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2020-10-02 13:32:52 -07:00 |
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debug.py
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DRC/LVS and errors fixes.
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2020-06-30 07:16:05 -07:00 |
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openram.py
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Add words_per_row and others in config file.
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2020-07-13 12:37:56 -07:00 |
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sram_factory.py
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Auto-generate port dependent cell names.
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2020-06-05 15:09:22 -07:00 |
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