mrg 43d2058b3c Remove temp files

2020-10-08 10:35:27 -07:00

..

base

no wl for col end

2020-10-08 03:34:16 -07:00

bitcells

fix replica bitcell col

2020-09-23 00:36:08 -07:00

characterizer

Change .spinit to .spiceinit

2020-10-05 13:50:04 -07:00

custom

fix extra wl in col end, work on bring wl pins out to row end array, TODO: mirror alternating row end

2020-10-08 05:32:03 -07:00

datasheet

…

drc

PEP8 cleanup

2020-04-15 11:24:28 -07:00

example_configs

merge in dev

2020-10-07 11:54:07 -07:00

gdsMill

single port progess

2020-09-14 18:11:38 -07:00

modules

fix extra wl in col end, work on bring wl pins out to row end array, TODO: mirror alternating row end

2020-10-08 05:32:03 -07:00

pgates

merge in dev

2020-10-07 11:54:07 -07:00

riscv

single port progess

2020-09-14 18:11:38 -07:00

router

Changes to simplify metal preferred directions and pitches.

2020-05-10 11:32:45 -07:00

sram

Allow 16-way column mux

2020-10-06 16:27:02 -07:00

tests

Remove temp files

2020-10-08 10:35:27 -07:00

verify

Initial pex sram test.

2020-10-02 13:32:52 -07:00

debug.py

DRC/LVS and errors fixes.

2020-06-30 07:16:05 -07:00

gen_stimulus.py

Fixed errors in extra rows characterization

2020-03-22 20:54:49 +00:00

globals.py

Add command line -j option for number of threads.

2020-10-05 15:49:00 -07:00

Makefile

…

openram.py

Add words_per_row and others in config file.

2020-07-13 12:37:56 -07:00

options.py

Add command line -j option for number of threads.

2020-10-05 15:49:00 -07:00

run_profile.sh

…

sram_factory.py

Auto-generate port dependent cell names.

2020-06-05 15:09:22 -07:00

view_profile.py

Remove some flake8 errors/warnings.

2019-10-02 23:26:02 +00:00