mirror of https://github.com/VLSIDA/OpenRAM.git
Add pand4 and pnand4
This commit is contained in:
mrg
parent
8e908f016e
commit
1fc4040607
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import debug
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from vector import vector
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import pgate
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from sram_factory import factory
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class pand4(pgate.pgate):
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"""
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This is a simple buffer used for driving loads.
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"""
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def __init__(self, name, size=1, height=None, vertical=False, add_wells=True):
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debug.info(1, "Creating pand4 {}".format(name))
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self.add_comment("size: {}".format(size))
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self.vertical = vertical
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self.size = size
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# Creates the netlist and layout
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super().__init__(name, height, add_wells)
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def create_netlist(self):
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self.add_pins()
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self.create_modules()
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self.create_insts()
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def create_modules(self):
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# Shield the cap, but have at least a stage effort of 4
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self.nand = factory.create(module_type="pnand4",
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height=self.height,
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add_wells=self.vertical)
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# Add the well tap to the inverter because when stacked
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# vertically it is sometimes narrower
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self.inv = factory.create(module_type="pdriver",
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size_list=[self.size],
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height=self.height,
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add_wells=self.add_wells)
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self.add_mod(self.nand)
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self.add_mod(self.inv)
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def create_layout(self):
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if self.vertical:
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self.height = 2 * self.nand.height
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self.width = max(self.nand.width, self.inv.width)
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else:
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self.width = self.nand.width + self.inv.width
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self.place_insts()
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self.add_wires()
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self.add_layout_pins()
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self.route_supply_rails()
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self.add_boundary()
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self.DRC_LVS()
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def add_pins(self):
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self.add_pin("A", "INPUT")
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self.add_pin("B", "INPUT")
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self.add_pin("C", "INPUT")
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self.add_pin("D", "INPUT")
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self.add_pin("Z", "OUTPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def create_insts(self):
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self.nand_inst = self.add_inst(name="pand4_nand",
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mod=self.nand)
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self.connect_inst(["A", "B", "C", "D", "zb_int", "vdd", "gnd"])
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self.inv_inst = self.add_inst(name="pand4_inv",
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mod=self.inv)
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self.connect_inst(["zb_int", "Z", "vdd", "gnd"])
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def place_insts(self):
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# Add NAND to the right
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self.nand_inst.place(offset=vector(0, 0))
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if self.vertical:
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# Add INV above
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self.inv_inst.place(offset=vector(self.inv.width,
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2 * self.nand.height),
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mirror="XY")
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else:
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# Add INV to the right
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self.inv_inst.place(offset=vector(self.nand_inst.rx(), 0))
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def route_supply_rails(self):
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""" Add vdd/gnd rails to the top, (middle), and bottom. """
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self.add_layout_pin_rect_center(text="gnd",
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layer=self.route_layer,
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offset=vector(0.5 * self.width, 0),
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width=self.width)
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# Second gnd of the inverter gate
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if self.vertical:
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self.add_layout_pin_rect_center(text="gnd",
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layer=self.route_layer,
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offset=vector(0.5 * self.width, self.height),
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width=self.width)
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if self.vertical:
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# Shared between two gates
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y_offset = 0.5 * self.height
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else:
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y_offset = self.height
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self.add_layout_pin_rect_center(text="vdd",
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layer=self.route_layer,
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offset=vector(0.5 * self.width, y_offset),
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width=self.width)
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def add_wires(self):
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# nand Z to inv A
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z1_pin = self.nand_inst.get_pin("Z")
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a2_pin = self.inv_inst.get_pin("A")
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if self.vertical:
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route_layer = "m2"
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self.add_via_stack_center(offset=z1_pin.center(),
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from_layer=z1_pin.layer,
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to_layer=route_layer)
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self.add_zjog(route_layer,
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z1_pin.uc(),
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a2_pin.bc(),
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"V")
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self.add_via_stack_center(offset=a2_pin.center(),
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from_layer=a2_pin.layer,
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to_layer=route_layer)
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else:
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route_layer = self.route_layer
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mid1_point = vector(z1_pin.cx(), a2_pin.cy())
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self.add_path(route_layer,
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[z1_pin.center(), mid1_point, a2_pin.center()])
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def add_layout_pins(self):
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pin = self.inv_inst.get_pin("Z")
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self.add_layout_pin_rect_center(text="Z",
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layer=pin.layer,
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offset=pin.center(),
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width=pin.width(),
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height=pin.height())
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for pin_name in ["A", "B", "C"]:
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pin = self.nand_inst.get_pin(pin_name)
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self.add_layout_pin_rect_center(text=pin_name,
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layer=pin.layer,
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offset=pin.center(),
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width=pin.width(),
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height=pin.height())
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def analytical_delay(self, corner, slew, load=0.0):
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""" Calculate the analytical delay of DFF-> INV -> INV """
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nand_delay = self.nand.analytical_delay(corner,
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slew=slew,
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load=self.inv.input_load())
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inv_delay = self.inv.analytical_delay(corner,
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slew=nand_delay.slew,
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load=load)
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return nand_delay + inv_delay
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@ -133,7 +133,6 @@ class pnand3(pgate.pgate):
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# This is the extra space needed to ensure DRC rules
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# to the active contacts
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nmos = factory.create(module_type="ptx", tx_type="nmos")
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extra_contact_space = max(-nmos.get_pin("D").by(), 0)
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def create_ptx(self):
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"""
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@ -0,0 +1,372 @@
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import pgate
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import debug
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from tech import drc, parameter, spice
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from vector import vector
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import logical_effort
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from sram_factory import factory
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from globals import OPTS
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import contact
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class pnand4(pgate.pgate):
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"""
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This module generates gds of a parametrically sized 4-input nand.
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This model use ptx to generate a 4-input nand within a cetrain height.
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"""
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def __init__(self, name, size=1, height=None, add_wells=True):
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""" Creates a cell for a simple 3 input nand """
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debug.info(2,
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"creating pnand4 structure {0} with size of {1}".format(name,
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size))
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self.add_comment("size: {}".format(size))
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# We have trouble pitch matching a 3x sizes to the bitcell...
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# If we relax this, we could size this better.
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self.size = size
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self.nmos_size = 2 * size
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self.pmos_size = parameter["beta"] * size
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self.nmos_width = self.nmos_size * drc("minwidth_tx")
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self.pmos_width = self.pmos_size * drc("minwidth_tx")
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# FIXME: Allow these to be sized
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debug.check(size == 1,
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"Size 1 pnand4 is only supported now.")
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self.tx_mults = 1
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if OPTS.tech_name == "sky130":
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self.nmos_width = self.nearest_bin("nmos", self.nmos_width)
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self.pmos_width = self.nearest_bin("pmos", self.pmos_width)
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# Creates the netlist and layout
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super().__init__(name, height, add_wells)
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def add_pins(self):
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""" Adds pins for spice netlist """
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pin_list = ["A", "B", "C", "D", "Z", "vdd", "gnd"]
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dir_list = ["INPUT", "INPUT", "INPUT", "INPUT", "OUTPUT", "POWER", "GROUND"]
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self.add_pin_list(pin_list, dir_list)
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def create_netlist(self):
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self.add_pins()
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self.add_ptx()
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self.create_ptx()
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def create_layout(self):
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""" Calls all functions related to the generation of the layout """
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self.setup_layout_constants()
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self.place_ptx()
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if self.add_wells:
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self.add_well_contacts()
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self.route_inputs()
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self.route_output()
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self.determine_width()
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self.route_supply_rails()
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self.connect_rails()
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self.extend_wells()
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self.add_boundary()
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def add_ptx(self):
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""" Create the PMOS and NMOS transistors. """
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self.nmos_center = factory.create(module_type="ptx",
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width=self.nmos_width,
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mults=self.tx_mults,
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tx_type="nmos",
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add_source_contact="active",
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add_drain_contact="active")
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self.add_mod(self.nmos_center)
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self.nmos_right = factory.create(module_type="ptx",
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width=self.nmos_width,
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mults=self.tx_mults,
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tx_type="nmos",
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add_source_contact="active",
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add_drain_contact=self.route_layer)
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self.add_mod(self.nmos_right)
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self.nmos_left = factory.create(module_type="ptx",
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width=self.nmos_width,
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mults=self.tx_mults,
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tx_type="nmos",
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add_source_contact=self.route_layer,
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add_drain_contact="active")
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self.add_mod(self.nmos_left)
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self.pmos_left = factory.create(module_type="ptx",
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width=self.pmos_width,
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mults=self.tx_mults,
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tx_type="pmos",
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add_source_contact=self.route_layer,
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add_drain_contact=self.route_layer)
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self.add_mod(self.pmos_left)
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self.pmos_center = factory.create(module_type="ptx",
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width=self.pmos_width,
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mults=self.tx_mults,
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tx_type="pmos",
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add_source_contact=self.route_layer,
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add_drain_contact=self.route_layer)
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self.add_mod(self.pmos_center)
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self.pmos_right = factory.create(module_type="ptx",
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width=self.pmos_width,
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mults=self.tx_mults,
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tx_type="pmos",
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add_source_contact=self.route_layer,
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add_drain_contact=self.route_layer)
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self.add_mod(self.pmos_right)
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def setup_layout_constants(self):
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""" Pre-compute some handy layout parameters. """
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# Compute the overlap of the source and drain pins
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self.ptx_offset = self.pmos_left.get_pin("D").center() - self.pmos_left.get_pin("S").center()
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# This is the extra space needed to ensure DRC rules
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# to the active contacts
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nmos = factory.create(module_type="ptx", tx_type="nmos")
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extra_contact_space = max(-nmos.get_pin("D").by(), 0)
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def create_ptx(self):
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"""
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Create the PMOS and NMOS in the netlist.
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"""
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self.pmos1_inst = self.add_inst(name="pnand4_pmos1",
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mod=self.pmos_left)
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self.connect_inst(["vdd", "A", "Z", "vdd"])
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self.pmos2_inst = self.add_inst(name="pnand4_pmos2",
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mod=self.pmos_center)
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self.connect_inst(["Z", "B", "vdd", "vdd"])
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self.pmos3_inst = self.add_inst(name="pnand4_pmos3",
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mod=self.pmos_center)
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self.connect_inst(["Z", "C", "vdd", "vdd"])
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self.pmos4_inst = self.add_inst(name="pnand4_pmos4",
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mod=self.pmos_right)
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self.connect_inst(["Z", "D", "vdd", "vdd"])
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self.nmos1_inst = self.add_inst(name="pnand4_nmos1",
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mod=self.nmos_left)
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self.connect_inst(["Z", "D", "net1", "gnd"])
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self.nmos2_inst = self.add_inst(name="pnand4_nmos2",
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mod=self.nmos_center)
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self.connect_inst(["net1", "C", "net2", "gnd"])
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self.nmos3_inst = self.add_inst(name="pnand4_nmos3",
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mod=self.nmos_center)
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self.connect_inst(["net2", "B", "net3", "gnd"])
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self.nmos4_inst = self.add_inst(name="pnand4_nmos4",
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mod=self.nmos_right)
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self.connect_inst(["net3", "A", "gnd", "gnd"])
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def place_ptx(self):
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"""
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Place the PMOS and NMOS in the layout at the upper-most
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and lowest position to provide maximum routing in channel
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"""
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pmos1_pos = vector(self.pmos_left.active_offset.x,
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self.height - self.pmos_left.active_height - self.top_bottom_space)
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self.pmos1_inst.place(pmos1_pos)
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pmos2_pos = pmos1_pos + self.ptx_offset
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self.pmos2_inst.place(pmos2_pos)
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pmos3_pos = pmos2_pos + self.ptx_offset
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self.pmos3_inst.place(pmos3_pos)
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self.pmos4_pos = pmos3_pos + self.ptx_offset
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self.pmos4_inst.place(self.pmos4_pos)
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nmos1_pos = vector(self.pmos_left.active_offset.x,
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self.top_bottom_space)
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self.nmos1_inst.place(nmos1_pos)
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nmos2_pos = nmos1_pos + self.ptx_offset
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self.nmos2_inst.place(nmos2_pos)
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nmos3_pos = nmos2_pos + self.ptx_offset
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self.nmos3_inst.place(nmos3_pos)
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self.nmos4_pos = nmos3_pos + self.ptx_offset
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self.nmos4_inst.place(self.nmos4_pos)
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def add_well_contacts(self):
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""" Add n/p well taps to the layout and connect to supplies """
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self.add_nwell_contact(self.pmos_right,
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self.pmos4_pos + vector(self.m1_pitch, 0))
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self.add_pwell_contact(self.nmos_right,
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self.nmos4_pos + vector(self.m1_pitch, 0))
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def connect_rails(self):
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""" Connect the nmos and pmos to its respective power rails """
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self.connect_pin_to_rail(self.nmos1_inst, "S", "gnd")
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self.connect_pin_to_rail(self.pmos1_inst, "S", "vdd")
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self.connect_pin_to_rail(self.pmos2_inst, "D", "vdd")
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self.connect_pin_to_rail(self.pmos4_inst, "D", "vdd")
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def route_inputs(self):
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""" Route the A and B and C inputs """
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# We can use this pitch because the contacts and overlap won't be adjacent
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pmos_drain_bottom = self.pmos1_inst.get_pin("D").by()
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self.output_yoffset = pmos_drain_bottom - 0.5 * self.route_layer_width - self.route_layer_space
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bottom_pin = self.nmos1_inst.get_pin("D")
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# active contact metal to poly contact metal spacing
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active_contact_to_poly_contact = bottom_pin.uy() + self.m1_space + 0.5 * contact.poly_contact.second_layer_height
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# active diffusion to poly contact spacing
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# doesn't use nmos uy because that is calculated using offset + poly height
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active_top = self.nmos1_inst.by() + self.nmos1_inst.mod.active_height
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active_to_poly_contact = active_top + self.poly_to_active + 0.5 * contact.poly_contact.first_layer_height
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active_to_poly_contact2 = active_top + self.poly_contact_to_gate + 0.5 * self.route_layer_width
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self.inputA_yoffset = max(active_contact_to_poly_contact,
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active_to_poly_contact,
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active_to_poly_contact2)
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apin = self.route_input_gate(self.pmos1_inst,
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self.nmos1_inst,
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self.inputA_yoffset,
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"A",
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position="left")
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self.inputB_yoffset = self.inputA_yoffset + self.m3_pitch
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bpin = self.route_input_gate(self.pmos2_inst,
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self.nmos2_inst,
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self.inputB_yoffset,
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"B",
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position="center")
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self.inputC_yoffset = self.inputB_yoffset + self.m3_pitch
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cpin = self.route_input_gate(self.pmos3_inst,
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self.nmos3_inst,
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self.inputC_yoffset,
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"C",
|
||||
position="right")
|
||||
|
||||
self.inputD_yoffset = self.inputC_yoffset + self.m3_pitch
|
||||
cpin = self.route_input_gate(self.pmos4_inst,
|
||||
self.nmos4_inst,
|
||||
self.inputD_yoffset,
|
||||
"D",
|
||||
position="right")
|
||||
|
||||
if OPTS.tech_name == "sky130":
|
||||
self.add_enclosure([apin, bpin, cpin], "npc", drc("npc_enclose_poly"))
|
||||
|
||||
def route_output(self):
|
||||
""" Route the Z output """
|
||||
|
||||
# PMOS1 drain
|
||||
pmos1_pin = self.pmos1_inst.get_pin("D")
|
||||
# PMOS3 drain
|
||||
pmos3_pin = self.pmos3_inst.get_pin("D")
|
||||
# NMOS3 drain
|
||||
nmos4_pin = self.nmos4_inst.get_pin("D")
|
||||
|
||||
out_offset = vector(nmos4_pin.cx() + self.route_layer_pitch,
|
||||
self.output_yoffset)
|
||||
|
||||
# Go up to metal2 for ease on all output pins
|
||||
# self.add_via_center(layers=self.m1_stack,
|
||||
# offset=pmos1_pin.center(),
|
||||
# directions=("V", "V"))
|
||||
# self.add_via_center(layers=self.m1_stack,
|
||||
# offset=pmos3_pin.center(),
|
||||
# directions=("V", "V"))
|
||||
# self.add_via_center(layers=self.m1_stack,
|
||||
# offset=nmos3_pin.center(),
|
||||
# directions=("V", "V"))
|
||||
|
||||
# # Route in the A input track (top track)
|
||||
# mid_offset = vector(nmos3_pin.center().x, self.inputA_yoffset)
|
||||
# self.add_path("m1", [pmos1_pin.center(), mid_offset, nmos3_pin.uc()])
|
||||
|
||||
# This extends the output to the edge of the cell
|
||||
# self.add_via_center(layers=self.m1_stack,
|
||||
# offset=mid_offset)
|
||||
|
||||
top_left_pin_offset = pmos1_pin.center()
|
||||
top_right_pin_offset = pmos3_pin.center()
|
||||
bottom_pin_offset = nmos4_pin.center()
|
||||
|
||||
# PMOS1 to output
|
||||
self.add_path(self.route_layer, [top_left_pin_offset,
|
||||
vector(top_left_pin_offset.x, out_offset.y),
|
||||
out_offset])
|
||||
# PMOS4 to output
|
||||
self.add_path(self.route_layer, [top_right_pin_offset,
|
||||
vector(top_right_pin_offset.x, out_offset.y),
|
||||
out_offset])
|
||||
# NMOS4 to output
|
||||
mid2_offset = vector(out_offset.x, bottom_pin_offset.y)
|
||||
self.add_path(self.route_layer,
|
||||
[bottom_pin_offset, mid2_offset],
|
||||
width=nmos4_pin.height())
|
||||
mid3_offset = vector(out_offset.x, nmos4_pin.by())
|
||||
self.add_path(self.route_layer, [mid3_offset, out_offset])
|
||||
|
||||
self.add_layout_pin_rect_center(text="Z",
|
||||
layer=self.route_layer,
|
||||
offset=out_offset)
|
||||
|
||||
def analytical_power(self, corner, load):
|
||||
"""Returns dynamic and leakage power. Results in nW"""
|
||||
c_eff = self.calculate_effective_capacitance(load)
|
||||
freq = spice["default_event_frequency"]
|
||||
power_dyn = self.calc_dynamic_power(corner, c_eff, freq)
|
||||
power_leak = spice["nand4_leakage"]
|
||||
|
||||
total_power = self.return_power(power_dyn, power_leak)
|
||||
return total_power
|
||||
|
||||
def calculate_effective_capacitance(self, load):
|
||||
"""Computes effective capacitance. Results in fF"""
|
||||
c_load = load
|
||||
# In fF
|
||||
c_para = spice["min_tx_drain_c"] * (self.nmos_size / parameter["min_tx_size"])
|
||||
transition_prob = 0.1094
|
||||
return transition_prob * (c_load + c_para)
|
||||
|
||||
def input_load(self):
|
||||
"""Return the relative input capacitance of a single input"""
|
||||
return self.nmos_size + self.pmos_size
|
||||
|
||||
def get_stage_effort(self, cout, inp_is_rise=True):
|
||||
"""
|
||||
Returns an object representing the parameters for delay in tau units.
|
||||
Optional is_rise refers to the input direction rise/fall.
|
||||
Input inverted by this stage.
|
||||
"""
|
||||
parasitic_delay = 3
|
||||
return logical_effort.logical_effort(self.name,
|
||||
self.size,
|
||||
self.input_load(),
|
||||
cout,
|
||||
parasitic_delay,
|
||||
not inp_is_rise)
|
||||
|
||||
def build_graph(self, graph, inst_name, port_nets):
|
||||
"""
|
||||
Adds edges based on inputs/outputs.
|
||||
Overrides base class function.
|
||||
"""
|
||||
self.add_graph_edges(graph, port_nets)
|
||||
|
|
@ -8,13 +8,13 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
from sram_factory import factory
|
||||
import debug
|
||||
|
||||
|
||||
class pand2_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
|
|
|
|||
|
|
@ -8,13 +8,13 @@
|
|||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
from sram_factory import factory
|
||||
import debug
|
||||
|
||||
|
||||
class pand3_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
|
|
|
|||
|
|
@ -0,0 +1,39 @@
|
|||
#!/usr/bin/env python3
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2019 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
import debug
|
||||
|
||||
|
||||
class pand4_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
|
||||
globals.init_openram(config_file)
|
||||
global verify
|
||||
import verify
|
||||
|
||||
import pand4
|
||||
|
||||
debug.info(2, "Testing pand4 gate 4x")
|
||||
a = pand4.pand4(name="pand4x4", size=4)
|
||||
self.local_check(a)
|
||||
|
||||
globals.end_openram()
|
||||
|
||||
# instantiate a copdsay of the class to actually run the test
|
||||
if __name__ == "__main__":
|
||||
(OPTS, args) = globals.parse_args()
|
||||
del sys.argv[1:]
|
||||
header(__file__, OPTS.tech_name)
|
||||
unittest.main(testRunner=debugTestRunner())
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
#!/usr/bin/env python3
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2019 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys, os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
from sram_factory import factory
|
||||
import debug
|
||||
|
||||
|
||||
class pnand4_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
|
||||
globals.init_openram(config_file)
|
||||
|
||||
debug.info(2, "Checking 4-input nand gate")
|
||||
tx = factory.create(module_type="pnand4", size=1)
|
||||
self.local_check(tx)
|
||||
|
||||
# debug.info(2, "Checking 3-input nand gate")
|
||||
# tx = factory.create(module_type="pnand3", size=1, add_wells=False)
|
||||
# # Only DRC because well contacts will fail LVS
|
||||
# self.local_drc_check(tx)
|
||||
|
||||
globals.end_openram()
|
||||
|
||||
|
||||
# run the test from the command line
|
||||
if __name__ == "__main__":
|
||||
(OPTS, args) = globals.parse_args()
|
||||
del sys.argv[1:]
|
||||
header(__file__, OPTS.tech_name)
|
||||
unittest.main(testRunner=debugTestRunner())
|
||||
Loading…
Reference in New Issue