mirror of https://github.com/VLSIDA/OpenRAM.git
track s8 customs modules
This commit is contained in:
jcirimel
parent
64cc620440
commit
5246d0a93b
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California
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# All rights reserved.
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#
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import design
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from sram_factory import factory
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from globals import OPTS
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from tech import cell_properties
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class s8_col_cap_array(design.design):
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"""
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Generate a dummy row/column for the replica array.
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"""
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def __init__(self, rows, cols, location, column_offset=0, mirror=0, name=""):
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super().__init__(name)
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self.rows = rows
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self.cols = cols
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self.location = location
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self.column_offset = column_offset
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self.mirror = mirror
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self.no_instances = True
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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""" Create and connect the netlist """
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self.add_modules()
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self.add_pins()
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self.create_instances()
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def create_layout(self):
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self.place_array("col_cap_r{0}_c{1}", self.mirror)
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self.add_layout_pins()
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self.add_boundary()
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self.DRC_LVS()
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def add_modules(self):
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""" Add the modules used in this design """
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if self.location == "top":
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self.colend1 = factory.create(module_type="s8_col_end", version = "colend")
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self.add_mod(self.colend1)
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self.colend2 = factory.create(module_type="s8_col_end", version = "colend_p_cent")
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self.add_mod(self.colend2)
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elif self.location == "bottom":
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self.colend1 = factory.create(module_type="s8_col_end", version = "colenda")
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self.add_mod(self.colend1)
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self.colend2 = factory.create(module_type="s8_col_end", version = "colenda_p_cent")
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self.add_mod(self.colend2)
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self.cell = factory.create(module_type="s8_bitcell", version = "opt1")
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def create_instances(self):
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""" Create the module instances used in this design """
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self.cell_inst = {}
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self.array_layout = []
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alternate_bitcell = 0
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for col in range((self.cols * 2 )-1):
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row_layout = []
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name="rca_{0}".format(col)
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# Top/bottom cell are always dummy cells.
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# Regular array cells are replica cells (>left_rbl and <rows-right_rbl)
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# Replic bit specifies which other bit (in the full range (0,rows) to make a replica cell.
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if alternate_bitcell == 0:
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row_layout.append(self.colend1)
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self.cell_inst[col]=self.add_inst(name=name, mod=self.colend1)
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#self.connect_inst(self.get_bitcell_pins(row, 0))
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alternate_bitcell = 1
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else:
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row_layout.append(self.colend2)
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self.cell_inst[col]=self.add_inst(name=name,mod=self.colend2)
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#self.connect_inst(self.get_bitcell_pins(row, 0))
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alternate_bitcell = 0
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self.array_layout.append(row_layout)
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def get_bitcell_pins(self, row, col):
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"""
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Creates a list of connections in the bitcell,
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indexed by column and row, for instance use in bitcell_array
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"""
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pin_name = cell_properties.bitcell.cell_6t.pin
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bitcell_pins = ["{0}_{1}".format(pin_name.bl0, col),
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"{0}_{1}".format(pin_name.br0, col),
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"vdd"]
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return bitcell_pins
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def place_array(self, name_template, row_offset=0):
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self.height = self.colend1.height
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self.width = (self.colend1.width + self.colend2.width) * self.cols - self.colend2.width
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yoffset = 0.0
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xoffset = 0.0
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for row in range(0, len(self.array_layout)):
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inst = self.insts[row]
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inst.place(offset=[xoffset, yoffset])
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xoffset += inst.width
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def add_pins(self):
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for row in range(self.cols):
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for port in self.all_ports:
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self.add_pin("bl{}_{}".format(port, row), "OUTPUT")
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self.add_pin("br{}_{}".format(port, row), "OUTPUT")
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self.add_pin("vpwr", "POWER")
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self.add_pin("vgnd", "GROUND")
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def add_layout_pins(self):
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""" Add the layout pins """
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return
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row_list = self.cell.get_all_wl_names()
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for row in range(1, self.row_size - 1):
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for cell_row in row_list:
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wl_pin = self.cell_inst[row, 0].get_pin(cell_row)
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self.add_layout_pin(text=cell_row + "_{0}".format(row),
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layer=wl_pin.layer,
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offset=wl_pin.ll().scale(0, 1),
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width=self.width,
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height=wl_pin.height())
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# Add vdd/gnd via stacks
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for row in range(1, self.row_size - 1):
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for col in range(self.column_size):
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inst = self.cell_inst[row, col]
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for pin_name in ["vdd", "gnd"]:
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for pin in inst.get_pins(pin_name):
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self.add_power_pin(name=pin.name,
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loc=pin.center(),
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start_layer=pin.layer)
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import design
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import debug
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import utils
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from tech import GDS,layer,drc,parameter,cell_properties
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from tech import cell_properties as props
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import bitcell_base
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from globals import OPTS
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class s8_dummy_bitcell(bitcell_base.bitcell_base):
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"""
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A single bit cell (6T, 8T, etc.) This module implements the
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single memory cell used in the design. It is a hand-made cell, so
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the layout and netlist should be available in the technology
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library.
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"""
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if props.compare_ports(props.bitcell.split_wl):
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pin_names = ["bl", "br", "wl0", "wl1", "vdd", "gnd"]
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type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT" , "POWER", "GROUND"]
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else:
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pin_names = [props.bitcell.cell_6t.pin.bl,
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props.bitcell.cell_6t.pin.br,
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props.bitcell.cell_6t.pin.wl,
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props.bitcell.cell_6t.pin.vdd,
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props.bitcell.cell_6t.pin.gnd]
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def __init__(self, version, name=""):
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# Ignore the name argument
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if version == "opt1":
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self.name = "s8sram_cell_opt1"
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self.border_structure = "s8sram_cell"
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elif version == "opt1a":
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self.name = "s8sram_cell_opt1a"
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self.border_structure = "s8sram_cell"
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bitcell_base.bitcell_base.__init__(self, self.name)
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debug.info(2, "Create dummy bitcell")
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(self.width, self.height) = utils.get_libcell_size(self.name,
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GDS["unit"],
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layer["mem"],
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"s8sram_cell\x00")
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self.pin_map = utils.get_libcell_pins(self.pin_names, self.name, GDS["unit"])
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California
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# All rights reserved.
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#
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import design
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from sram_factory import factory
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from globals import OPTS
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from tech import cell_properties
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class s8_row_cap_array(design.design):
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"""
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Generate a dummy row/column for the replica array.
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"""
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def __init__(self, rows, cols, column_offset=0, mirror=0, name=""):
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super().__init__(name)
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self.rows = rows
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self.cols = cols
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self.column_offset = column_offset
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self.mirror = mirror
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self.no_instances = True
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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""" Create and connect the netlist """
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self.add_modules()
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self.add_pins()
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self.create_instances()
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def create_layout(self):
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self.place_array("dummy_r{0}_c{1}", self.mirror)
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self.add_layout_pins()
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self.add_boundary()
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self.DRC_LVS()
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def add_modules(self):
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""" Add the modules used in this design """
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if self.column_offset == 0:
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self.top_corner = factory.create(module_type="s8_corner", location = "ul")
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self.add_mod(self.top_corner)
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self.bottom_corner =factory.create(module_type="s8_corner", location = "ll")
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self.add_mod(self.bottom_corner)
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else:
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self.top_corner = factory.create(module_type="s8_corner", location = "ur")
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self.add_mod(self.top_corner)
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self.bottom_corner = factory.create(module_type="s8_corner", location = "lr")
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self.add_mod(self.bottom_corner)
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self.rowend1 = factory.create(module_type="s8_row_end", version = "rowend")
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self.add_mod(self.rowend1)
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self.rowend2 = factory.create(module_type="s8_row_end", version = "rowenda")
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self.add_mod(self.rowend2)
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self.cell = factory.create(module_type="s8_bitcell", version = "opt1")
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def create_instances(self):
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""" Create the module instances used in this design """
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self.cell_inst = {}
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self.array_layout = []
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alternate_bitcell = 0
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for row in range(self.rows):
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row_layout = []
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name="rca_{0}".format(row)
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# Top/bottom cell are always dummy cells.
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# Regular array cells are replica cells (>left_rbl and <rows-right_rbl)
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# Replic bit specifies which other bit (in the full range (0,rows) to make a replica cell.
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if (row < self.rows -1 and row >0):
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if alternate_bitcell == 0:
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row_layout.append(self.rowend1)
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self.cell_inst[row]=self.add_inst(name=name, mod=self.rowend1)
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#self.connect_inst(self.get_bitcell_pins(row, 0))
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alternate_bitcell = 1
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else:
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row_layout.append(self.rowend2)
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self.cell_inst[row]=self.add_inst(name=name,mod=self.rowend2)
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#self.connect_inst(self.get_bitcell_pins(row, 0))
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alternate_bitcell = 0
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elif (row == 0):
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row_layout.append(self.bottom_corner)
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self.cell_inst[row]=self.add_inst(name=name, mod=self.bottom_corner)
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#self.connect_inst(self.get_bitcell_pins_col_cap(row, 0))
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elif (row == self.rows - 1):
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row_layout.append(self.top_corner)
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self.cell_inst[row]=self.add_inst(name=name, mod=self.top_corner)
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#self.connect_inst(self.get_bitcell_pins_col_cap(row, 0))
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self.array_layout.append(row_layout)
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def get_bitcell_pins(self, row, col):
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"""
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Creates a list of connections in the bitcell,
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indexed by column and row, for instance use in bitcell_array
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"""
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pin_name = cell_properties.bitcell.cell_1rw1r.pin
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bitcell_pins = ["{0}_{1}".format(pin_name.wl0, row),
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"{0}_{1}".format(pin_name.wl1, row),
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"gnd"]
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return bitcell_pins
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def place_array(self, name_template, row_offset=0):
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self.width = 0
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self.height = 0
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for inst in self.insts:
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self.height += inst.height
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if inst.width > self.width:
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self.width = inst.width
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yoffset = 0.0
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for row in range(0, len(self.array_layout)):
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xoffset = 0.0
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for col in range(0, len(self.array_layout[row])):
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inst = self.insts[col + row*len(self.array_layout[row])]
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inst.place(offset=[xoffset, yoffset])
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xoffset += inst.width
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yoffset += inst.height
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def add_pins(self):
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for row in range(self.rows-2):
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for port in self.all_ports:
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self.add_pin("wl_{}_{}".format(port, row), "INPUT")
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for row in range(self.rows-2):
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for port in self.all_ports:
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self.add_pin("wl0_{}_{}".format(port, row), "OUTPUT")
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self.add_pin("wl1_{}_{}".format(port, row), "OUTPUT")
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self.add_pin("vpwr", "POWER")
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self.add_pin("vgnd", "GROUND")
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def add_layout_pins(self):
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""" Add the layout pins """
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return
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row_list = self.cell.get_all_wl_names()
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for row in range(1, self.row_size - 1):
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for cell_row in row_list:
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wl_pin = self.cell_inst[row, 0].get_pin(cell_row)
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self.add_layout_pin(text=cell_row + "_{0}".format(row),
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layer=wl_pin.layer,
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offset=wl_pin.ll().scale(0, 1),
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width=self.width,
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height=wl_pin.height())
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# Add vdd/gnd via stacks
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for row in range(1, self.row_size - 1):
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for col in range(self.column_size):
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inst = self.cell_inst[row, col]
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for pin_name in ["vdd", "gnd"]:
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for pin in inst.get_pins(pin_name):
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self.add_power_pin(name=pin.name,
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loc=pin.center(),
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start_layer=pin.layer)
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@ -0,0 +1,34 @@
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import debug
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import design
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import utils
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from globals import OPTS
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from tech import parameter, drc, layer, GDS
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class s8_row_end(design.design):
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def __init__(self, version, name=""):
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super().__init__(name)
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pin_names = []
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type_list = []
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if version == "rowend":
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self.name = "s8sram16x16_rowend"
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elif version == "rowenda":
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self.name = "s8sram16x16_rowenda"
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else:
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debug.error("Invalid type for row_end", -1)
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design.design.__init__(self, name=self.name)
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(self.width, self.height) = utils.get_libcell_size(self.name,
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GDS["unit"],
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layer["mem"],
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"s8sram16x16_rowend_ce\x00")
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pin_map = utils.get_libcell_pins(pin_names, self.name, GDS["unit"])
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