OpenRAM/compiler
mrg 18c8ad265e Unique name for sram channel routes 2020-10-01 09:55:34 -07:00
..
base Use unique instance names for channel routes. 2020-10-01 07:43:06 -07:00
bitcells update to new metal stack names 2020-07-31 05:27:19 -07:00
characterizer Add num_threads to options. PEP8 cleanup. 2020-10-01 08:07:03 -07:00
custom Removed dead code related to older characterization scheme 2020-08-27 17:30:58 -07:00
datasheet
drc
example_configs Fix 1w/1r example 2020-07-23 14:17:13 -07:00
gdsMill
modules Provide unique WL driver instance name 2020-10-01 07:17:32 -07:00
pgates Zjog the WL enable. Min driver is 1. 2020-09-28 12:24:55 -07:00
router
sram Unique name for sram channel routes 2020-10-01 09:55:34 -07:00
tests Enable riscv tests 2020-09-30 12:39:40 -07:00
verify Do not do final verification if supplies were not routed 2020-09-15 13:39:00 -07:00
Makefile
debug.py DRC/LVS and errors fixes. 2020-06-30 07:16:05 -07:00
gen_stimulus.py
globals.py OpenRAM 1.1.6 2020-07-13 16:26:25 -07:00
openram.py Add words_per_row and others in config file. 2020-07-13 12:37:56 -07:00
options.py Default to 2 threads only 2020-10-01 09:55:17 -07:00
run_profile.sh
sram_factory.py
view_profile.py