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d315ff18e55e08dc7743a0b7f8d3bd37eed5b0f4
OpenRAM/compiler
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mrg d315ff18e5 Add num_threads to options. PEP8 cleanup.
2020-10-01 08:07:03 -07:00
..
base
Use unique instance names for channel routes.
2020-10-01 07:43:06 -07:00
bitcells
update to new metal stack names
2020-07-31 05:27:19 -07:00
characterizer
Add num_threads to options. PEP8 cleanup.
2020-10-01 08:07:03 -07:00
custom
Removed dead code related to older characterization scheme
2020-08-27 17:30:58 -07:00
datasheet
…
drc
PEP8 cleanup
2020-04-15 11:24:28 -07:00
example_configs
Fix 1w/1r example
2020-07-23 14:17:13 -07:00
gdsMill
added purposes to addText(), removed reference to specific tech from gdsMill
2020-02-19 16:26:52 -08:00
modules
Provide unique WL driver instance name
2020-10-01 07:17:32 -07:00
pgates
Zjog the WL enable. Min driver is 1.
2020-09-28 12:24:55 -07:00
router
Changes to simplify metal preferred directions and pitches.
2020-05-10 11:32:45 -07:00
sram
Enable riscv tests
2020-09-30 12:39:40 -07:00
tests
Enable riscv tests
2020-09-30 12:39:40 -07:00
verify
Do not do final verification if supplies were not routed
2020-09-15 13:39:00 -07:00
debug.py
DRC/LVS and errors fixes.
2020-06-30 07:16:05 -07:00
gen_stimulus.py
Fixed errors in extra rows characterization
2020-03-22 20:54:49 +00:00
globals.py
OpenRAM 1.1.6
2020-07-13 16:26:25 -07:00
Makefile
…
openram.py
Add words_per_row and others in config file.
2020-07-13 12:37:56 -07:00
options.py
Add num_threads to options. PEP8 cleanup.
2020-10-01 08:07:03 -07:00
run_profile.sh
…
sram_factory.py
Auto-generate port dependent cell names.
2020-06-05 15:09:22 -07:00
view_profile.py
Remove some flake8 errors/warnings.
2019-10-02 23:26:02 +00:00