mrg 483f6b187c RBL driver supply location differs for sky130 and other techs

2020-10-06 16:47:32 -07:00

..

base

Fix run-time bug for duplicate instance check

2020-10-06 16:26:35 -07:00

bitcells

update to new metal stack names

2020-07-31 05:27:19 -07:00

characterizer

Change .spinit to .spiceinit

2020-10-05 13:50:04 -07:00

custom

Use 4x16 decoder with dual port bitcell in tests.

2020-10-05 10:52:56 -07:00

datasheet

Convert capital names to lower case for consistency

2019-08-21 13:45:34 -07:00

drc

PEP8 cleanup

2020-04-15 11:24:28 -07:00

example_configs

Add various riscv examples

2020-10-06 16:25:44 -07:00

gdsMill

added purposes to addText(), removed reference to specific tech from gdsMill

2020-02-19 16:26:52 -08:00

modules

RBL driver supply location differs for sky130 and other techs

2020-10-06 16:47:32 -07:00

pgates

Use 4x16 decoder with dual port bitcell in tests.

2020-10-05 10:52:56 -07:00

router

Changes to simplify metal preferred directions and pitches.

2020-05-10 11:32:45 -07:00

sram

Allow 16-way column mux

2020-10-06 16:27:02 -07:00

tests

PEP8 fixes in regress.py

2020-10-05 15:56:12 -07:00

verify

Initial pex sram test.

2020-10-02 13:32:52 -07:00

debug.py

DRC/LVS and errors fixes.

2020-06-30 07:16:05 -07:00

gen_stimulus.py

Fixed errors in extra rows characterization

2020-03-22 20:54:49 +00:00

globals.py

Add command line -j option for number of threads.

2020-10-05 15:49:00 -07:00

Makefile

Clean up Makefile for unit tests

2018-12-05 12:58:10 -08:00

openram.py

Add words_per_row and others in config file.

2020-07-13 12:37:56 -07:00

options.py

Add command line -j option for number of threads.

2020-10-05 15:49:00 -07:00

run_profile.sh

Convert pin map to a set for faster membership.

2019-04-01 15:45:44 -07:00

sram_factory.py

Auto-generate port dependent cell names.

2020-06-05 15:09:22 -07:00

view_profile.py

Remove some flake8 errors/warnings.

2019-10-02 23:26:02 +00:00