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mrg 2020-10-08 09:53:17 -07:00
parent 3dd72cdeac
commit 7076c376e0
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compiler/tests/b3v3_1check.log
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BSIM3V3.1 Parameter Check
Model = p
W = 6e-07, L = 8e-07
Warning: Pd = 0 is less than W.
Warning: Ps = 0 is less than W.

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compiler/tests/missing_pin.gds
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compiler/tests/sram_1b_16_1rw_freepdk45.log
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[globals/init_openram]: Initializing OpenRAM...
[globals/setup_paths]: Setting up paths...
[globals/setup_paths]: Temporary files saved in /home/jesse/output/
[globals/read_config]: Configuration file is /home/jesse/openram/compiler/tests/configs/config.py
[globals/read_config]: Output saved in /home/jesse/openram/compiler/tests/./
[globals/import_tech]: Importing technology: freepdk45
[globals/import_tech]: Adding technology path: /home/jesse/openram/technology
[globals/init_paths]: Creating temp directory: /home/jesse/output/
[characterizer/<module>]: Initializing characterizer...
[characterizer/<module>]: Analytical model enabled.
[verify/<module>]: Initializing verify...
[verify/<module>]: Finding DRC/LVS/PEX tools.
[globals/get_tool]: Finding DRC tool...
[globals/get_tool]: Using DRC: /opt/calibre/bin/calibre
[globals/get_tool]: Finding LVS tool...
[globals/get_tool]: Using LVS: /opt/calibre/bin/calibre
[globals/get_tool]: Finding PEX tool...
[globals/get_tool]: Using PEX: /opt/calibre/bin/calibre
[__main__/runTest]: Performing LVS on: cell_1w_1r, write_driver, replica_cell_1rw_1r, dummy_cell_6t, cell_1rw_1r, replica_cell_6t, dff, dummy_cell_1rw_1r, sense_amp, replica_cell_1w_1r, dummy_cell_1w_1r, cell_6t, tri_gate
[run_script/run_script]: /home/jesse/output/run_drc.sh 2> /home/jesse/output/cell_1w_1r.drc.err 1> /home/jesse/output/cell_1w_1r.drc.out
[verify.calibre/run_drc]: cell_1w_1r Geometries: 238 Checks: 167 Errors: 0
[run_script/run_script]: /home/jesse/output/run_lvs.sh 2> /home/jesse/output/cell_1w_1r.lvs.err 1> /home/jesse/output/cell_1w_1r.lvs.out
[verify.calibre/run_lvs]: cell_1w_1r Summary: 0 Output: 0 Extraction: 0
[run_script/run_script]: /home/jesse/output/run_drc.sh 2> /home/jesse/output/write_driver.drc.err 1> /home/jesse/output/write_driver.drc.out
[verify.calibre/run_drc]: write_driver Geometries: 308 Checks: 167 Errors: 0
[run_script/run_script]: /home/jesse/output/run_lvs.sh 2> /home/jesse/output/write_driver.lvs.err 1> /home/jesse/output/write_driver.lvs.out
[verify.calibre/run_lvs]: write_driver Summary: 0 Output: 0 Extraction: 0
[run_script/run_script]: /home/jesse/output/run_drc.sh 2> /home/jesse/output/replica_cell_1rw_1r.drc.err 1> /home/jesse/output/replica_cell_1rw_1r.drc.out
[verify.calibre/run_drc]: replica_cell_1rw_1r Geometries: 239 Checks: 167 Errors: 0
[run_script/run_script]: /home/jesse/output/run_lvs.sh 2> /home/jesse/output/replica_cell_1rw_1r.lvs.err 1> /home/jesse/output/replica_cell_1rw_1r.lvs.out
[verify.calibre/run_lvs]: replica_cell_1rw_1r Summary: 0 Output: 0 Extraction: 0
[run_script/run_script]: /home/jesse/output/run_drc.sh 2> /home/jesse/output/dummy_cell_6t.drc.err 1> /home/jesse/output/dummy_cell_6t.drc.out
[verify.calibre/run_drc]: dummy_cell_6t Geometries: 289 Checks: 167 Errors: 0
[run_script/run_script]: /home/jesse/output/run_lvs.sh 2> /home/jesse/output/dummy_cell_6t.lvs.err 1> /home/jesse/output/dummy_cell_6t.lvs.out
[verify.calibre/run_lvs]: dummy_cell_6t Summary: 0 Output: 0 Extraction: 0
[run_script/run_script]: /home/jesse/output/run_drc.sh 2> /home/jesse/output/cell_1rw_1r.drc.err 1> /home/jesse/output/cell_1rw_1r.drc.out
[verify.calibre/run_drc]: cell_1rw_1r Geometries: 238 Checks: 167 Errors: 0
[run_script/run_script]: /home/jesse/output/run_lvs.sh 2> /home/jesse/output/cell_1rw_1r.lvs.err 1> /home/jesse/output/cell_1rw_1r.lvs.out
[verify.calibre/run_lvs]: cell_1rw_1r Summary: 0 Output: 0 Extraction: 0
[run_script/run_script]: /home/jesse/output/run_drc.sh 2> /home/jesse/output/replica_cell_6t.drc.err 1> /home/jesse/output/replica_cell_6t.drc.out
[verify.calibre/run_drc]: replica_cell_6t Geometries: 291 Checks: 167 Errors: 0
[run_script/run_script]: /home/jesse/output/run_lvs.sh 2> /home/jesse/output/replica_cell_6t.lvs.err 1> /home/jesse/output/replica_cell_6t.lvs.out
[verify.calibre/run_lvs]: replica_cell_6t Summary: 0 Output: 0 Extraction: 0
[run_script/run_script]: /home/jesse/output/run_drc.sh 2> /home/jesse/output/dff.drc.err 1> /home/jesse/output/dff.drc.out
[verify.calibre/run_drc]: dff Geometries: 307 Checks: 167 Errors: 0
[run_script/run_script]: /home/jesse/output/run_lvs.sh 2> /home/jesse/output/dff.lvs.err 1> /home/jesse/output/dff.lvs.out
[verify.calibre/run_lvs]: dff Summary: 0 Output: 0 Extraction: 0
[run_script/run_script]: /home/jesse/output/run_drc.sh 2> /home/jesse/output/dummy_cell_1rw_1r.drc.err 1> /home/jesse/output/dummy_cell_1rw_1r.drc.out
[verify.calibre/run_drc]: dummy_cell_1rw_1r Geometries: 234 Checks: 167 Errors: 0
[run_script/run_script]: /home/jesse/output/run_lvs.sh 2> /home/jesse/output/dummy_cell_1rw_1r.lvs.err 1> /home/jesse/output/dummy_cell_1rw_1r.lvs.out
[verify.calibre/run_lvs]: dummy_cell_1rw_1r Summary: 0 Output: 0 Extraction: 0
[run_script/run_script]: /home/jesse/output/run_drc.sh 2> /home/jesse/output/sense_amp.drc.err 1> /home/jesse/output/sense_amp.drc.out
[verify.calibre/run_drc]: sense_amp Geometries: 221 Checks: 167 Errors: 0
[run_script/run_script]: /home/jesse/output/run_lvs.sh 2> /home/jesse/output/sense_amp.lvs.err 1> /home/jesse/output/sense_amp.lvs.out
[verify.calibre/run_lvs]: sense_amp Summary: 0 Output: 0 Extraction: 0
[run_script/run_script]: /home/jesse/output/run_drc.sh 2> /home/jesse/output/replica_cell_1w_1r.drc.err 1> /home/jesse/output/replica_cell_1w_1r.drc.out
[verify.calibre/run_drc]: replica_cell_1w_1r Geometries: 239 Checks: 167 Errors: 0
[run_script/run_script]: /home/jesse/output/run_lvs.sh 2> /home/jesse/output/replica_cell_1w_1r.lvs.err 1> /home/jesse/output/replica_cell_1w_1r.lvs.out
[verify.calibre/run_lvs]: replica_cell_1w_1r Summary: 0 Output: 0 Extraction: 0
[run_script/run_script]: /home/jesse/output/run_drc.sh 2> /home/jesse/output/dummy_cell_1w_1r.drc.err 1> /home/jesse/output/dummy_cell_1w_1r.drc.out
[verify.calibre/run_drc]: dummy_cell_1w_1r Geometries: 234 Checks: 167 Errors: 0
[run_script/run_script]: /home/jesse/output/run_lvs.sh 2> /home/jesse/output/dummy_cell_1w_1r.lvs.err 1> /home/jesse/output/dummy_cell_1w_1r.lvs.out
[verify.calibre/run_lvs]: dummy_cell_1w_1r Summary: 0 Output: 0 Extraction: 0
[run_script/run_script]: /home/jesse/output/run_drc.sh 2> /home/jesse/output/cell_6t.drc.err 1> /home/jesse/output/cell_6t.drc.out
[verify.calibre/run_drc]: cell_6t Geometries: 291 Checks: 167 Errors: 0
[run_script/run_script]: /home/jesse/output/run_lvs.sh 2> /home/jesse/output/cell_6t.lvs.err 1> /home/jesse/output/cell_6t.lvs.out
[verify.calibre/run_lvs]: cell_6t Summary: 0 Output: 0 Extraction: 0
[run_script/run_script]: /home/jesse/output/run_drc.sh 2> /home/jesse/output/tri_gate.drc.err 1> /home/jesse/output/tri_gate.drc.out
[verify.calibre/run_drc]: tri_gate Geometries: 156 Checks: 167 Errors: 0
[run_script/run_script]: /home/jesse/output/run_lvs.sh 2> /home/jesse/output/tri_gate.lvs.err 1> /home/jesse/output/tri_gate.lvs.out
[verify.calibre/run_lvs]: tri_gate Summary: 0 Output: 0 Extraction: 0
[globals/cleanup_paths]: Preserving temp directory: /home/jesse/output/
[verify.calibre/print_drc_stats]: DRC runs: 13
[verify.calibre/print_lvs_stats]: LVS runs: 13
[verify.calibre/print_pex_stats]: PEX runs: 0

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compiler/tests/sram_1b_16_1rw_s8.log
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[globals/init_openram]: Initializing OpenRAM...
[globals/setup_paths]: Setting up paths...
[globals/setup_paths]: Temporary files saved in /home/jesse/output/
[globals/read_config]: Configuration file is /home/jesse/openram/compiler/tests/configs/config.py
[globals/read_config]: Output saved in /home/jesse/openram/compiler/tests/./
[globals/import_tech]: Importing technology: s8
[globals/import_tech]: Adding technology path: /home/jesse/openram/technology
[globals/init_paths]: Creating temp directory: /home/jesse/output/
[verify/<module>]: Initializing verify...
[verify/<module>]: Finding DRC/LVS/PEX tools.
[globals/get_tool]: Finding DRC tool...
[globals/get_tool]: Using DRC: /opt/calibre/bin/calibre
[globals/get_tool]: Finding LVS tool...
[globals/get_tool]: Using LVS: /opt/calibre/bin/calibre
[globals/get_tool]: Finding PEX tool...
[globals/get_tool]: Using PEX: /opt/calibre/bin/calibre
[characterizer/<module>]: Initializing characterizer...
[characterizer/<module>]: Analytical model enabled.
[globals/setup_bitcell]: Using bitcell: bitcell_1rw_1r
[characterizer/<module>]: Initializing characterizer...
[characterizer/<module>]: Finding spice simulator.
[bitcell_1rw_1r/__init__]: Create bitcell with 1RW and 1R Port
[sram_config/recompute_sizes]: Recomputing with words per row: 2
[sram_config/recompute_sizes]: Rows: 16 Cols: 8
[sram_config/recompute_sizes]: Row addr size: 4 Col addr size: 1 Bank addr size: 5
[sram_config/recompute_sizes]: Recomputing with words per row: 1
[sram_config/recompute_sizes]: Rows: 32 Cols: 4
[sram_config/recompute_sizes]: Row addr size: 5 Col addr size: 0 Bank addr size: 5
[__main__/runTest]: Functional test for sram 1rw,1r with 4 bit words, 32 words, 1 words per row, 1 banks
[sram/__init__]: create sram of size 4 with 32 num of words 1 banks
[dff_array/__init__]: Creating row_addr_dff rows=5 cols=1
[dff_array/__init__]: Creating data_dff rows=1 cols=4
[bank/__init__]: create sram of size 4 with 32 words
[port_data/__init__]: create data port of size 4 with 1 words per row
[precharge/__init__]: creating precharge cell precharge
[pgate/bin_width]: binning pmos tx, target: 0.44999999999999996, found 0.55 x 1 = 0.55
[pgate/bin_width]: binning pmos tx, target: 0.55, found 0.55 x 1 = 0.55
[precharge_array/__init__]: Creating precharge_array
[precharge/__init__]: creating precharge cell precharge_0
[pgate/bin_width]: binning pmos tx, target: 0.44999999999999996, found 0.55 x 1 = 0.55
[sense_amp_array/__init__]: Creating sense_amp_array
[sense_amp/__init__]: Create sense_amp
[write_driver_array/__init__]: Creating write_driver_array
[write_driver/__init__]: Create write_driver
[port_data/__init__]: create data port of size 4 with 1 words per row
[precharge_array/__init__]: Creating precharge_array_0
[precharge/__init__]: creating precharge cell precharge_1
[pgate/bin_width]: binning pmos tx, target: 0.44999999999999996, found 0.55 x 1 = 0.55
[port_address/__init__]: create data port of cols 4 rows 32
[and2_dec/__init__]: Creating and2_dec and2_dec
[pinv_dec/__init__]: creating pinv_dec structure pinv_dec with size of 1
[pinv/__init__]: creating pinv structure pinv_dec with size of 1
[pgate/bin_width]: binning nmos tx, target: 0.36, found 0.36 x 1 = 0.36
[pgate/bin_width]: binning pmos tx, target: 1.08, found 1.12 x 1 = 1.12
[pgate/bin_width]: binning nmos tx, target: 0.36, found 0.36 x 1 = 0.36
[pgate/bin_width]: binning pmos tx, target: 1.12, found 1.12 x 1 = 1.12
[and3_dec/__init__]: Creating and3_dec and3_dec
[wordline_driver_array/__init__]: Creating wordline_driver_array
[wordline_driver/__init__]: Creating wordline_driver wordline_driver
[pinv_dec/__init__]: creating pinv_dec structure pinv_dec_0 with size of 4
[pinv/__init__]: creating pinv structure pinv_dec_0 with size of 4
[pgate/bin_width]: binning nmos tx, target: 1.44, found 1.68 x 1 = 1.68
[pgate/bin_width]: binning pmos tx, target: 4.32, found 5.0 x 1 = 5.0
[pgate/bin_width]: binning nmos tx, target: 1.68, found 1.68 x 1 = 1.68
[pgate/bin_width]: binning pmos tx, target: 5.0, found 5.0 x 1 = 5.0
[replica_bitcell_array/__init__]: Creating replica_bitcell_array 32 x 4
[bitcell_base_array/__init__]: Creating bitcell_array 32 x 4
[replica_bitcell_1rw_1r/__init__]: Create replica bitcell 1rw+1r object
[dummy_bitcell_1rw_1r/__init__]: Create dummy bitcell 1rw+1r object
[col_cap_bitcell_1rw_1r/__init__]: Create col_cap bitcell 1rw+1r object
[bitcell_base_array/__init__]: Creating dummy_array 1 x 4
[bitcell_base_array/__init__]: Creating col_cap_array 1 x 4
[bitcell_base_array/__init__]: Creating row_cap_array 36 x 1
[row_cap_bitcell_1rw_1r/__init__]: Create row_cap bitcell 1rw+1r object
[bitcell_base_array/__init__]: Creating row_cap_array_0 36 x 1
[control_logic/__init__]: Creating control_logic_rw
[dff_buf/__init__]: Creating dff_buf
[pinv/__init__]: creating pinv structure pinv with size of 2
[pgate/bin_width]: binning nmos tx, target: 0.72, found 0.74 x 1 = 0.74
[pgate/bin_width]: binning pmos tx, target: 2.16, found 1.26 x 2 = 2.52
[pgate/bin_width]: binning nmos tx, target: 0.74, found 0.74 x 1 = 0.74
[pgate/bin_width]: binning pmos tx, target: 1.26, found 1.26 x 1 = 1.26
[pinv/__init__]: creating pinv structure pinv_0 with size of 4
[pgate/bin_width]: binning nmos tx, target: 1.44, found 1.68 x 1 = 1.68
[pgate/bin_width]: binning pmos tx, target: 4.32, found 5.0 x 1 = 5.0
[dff_buf_array/__init__]: Creating dff_buf_array
[dff_buf/__init__]: Creating dff_buf_0
[pand2/__init__]: Creating pand2 pand2
[pnand2/__init__]: creating pnand2 structure pnand2 with size of 1
[pgate/bin_width]: binning nmos tx, target: 0.72, found 0.74 x 1 = 0.74
[pgate/bin_width]: binning pmos tx, target: 1.08, found 1.12 x 1 = 1.12
[pgate/bin_width]: binning nmos tx, target: 0.74, found 0.74 x 1 = 0.74
[pgate/bin_width]: binning nmos tx, target: 0.74, found 0.74 x 1 = 0.74
[pgate/bin_width]: binning pmos tx, target: 1.12, found 1.12 x 1 = 1.12
[pdriver/__init__]: creating pdriver pdriver
[pinv/__init__]: creating pinv structure pinv_1 with size of 12
[pgate/bin_width]: binning nmos tx, target: 4.32, found 5.0 x 1 = 5.0
[pgate/bin_width]: binning pmos tx, target: 12.959999999999999, found 7.0 x 2 = 14.0
[pgate/bin_width]: binning nmos tx, target: 5.0, found 5.0 x 1 = 5.0
[pgate/bin_width]: binning pmos tx, target: 7.0, found 7.0 x 1 = 7.0
[pbuf/__init__]: creating pbuf with size of 4
[pinv/__init__]: creating pinv structure pinv_2 with size of 1
[pgate/bin_width]: binning nmos tx, target: 0.36, found 0.36 x 1 = 0.36
[pgate/bin_width]: binning pmos tx, target: 1.08, found 1.12 x 1 = 1.12
[pinv/__init__]: creating pinv structure pinv_3 with size of 4
[pgate/bin_width]: binning nmos tx, target: 1.44, found 1.68 x 1 = 1.68
[pgate/bin_width]: binning pmos tx, target: 4.32, found 5.0 x 1 = 5.0
[pdriver/__init__]: creating pdriver pdriver_0
[pinv/__init__]: creating pinv structure pinv_4 with size of 1
[pgate/bin_width]: binning nmos tx, target: 0.36, found 0.36 x 1 = 0.36
[pgate/bin_width]: binning pmos tx, target: 1.08, found 1.12 x 1 = 1.12
[pinv/__init__]: creating pinv structure pinv_5 with size of 2
[pgate/bin_width]: binning nmos tx, target: 0.72, found 0.74 x 1 = 0.74
[pgate/bin_width]: binning pmos tx, target: 2.16, found 1.26 x 2 = 2.52
[pinv/__init__]: creating pinv structure pinv_6 with size of 7
[pgate/bin_width]: binning nmos tx, target: 2.52, found 3.0 x 1 = 3.0
[pgate/bin_width]: binning pmos tx, target: 7.56, found 3.0 x 3 = 9.0
[pgate/bin_width]: binning nmos tx, target: 3.0, found 3.0 x 1 = 3.0
[pgate/bin_width]: binning pmos tx, target: 3.0, found 3.0 x 1 = 3.0
[pinv/__init__]: creating pinv structure pinv_7 with size of 20
[pgate/bin_width]: binning nmos tx, target: 7.199999999999999, found 2.0 x 4 = 8.0
[pgate/bin_width]: binning pmos tx, target: 21.599999999999998, found 5.0 x 5 = 25.0
[pgate/bin_width]: binning nmos tx, target: 2.0, found 2.0 x 1 = 2.0
[pgate/bin_width]: binning pmos tx, target: 5.0, found 5.0 x 1 = 5.0
[pdriver/__init__]: creating pdriver pdriver_1
[pinv/__init__]: creating pinv structure pinv_8 with size of 1
[pgate/bin_width]: binning nmos tx, target: 0.36, found 0.36 x 1 = 0.36
[pgate/bin_width]: binning pmos tx, target: 1.08, found 1.12 x 1 = 1.12
[pinv/__init__]: creating pinv structure pinv_9 with size of 11
[pgate/bin_width]: binning nmos tx, target: 3.96, found 2.0 x 2 = 4.0
[pgate/bin_width]: binning pmos tx, target: 11.879999999999999, found 7.0 x 2 = 14.0
[pgate/bin_width]: binning nmos tx, target: 2.0, found 2.0 x 1 = 2.0
[pand3/__init__]: Creating pand3 pand3
[pnand3/__init__]: creating pnand3 structure pnand3 with size of 1
[pgate/bin_width]: binning nmos tx, target: 0.72, found 0.74 x 1 = 0.74
[pgate/bin_width]: binning pmos tx, target: 1.08, found 1.12 x 1 = 1.12
[pgate/bin_width]: binning nmos tx, target: 0.74, found 0.74 x 1 = 0.74
[pand3/__init__]: Creating pand3 pand3_0
[pdriver/__init__]: creating pdriver pdriver_2
[pinv/__init__]: creating pinv structure pinv_10 with size of 4
[pgate/bin_width]: binning nmos tx, target: 1.44, found 1.68 x 1 = 1.68
[pgate/bin_width]: binning pmos tx, target: 4.32, found 5.0 x 1 = 5.0
[pinv/__init__]: creating pinv structure pinv_11 with size of 1
[pgate/bin_width]: binning nmos tx, target: 0.36, found 0.36 x 1 = 0.36
[pgate/bin_width]: binning pmos tx, target: 1.08, found 1.12 x 1 = 1.12
[pdriver/__init__]: creating pdriver pdriver_3
[pnand2/__init__]: creating pnand2 structure pnand2_0 with size of 1
[pgate/bin_width]: binning nmos tx, target: 0.72, found 0.74 x 1 = 0.74
[pgate/bin_width]: binning pmos tx, target: 1.08, found 1.12 x 1 = 1.12
[delay_chain/__init__]: creating delay chain [4, 4, 4, 4, 4, 4, 4, 4, 4]
[pinv/__init__]: creating pinv structure pinv_12 with size of 1
[pgate/bin_width]: binning nmos tx, target: 0.36, found 0.36 x 1 = 0.36
[pgate/bin_width]: binning pmos tx, target: 1.08, found 1.12 x 1 = 1.12
[control_logic/__init__]: Creating control_logic_r
[dff_buf_array/__init__]: Creating dff_buf_array_0
[pdriver/__init__]: creating pdriver pdriver_4
[pinv/__init__]: creating pinv structure pinv_13 with size of 6
[pgate/bin_width]: binning nmos tx, target: 2.16, found 1.26 x 2 = 2.52
[pgate/bin_width]: binning pmos tx, target: 6.4799999999999995, found 7.0 x 1 = 7.0
[pgate/bin_width]: binning nmos tx, target: 1.26, found 1.26 x 1 = 1.26
[pgate/bin_width]: binning pmos tx, target: 7.0, found 7.0 x 1 = 7.0
[pinv/__init__]: creating pinv structure pinv_14 with size of 18
[pgate/bin_width]: binning nmos tx, target: 6.4799999999999995, found 7.0 x 1 = 7.0
[pgate/bin_width]: binning pmos tx, target: 19.439999999999998, found 7.0 x 3 = 21.0
[pgate/bin_width]: binning nmos tx, target: 7.0, found 7.0 x 1 = 7.0
[pgate/bin_width]: binning pmos tx, target: 7.0, found 7.0 x 1 = 7.0
[graph_util/get_all_paths]: Paths found=4
[characterizer.functional/set_internal_spice_names]: s_en name = xsram.s_en0
[characterizer.functional/set_internal_spice_names]: bl name=xsram.xbank0.bl0_0, br name=xsram.xbank0.br0_0
[characterizer.functional/set_internal_spice_names]: q name=xsram.xbank0.xreplica_bitcell_array.xbitcell_array.xbit_r0_c0.Q
qbar name=xsram.xbank0.xreplica_bitcell_array.xbitcell_array.xbit_r0_c0.Q_bar
[characterizer.simulation/add_noop_all_ports]: Idle during cycle 0 (0ns - 10ns)
[characterizer.simulation/add_write_one_port]: Writing 0000 to address 11010 (from port 0) during cycle 1 (10ns - 20ns)
[characterizer.simulation/add_read_one_port]: Reading 0000 from address 11010 (from port 1) during cycle 2 (20ns - 30ns)
[characterizer.simulation/add_write_one_port]: Writing 0110 to address 10111 (from port 0) during cycle 3 (30ns - 40ns)
[characterizer.simulation/add_read_one_port]: Reading 0000 from address 11010 (from port 1) during cycle 4 (40ns - 50ns)
[characterizer.simulation/add_write_one_port]: Writing 0101 to address 10000 (from port 0) during cycle 5 (50ns - 60ns)
[characterizer.simulation/add_write_one_port]: Writing 1101 to address 00101 (from port 0) during cycle 6 (60ns - 70ns)
[characterizer.simulation/add_read_one_port]: Reading 0000 from address 11010 (from port 0) during cycle 8 (80ns - 90ns)
[characterizer.simulation/add_write_one_port]: Writing 0000 to address 10100 (from port 0) during cycle 9 (90ns - 100ns)
[characterizer.simulation/add_read_one_port]: Reading 0101 from address 10000 (from port 1) during cycle 9 (90ns - 100ns)
[characterizer.simulation/add_read_one_port]: Reading 0000 from address 11010 (from port 1) during cycle 10 (100ns - 110ns)
[characterizer.simulation/add_read_one_port]: Reading 0110 from address 10111 (from port 0) during cycle 12 (120ns - 130ns)
[characterizer.simulation/add_read_one_port]: Reading 0000 from address 11010 (from port 1) during cycle 12 (120ns - 130ns)
[characterizer.simulation/add_read_one_port]: Reading 1101 from address 00101 (from port 0) during cycle 13 (130ns - 140ns)
[characterizer.simulation/add_read_one_port]: Reading 0000 from address 10100 (from port 0) during cycle 14 (140ns - 150ns)
[characterizer.simulation/add_read_one_port]: Reading 1101 from address 00101 (from port 0) during cycle 15 (150ns - 160ns)
[characterizer.simulation/add_read_one_port]: Reading 0000 from address 10100 (from port 0) during cycle 16 (160ns - 170ns)
[characterizer.simulation/add_read_one_port]: Reading 0000 from address 11010 (from port 1) during cycle 16 (160ns - 170ns)
[characterizer.simulation/add_noop_all_ports]: Idle during cycle 18 (180ns - 190ns)

1
compiler/tests/sram_1b_16_1rw_scn4m_subm.log
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@ -1 +0,0 @@
[globals/cleanup_paths]: Preserving temp directory: /home/jesse/output/

9
compiler/tests/sram_1b_16_1rw_sky130.log
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ERROR: file hierarchy_spice.py: line 176: Connection mismatch:
Inst (4) -> Mod (6)
bl_0_0 -> bl0
br_0_0 -> bl1
vdd -> wl0
gnd -> wl1
-> vpwr
-> vgnd